Low Power Design: From Soup to Nuts. Tutorial Outline

Transcription

1 Low Power Design: From Soup to Nuts Mary Jane Irwin and Vijay Narayanan Dept of CSE, Microsystems Design Lab Penn State University ( ISCA Tutorial: Low Power Design Introduction.1 Tutorial Outline 8:30-8:45 8:45-9:05 9:05-9:30 9:30-10:30 10:30-10:50 10:50-12:15 12:15-1:30 1:30-2:30 2:30-3:30 3:30-3:50 3:50-4:30 4:30-4:45 Introduction and motivation Sources of power in CMOS designs Power analysis tools and techniques Gate & functional unit design issues & techniques BREAK Architectural level issues and techniques LUNCH Low power memory system design Software level issues and techniques BREAK Software level issues and techniques, con t Future challenges ISCA Tutorial: Low Power Design Introduction.2 1

2 Why worry about power? -- Heat Dissipation DEC source : arpa-esto From Rabaey, Rabaey, 1995 ISCA Tutorial: Low Power Design Introduction.3 Introduction.3 BATTERY (40+ lbs) Nominal Capacity (Watt-hours / lb) Why worry about power? -- Battery Size/Weight 50 Rechargable Lithium 40 Ni-Metal Hydride Nickel-Cadium Year Expected battery lifetime increase over the next 5 years: 30 to 40% ISCA Tutorial: Low Power Design Introduction.4 Introduction.4 From Rabaey, Rabaey,

3 Why Power Matters Packaging costs; cooling costs Power supply rail design Digital noise immunity Battery life (in portable systems) Environmental concerns» Office equipment accounted for 5% of total US commercial energy usage in 1993» Energy Star compliant systems ISCA Tutorial: Low Power Design Introduction.5 Technology Directions: SIA Roadmap Year Feature size (nm) Logic trans/cm 2 6.2M 18M 39M 84M 180M 390M Cost/trans (mc) #pads/chip Clock (MHz) Chip size (mm 2 ) Wiring levels Power supply (V) High-perf pow (W) Battery pow (W) ISCA Tutorial: Low Power Design Introduction.6 3

4 Chip Power Densities W/cm Hot plate Process (microns) From Borkar,, 1999 ISCA Tutorial: Low Power Design Introduction.7 Figures of Merit Power consumption in Watts» determines battery life in hours» sets packaging limits Peak power» determines power ground wiring designs» impacts signal noise margin and reliability analysis Energy efficiency in Joules» rate at which energy is consumed over time» energy = power * delay (joules = watts * seconds)» lower energy number means less power to perform a computation at the same frequency ISCA Tutorial: Low Power Design Introduction.8 4

5 Power versus Energy Watts Power is height of curve Lower power design could simply be slower Approach 1 Approach 2 Watts time Energy is area under curve Total energy needed to complete operation Approach 1 Approach 2 time ISCA Tutorial: Low Power Design Introduction.9 Figures of Merit, con t Power-delay product (PDP) = P av * t p» PDP is the average energy consumed per switching event» lower power design could simply be slower Energy-delay product (EDP) = PDP * t p» takes into account that one can trade increased delay for lower energy/operation» allows one to understand tradeoffs better» higher supplies reduce delay, but increase energy ISCA Tutorial: Low Power Design Introduction.10 5

6 Energy Understanding Tradeoffs b Lower EDP c a d 1/Delay ISCA Tutorial: Low Power Design Introduction.11 EDP Plot Energy-Delay Energy 5 Energy-Delay (norm) Delay V DD (V) ISCA Tutorial: Low Power Design Introduction.12 6

7 Notebook Power Usage Stats 16% 8% 52% 2% 12% V Notebook PC Motherboard Hard Disk Floppy Disk LCD/VGA Power Supply From Roy, 1997 ISCA Tutorial: Low Power Design Introduction.13 Processor Power Budgets Clock Datapath Memory I/O (pads) Inner circle: low end embedded microprocessor Next circle: high end CPU with on-chip cache Next circle: MPEG2 decoder ASIC Outer circle: ATM switch ASIC ISCA Tutorial: Low Power Design Introduction.14 7

8 Key References Borkar, Design Challenges of Technology Scaling, IEEE Micro, Aug Chandrakasan, Broderson, Low Power Digital CMOS Design, KAP, Pedram, Power minimization in IC design, ACM TODAES, 1(1):3-56, Proceedings of ACM/IEEE Symposium on Low Power Electronics and Design (SLPED), Rabaey, Digital Integrated Circuits, Prentice-Hall, Rabaey, Pedram, Low Power Design Methodologies, KAP, SIA Roadmap, notes.sematech.org/ntrs/pubintrs.nsf Tiwari, Reducing power in high-performance microprocessors, DAC, Yeap, Practical Low Power Digital VLSI Design, KAP, ISCA Tutorial: Low Power Design Introduction.15 8