QDR SRAM DESIGN USING MULTI-BIT FLIP-FLOP M.Ananthi, C.Sathish Kumar 1. INTRODUCTION In memory devices the most

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1 International Journal of Avance Research in Electronics an Communication Engineering (IJARECE) ABSTRACT: QDR SRAM DESIGN USING MULTI-BIT FLIP-FLOP M.Ananthi, C.Sathish Kumar 1. INTRODUCTION In memor evices the most In memories the power important factor is power consumption. Because the power consumption of the memor evice increases means, the evice reliabilit an life time is reuce. B using the arra of flip-flops the SRAM is esigne. The clock network of the flip-flop consumes more power. To reuce this power, the Single- Bit Flip-Flop (SBFF) is replace b Multi-Bit Flip-Flop (MBFF). While esigning the memor b using SBFF means it consumes more power. So MBFF is use to esign the memor. The general tpe of SRAM performs a single operation (Rea or Write) in each clock pulse, epening on its control signal. To overcome this limitation, QDR SRAM is esigne. It has man real time applications like high spee communications, militar applications, etc. In here QDR SRAM is esigne b using MBFF. consumption is one of the major problems. To optimize the power consumption man techniues are propose. Multi-Bit Flip- Flop is one of the main techniue to minimize the clock network power[10]. The Multi-Bit Flip-Flop oes not reuce the number of flip-flops, it onl reuces the number of inverters in clock networks. Memor is classifie as Ranom access memor (RAM) an Rea onl memor (ROM). Compare to ROM, RAM is the fastest access memor. RAM is classifie as SRAM an DRAM. B using the flip-flops the SRAM is esigne. Depening on feature the SRAM is classifie as ZBT, DDR SRAM, QDR SRAM. 2. MULTI-BIT D FLIP-FLOP: The Single-Bit D Flip-Flop consist one master latch, slave latch an two inverters in clock network. These two inverters consume more power compare to others. To reuce this power consumption Kewors: Single-Bit Flip-Flop, Multithe SBFF is replace b MBFF[8]. Fig.1 Bit Flip-Flop, QDR SRAM. shows the 4-bit D flip-flop. It shares the 2 Manuscript receive on March 20, inverters to all flip-flops. So 6 inverters are M.Ananthi,ME(VLSI Design),Srinivasan save compare to original one. Engineering college, perambalur, Inia. C.SathishKumar, Assistant Professor, Srinivasan Engineering college, Perambalur, Inia. ISSN: X All Rights Reserve 2015 IJARECE 614

2 r International Journal of Avance Research in Electronics an Communication Engineering (IJARECE) [0] [0] bar[0] 3. SRAM: The ata storage in SRAM epens on the.c source. If the.c is remove clock NOT 8 NOT 9 means, the ata can be erase. The SRAM [1] [1] bar[1] is entirel ifferent into DRAM, because DRAM nees refreshing ccle. B using the Multi-Bit Flip-Flops the SRAM is [2] [2] esigne. To esign 4x4 SRAM, it nees 4 Multi-Bit Flip-Flop. The general SRAM bar[2] architecture is shown in Fig.3. [[3] [3] bar[3] 4 Fig.1. 4-bit D flip-flop The 4 bit flip-flop has 2 inputs an 1 output. The inputs are ata input () an a0 a1 ec a0 a1 5 4 clock input () an ata output (). The 6 output for Multi-bit (4-bit) flip-flop is shown in Fig o3 o2 o1 Fig.2. 4-bit flip-flop output The MBFF has man avantages. That is i. Area an ela is reuce. ii. Number of inverters is reuce in clock sinks. So total power consumption is reuce. o0 Fig.3. SRAM esign using MBFF The architecture of the SRAM consist one ecoer, 4 AND gates, 4 MBFF an 4 multiplexer. It has 4 bit ata inputs (,,,) an 2 aress lines (a0,a1) an one control signal (r). The ecoer is use to generate the aress lines. B using this aress lines the flipflop is select to write or rea the ata. The ISSN: X All Rights Reserve 2015 IJARECE 615

3 International Journal of Avance Research in Electronics an Communication Engineering (IJARECE) operation of the SRAM is, when r=0, the write operation is one. When r=1, the rea operation is performe. The output for SRAM using MBFF is shown in Fig.4. of inverters in clock sinks. So the QDR SRAM is esigne b using Multi-Bit Flip-Flop. The QDR SRAM architecture is shown in Fig.5. ctrlwa out v ref wps v ref wps 4 8 Fig.4. SRAM output 4. QDR SRAM: This QDR SRAM is esigne for high spee communications an networking applications. This technolog was introuce b cpress an micron. After that it is followe b IDT then NEC, Samsung, Renesas[7]. In general SRAM an one operation is performe in a single clock pulse. It is the biggest limitation of the general SRAM. Depening on the feature the SRAM is classifie as, Zero Bus Turn aroun (ZBT), snchronous bu (SncBu), Double Data Rate (DDR) SRAM, Qua Data Rate (QDR) SRAM. ZBT efines about the latenc as zero, in between write an rea ccle. SncBu is use to increase the write operation. DDR SRAM has ouble ata rate, but it has single rea/write port. But the QDR SRAM has separate rea/write port with ouble ata rate[6]. B using the SBFF the QDR SRAM is esigne. But the SBFF consumes more power because a0w ec ge a0 a1 k k cout kbar kbar of f of f bar 9 a1w a1r a0r ctrlra c c outr cbar cbar rps rps Fig.5. QDR SRAM using MBFF The architecture consist separate rea an write ports. For that it has separate aress inputs for Rea an Write operation. To control the rea an write operation it has two control signals name as RPS an WPS. B using the registers, the ata inputs an aress lines are connecte to the memor arra. The memor arra is esigne b using MBFF. Depening on the control signals the rea an write operation is simultaneousl performe [5]. The output for QDR SRAM is shown in Fig.6. It performs both rea an write operations in simultaneousl. ISSN: X All Rights Reserve 2015 IJARECE 616

4 International Journal of Avance Research in Electronics an Communication Engineering (IJARECE) Fig.6. QDR SRAM using MBFF output 5. CONCLUSION The Single-Bit Flip-Flop consumes more power because of inverters in clock sinks. To reuce this power consumption MBFF is esigne. In here Quartus II 8.0 (32 bit) tool is use to esign the MBFF an SRAM. Previousl, the general SRAM was esigne b using both SBFF an MBFF. The SBFF SRAM issipates the power as mw an MBFF SRAM issipates the power as mw. So, 0.23 mw power issipation is reuce. But it performs a single operation either Rea or Write in single clock pulse. To perform both operations, the architecture nees to work in twice. So the power issipation is also twice from original one. So the QDR SRAM using MBFF architecture is propose. The QDR SRAM performs simultaneous rea an write operation in single clock ccle. So the total power issipation is reuce 50% of the original one. In future the size of the memor will be increase. REFERENCES [1]. An-Chi CHANG. an Ting-Ting HWANG. (2012) Snthesis of Multi-Bit Flip-Flops for Clock Power Reuction Interisipilinar Information science., Vol 18, pp [2]. G.K.Kharate. (2010) Digital Electronics, Oxfor higher eucation. [3]. Hiroshi Kawaguchi. an Takaasu Sakurai. (1998) A Reuce Clock- Swing Flip-Flop (RCSFF) for 63% Power Reuction IEEE Journal of Soli-State Circuits., Vol 33, pp [4]. [5]. [6]. Data_Rate_SRAM [7]. x.htm [8]. Linc.J. an Sivakumar Rajamani.P. (2013) Low Power SRAM Design Using Multi-Bit Flip-Flop International Journal of Technolog Enhancement an Emerging Engineering Research., Vol 2, pp [9]. M.Morris Mano (2009) Digital esign, thir Eition., Pearson prentice hall. ISSN: X All Rights Reserve 2015 IJARECE 617

5 International Journal of Avance Research in Electronics an Communication Engineering (IJARECE) [10]. Mark Po-Hung, Chih-Cheng an Yao-Tsung Chang. (2011) Post- Placement Power Optimization with Multi-Bit Flip-flops IEEE transactions on Computer-Aie Design of Integrate Circuits an Sstems., Vol 30, pp [11]. Paul E. Gronowski, William J. Bowhill, Ronal P. Preston, Michael K. Gowan an Ran L. Allmon. (1998) High-Performance Microprocessor Design IEEE Journal of Soli-State Circuits., Vol 33, pp [12]. Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo an Wai-Kei Mak. (2012) Power-Driven Flip-Flop Merging an Relocation IEEE transactions on Computer-Aie Design of Integrate Circuits an Sstems., pp [13]. Ya-Ting Shu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin an Soon-Jh Chang. (2013) Effective an Efficient Approach for Power Reuction b Using Multi-Bit Flip-Flop IEEE transactions on Ver Large Scale Integration (VLSI) sstems IEEE transactions on Ver Large Scale Integration (VLSI) Sstems., Vol 21, pp [14]. Yongseok Cheon, Pei-Hsin Ho, Anrew B. Kahng, Sherief Rea, Qinke Wang. (2005) Power- Aware Placement Proc. Design Autom, Conf., pp Fi Author M.Ananthi receive the Bachelor s egree from Oxfor Engineering College Trich, Inia an oing Masters egree in VLSI Design at Srinivasan Engineering College Perambalur, Inia. Secon Author C.SathishKumar receive the Bachelor s egree from Seethai Ammal Engineering College, Sivagangai, Inia an oing Masters egree in Dhanalakshmi Srinivasan Engineering College Perambalur, Inia. He is currentl an Assistant Professor with the Department of Electronics an Communication Engineering, Srinivasan Engineering college, Perambalur. ISSN: X All Rights Reserve 2015 IJARECE 618