Synthesis of Reversible Sequential Elements*

Transcription

1 4-4 Snthesis of Reversible Sequential Elements* Min-Lun huang hun-yao Wang epartment of omputer Science, National sing Hua Universit, Hsinhu, aiwan R.O.. Abstract o construct a reversible sequential circuit, reversible sequential elements are required. his work presents novel designs of reversible sequential elements such as,, and. Based on these reversible es, we also construct the designs of the corresponding flip-flops. omparing with previous work, the implementation cost of our new designs, including the number of gates and the number of garbage outputs is considerabl reduced. I. Introduction Power consumption is a ver important issue in modern VLSI designs. Part of the problem of power dissipation is resulted from the technological nonidealit of switches and materials. herefore, fabrication processes have been continuall improved to reduce power dissipation. he other part of the problem arises from Landauer s principle [5]. Landauer's principle states that logic computations that are irreversible necessaril generate at least k log 2 oules of heat energ for ever bit of information loss, where k is Boltzmann's constant and the absolute temperature at which computation is performed. his part of energ dissipation is independent of what the underling technolog is. Although power dissipation due to information loss is negligible under current technologies, this part of energ dissipation would become essential in 22 or earlier if the Moore s Law continues being in effect [2]. his is due to the increasing densit in computer hardware. People believe that there will be more than 7 logic devices packed in a cubiccentimeter [] in the future. herefore, 7 conventional devices operating at room temperature (=3 k), at a frequenc of GHz would dissipate more than 3,, Watts of power. Moreover, a computer with, times as man logic elements would still be of reasonable size, but it would dissipate 3,,, Watts of power []. Reversible computing does not result in information loss during the computation process. hus, it naturall takes care of heating generated due to information loss. Bennett [] shows that zero energ dissipation would be possible onl if the gates in a network are all reversible. As a result, reversibilit will become an essential propert in future *his work was supported in part b RO National Science ouncil under Grant NS94-22-E-7-2 z z Figure : 3-bit offoli gate truth table; smbol. circuit design. Reversible logic has been applied to various future technologies, such as ultra-low-power MOS design [6], optical computing [3], quantum computing [2], and nanotechnolog [6]. hese technologies eploit reversible gates to reduce the power consumption [3]. o realize a function with reversibilit, man reversible logic snthesis algorithms have been proposed in [4][8][9][3][9]. But most of them address this issue from the aspect of combinational logic. o snthesize reversible sequential circuits, reversible sequential elements such as es and flip-flops are necessar. hus, this paper proposes novel designs of reversible sequential elements such as clocked, clocked, and clocked. he corresponding flip-flop designs are also introduced. he remainder of this paper is organized as follows. In Section 2, we introduce the background of reversible logic. In Section 3, we review some eisting implementations of reversible sequential elements. hen we propose our new designs of these reversible sequential elements and verif the functionalities of them in Section 4. he statistics and comparison of these new designs and previous work are presented in Section 5. Section 6 concludes the work. II. Background efinition : A gate is reversible if and onl if the (Boolean) function is bijective. It means that a reversible function f:(, 2,, n ) (, 2,, m ) satisfies the condition of one-to-one and onto mapping between the input and output domains. It is obvious that the conventional logic gates are almost irreversible. Among the commonl used gates, onl NO gate is reversible. AN gate and OR gate are irreversible because the violate the requirement of reversible function. One wa to make the AN function reversible is to add one z z /7/$2. 27 IEEE. 42

2 4-4 input and two outputs as shown in Figure. he AN function can be obtained in the third output column z of Figure, when setting z =. he truth table of AN function is shown in bold. efinition 2: A garbage bit is an additional output that makes an n-input m-output function reversible. In the reversible AN function as shown in Figure, the outputs, are garbage outputs which are used to make the function reversible. A set of reversible gates is needed to snthesize reversible circuits. Several reversible gates have been proposed in the centuries. Here we introduce offoli gate and Fredkin gate because the will be used in our work. offoli gate: he truth table of 3-bit offoli gate is shown in Figure and its smbol is shown in Figure [2]. he function of the third column is z. hat means when ==, the output is z, otherwise the output is z. his gate can be used to realize a 2-input reversible AN function b setting z as a constant as mentioned. A offoli gate can be generalized as OF(;), where is a set of control variables {, 2,, n- }, is a target variable { n } and = Ø. OF(, 2,, n- ; n ) is a gate which maps a Boolean pattern (, 2,, n-, n ) to (, 2,, n-, 2... n- n ). Fredkin gate: Fredkin gate is also called controlled SWAP gate. Figure 2 is the smbol of Fredkin gate and Figure 2 is its truth table [2]. Its behavior can be described as follows: if the control bit is set to, the outputs of and z are swapped, otherwise the remain unchanged. z z z z z z z z Figure 2: Fredkin gate smbol; truth table. A restriction on reversible logic snthesis has to be followed [8]: he fanout count of a signal net must equal one. If two copies of one signal are needed, a duplication is necessar. his restriction is due to the fact that fanout structure itself is not reversible. For fanout, the number of input signal is one, but there are two or more output signals. herefore, for this restriction, we use a 2-bit offoli gate (also called Fenman gate) to duplicate a signal. he smbol of a 2-bit offoli gate and its truth table are shown in Figure 3 and 3, respectivel. he function of the second output column is. If is set as a constant, a cop of input variable will be obtained in the second output, which is shown in bold. herefore, the fanout structure in a conventional network can be implemented in this wa. here are two objectives in reversible circuit snthesis:. Minimize the number of gates: the number of gates gives a simple estimation of the implementation cost of a reversible circuit. 2. Minimize the number of garbage outputs: we need etra implementation cost (area and power) for those garbage outputs in reversible circuits. Minimizing the number of garbage outputs leads to minimizing area and power. III. Previous Work Fredkin and offoli [2] discussed some topics about reversible sequential network and first introduced a sequential element in the form of flip-flop. However, the did not discuss other popular sequential elements such as, flip-flop, etc. Picton [4] proposed a new design of reversible RS without clock signal. his work decomposes a clockless RS into two conventional NOR gates as shown in Figure 4. hen each NOR gate is replaced b a Fredkin gate, which can implement the function of NOR gate. his new structure of RS is considered reversible because it is entirel constructed b reversible gates as shown in Figure 5. In this work, the did not discuss other reversible sequential elements either. S R Figure 4: he traditional RS. Figure 3: 2-bit offoli gate smbol; truth table. Figure 5: he reversible RS proposed b Picton [4]. A recent work proposed b haplial et al. [7] eploited similar approach, direct transformation, to design other sequential elements such as,, etc. In addition, not onl Fredkin gate, but also some other reversible gates are used to implement conventional logic gates such as NOR gate, AN gate, etc. Although man reversible sequential S R Fanout structure 42

3 4-4 elements are considered in this work, the implementation cost of them is quite large because the did not further optimize these reversible sequential elements. Rice [5] recentl proposed a new design of reversible RS to avoid fanout structures in the original reversible RS design proposed in [4]. he new structure of reversible RS is shown in Figure 6. Moreover, since some other sequential elements such as flip-flop, flip-flop, and flip-flop can be built b RS, this work constructs other reversible sequential elements based on this new reversible RS design. irect transformation approach is also adapted in this work to design sequential elements. hese three work all use direct transformation approach to design reversible sequential elements. irect transformation approaches, however, would cause a large number of gates and garbage outputs required. herefore, this paper proposes a new approach to the construction of reversible sequential elements. S R Figure 6: he reversible RS proposed b Rice [5]. IV. Novel esigns of Reversible Sequential Elements his section presents our new designs of reversible sequential elements. Also, our approach to getting these results is introduced in detail. A. locked Reversible Latches Our snthesis method is a truth table etension method. Unlike the direct transformation based method, we do not replace those irreversible gates with the reversible ones within a sequential element. Alternativel, we etend the original irreversible truth table of a sequential element to an augmented reversible one. We take as an eample. First, we get the truth table of and make it reversible. Obviousl, the truth table of in able is not a reversible function. he mapping between the input and output domains is not one-to-one. herefore we have to add some garbage outputs to make it reversible. he minimum number of garbage outputs required for reversibilit is log(q), where q is the maimum number of times an output pattern repeated in the truth table [7]. In this case, and are repeated 4 times in the output column +. herefore, we add log(4) =2 output variables and in the truth table and make the table reversible as shown in able 2. Note that different values assigned to these two output columns will affect the result of our design. Under our assignments in able 2, we observe that able 2 is identical to Figure 2. hus, a can be modeled b a Fredkin gate. his means we onl need one Fredkin gate to implement a reversible. However, if we assign these values in different was, the design ma be different. able : he truth table of. able 2: he augmented reversible truth table of. + + omparing with previous work, if we use direct transformation method to implement reversible, the snthesis result would be not good. his is because a traditional is built b man irreversible gates, using direct transformation method to construct a reversible will cause a large number of gates and garbage outputs required. After snthesizing this augmented reversible function, we need to consider the fanout problem. he input in the net state comes from the current output +. hus, an additional + is needed for feedback. Here a Fenman gate is used to duplicate the output variable +. hus, the final structure of is shown as Figure 7. Figure 7: he complete implementation of reversible. We verif if this reversible design eactl implements the behavior of a. he leftmost part of Figure 8 shows the Boolean functions obtained from the augmented truth table of in able 2. o simplif the epression of Boolean equations, the smbol is used to represent input variable. he rightmost part of Figure

4 4-4 shows the functions of implemented reversible. hese two epressions are identical, therefore, the functionalit of our reversible is correct. = + = = + = + n Figure 9: structure; functional verification; (c) the augmented truth table. Similarl, a reversible can be modeled as a offoli gate using the same method. he implementation of reversible is shown in Figure 9. Figure 9 shows the verification result. Figure 9(c) is the augmented truth table. As for, because its function is quite comple, it is not eas to model its function using a single reversible gate. herefore, we eploit a transformation based snthesis algorithm [9] to construct the reversible. First, we also derive the augmented reversible truth table as shown in able 3. hen, we appl the transformation based snthesis algorithm to implement the reversible function. he philosoph of the transformation based algorithm is to cascade some reversible gates such that the output of the truth table is equal to the input. Net, we describe how to construct our reversible in detail. able 3: he augmented reversible truth table of = n n = + = = = Figure 8: Functional verification on reversible. + (c) First, we inspect the augmented truth table in the leicographical order until the first output assignment differs from the input assignment. he first output assignment which is not equal to input assignment in able 3 is. hen we want to add some generalized offoli gates from the end of constructed circuit towards its beginning to make the output assignments be equal to input assignments. here are two rules when we choose a generalized offoli gate.. eal with those bits that should become to first: we want to change the output assignment to. Hence the 2 nd bit should be changed from to and the 4 th bit should be changed from to. herefore, we deal with the 4 th bit first. 2. Remain the output assignments which are prior to the current one intact: the output assignments prior to are identical to their corresponding input assignments, so we leave them unchanged. Using OF(,, ;+ ) or OF(, ;+ ) are effective to invert the 4 th bit of and leave the output assignments prior to it unchanged. In our design, we choose a OF(, ;+ ) and add it to the end of constructed circuit in this iteration. Note that this process might change other output assignments after, such as or. Nevertheless, we can reform them in the same wa in the later iterations. In each step, we choose an appropriate generalized offoli gate to snthesize the reversible function according to these two rules. he algorithm is terminated until all of the output assignments are equal to the input assignments. Figure shows the process of snthesizing this reversible. After adding a generalized offoli gate in each step, we show those changed output assignments in bold. Note that the gates are identified sequentiall from the output side to the input side. he resulting circuit has to be reversed and is shown in Figure, and the final structure of reversible is shown in Figure. he verification of reversible is shown in Figure 2. We use Figure 3 to illustrate the structure of a reversible sequential circuit with the new proposed reversible es. he combinational part and the sequential elements of a reversible sequential circuit have In Out S S2 S3 S S2 S3 Figure : he snthesis process of reversible. 423

5 4-4 = + = ( ) = + =( ) = = Figure 2: Functional verification on reversible. Figure : the reversible transition function; the complete implementation * * inv + + Figure5: flip-flop behavior; structure. + + Reversible ombinational Reversible Logic z A z A A A A +A A A A B B Reversible to be reversible. he clock signal of each reversible sequential element would be pulsed b a global clock source. B. locked Reversible Flip-Flops A flip-flop is an edge-triggered sequential element while a is a level sensitive sequential element. A traditional flip-flop consists of two es and one inverter, and is shown in Figure 4 [].he first is called the master and the second one is called the slave. Since a reversible has been built, a reversible flip-flop can be constructed directl b replacing the es and inverter with its reversible versions. he behavior and structure of a reversible flip-flop are shown in Figure 5 and Figure 5, respectivel. We can trace the flip-flop design and compare the function with its truth table. he behavior of implemented flip-flop is the same as that of the truth table in Figure 5. he implementations of reversible flip-flop and flip-flop are shown in Figure 6 and Figure 7, respectivel. B B B B B +B B Figure 3: An illustration of reversible sequential network. (master) inv (slave) Figure 4: An irreversible conventional flip-flop. + * * Figure6: flip-flop behavior; structure. + * * * * V. he iscussion of Results able 4 shows the statistics and comparison of our new designs against that proposed in [7]. able 5 is another statistics and comparison of our designs against another work proposed in [5]. In these two tables, column shows the tpes of the sequential element. We use the number of gates and the number of garbage outputs as the cost functions to measure the qualit of a design. Each table is separated into two parts b these two costs and each part has three columns. In able 4, the column Ours shows the cost of our design. he column [7] shows the cost reported in [7]. he Figure7: flip-flop behavior; structure

6 4-4 able 4: he statistics and comparison of our new designs and previous work [7]. pes NO. of gates NO. of garbage outputs Ours [7] Ratio (%) Ours [7] Ratio (%) flip-flop Average able 5: he statistics and comparison of our new designs and previous work [5]. pes NO. of gates NO. of garbage outputs Ours [5] Ratio (%) Ours [5] Ratio (%) flip-flop flip-flop flip-flop Average column Ratio is the percentage of Ours/[7]. For eample, for a design, our implementation has 2 gates while [7] has 7 gates. he ratio is 2/7=28.6%. he last row Average shows the averaged ratio among these different reversible sequential elements. In [5], the do not summarize these two kinds of implementation costs of their reversible sequential elements. We count these numbers based on their designs and show them in able 5. According to the statistics in able 4 and able 5, the implementation cost of our designs is smaller than that of these two previous work. VI.onclusion his paper proposes novel designs of basic reversible sequential elements such as es and flip-flops. he design process is also introduced in detail. As comparing with previous work, the implementation costs of these new designs are more competitive. hus, the resulting reversible sequential circuits are more cost efficient. References []. Bennett, Logical reversibilit of computation, IBM ournal of Research and evelopment, 7: pp , 973. [2] E. Fredkin and. offoli, onservative logic, International ournal of heoretical Phsics, 2:pp , 982. [3] E. nill, R. Laflamme, and G.. Milburn, A scheme for efficient quantum computation with linear optics, Nature, pp , 2. [4] P.erntopf, A new heuristic algorithm for reversible logic snthesis, in Proc. of the IEEE esign Automation onference, pp , 24. [5] R. Landauer, Irreversibilit and heat generation in the computational process, IBM ournal of Research and evelopment, 5: pp. 83-9, 96. [6] R.. Merkle, wo tpes of mechanical reversible logic, Nanotechnolog, 4:pp. 4-3, 993. [7]. Maslov and G. W. ueck, Garbage in reversible design of multiple output functions, in Proc. of 6th International Smposium on Representations and Methodolog of Future omputing echnologies, pp. 62-7, 23. [8]. M. Miller, Spectral and two-place decomposition techniques in reversible logic, in Proc. of the IEEE Midwest Smposium on ircuits and Sstems, pp. II493 II496, 22. [9]. M. Miller,. Maslov, and G. W. ueck, A transformation based algorithm for reversible logic snthesis, in Proc. of the IEEE esign Automation onference, pp , 23. [] M. M. Mano, omputer engineering: hardware design, Prentice-Hall, Englewood liffs, N, 988. [] R.. Merkle, and. reler, Helical logic, Nanotechnolog, 7: pp , 996. [2] M. Nielsen and I. huang, uantum computation and quantum information, ambridge Universit Press, 2. [3] M. Perkowski, L. oziwak, A. Mihchenko, A. Al-rabadi, A. oppola, A. Buller, X. Song, M. han, S. Yanushkevich, V. P. Shmerko, and M. hrzanowska-eske, A general decomposition for reversible logic, in Proc. of Reed-Muller Workshop, pp. 9-38, 2. [4] P. Picton, Multi-valued sequential logic design using Fredkin gates, Multiple-Valued Logic ournal, l.:pp , 996. [5]. E. Rice, A new look at reversible memor elements, in Proc. of the IEEE International Smposium on ircuits and Sstems, 26 [6] G. Schrom, Ultra-low-power MOS technolog, Ph thesis, echnischen Universitat Wien, une 998. [7] H. haplial and M. B. Srinivas, A beginning in the reversible logic snthesis of sequential circuits, in Proc. of Militar and Aerospace Programmable Logic evices International onference, 25. [8]. offoli, Reversible computing, ech memo MI/LS/M-5, MI Lab for omp. Sci, 98. [9] G. Yang, X. Song, W. N.N. Hung, and M. A. Perkowski, Fast snthesis of eact minimal reversible circuits using group theor, in Proc. of the IEEE Asia and South Pacific esign Automation onference, pp. 2-5, 25. [2] V. V. Zhirnov, R.. avin,. A. Hutchb, and G. I. Bourianoff, Limits to binar logic switch scaling a gedanken model, in Proc. of the IEEE, pp ,