EE 101 Lab 7 Crosswalk

Transcription

1 EE 0 Lab 7 Crosswalk Introduction In this lab you will complete the control unit and datapath for a simple crosswalk controller that was discussed in class. You should work on this lab INDIVIDUALLY! 2 What you will learn This lab is intended to teach you how to implement state machines, use datapath components and perform a non-trivial digital design. 3 Background Information and Notes. The Crosswalk Control Unit (FSM) The crosswalk system we will design in this lab is the same as the design covered in lecture. Pedestrians should be allowed to walk for 8 ticks of the clock, followed by a blinking hand (do not start walking) for 6 ticks of the clock. During these 6 ticks, a solid hand will blink on for a tick and then off for a tick while a counter counts down from 8 to decrementing every two clocks. Then the system should display a solid hand continuously for 6 ticks indicating the red light period of the intersection. To implement this sequence, an FSM can be implemented whose state diagram is shown below. C7=0 RESET WALK WALK= EN= C7= BlinkOff NUM_ON= TC= TC=0 TC=0 NOWALK HAND= EN= TC= BlinkOn HAND= EN= NUM_ON= Figure - Crosswalk System State Diagram In the state diagram, C7 is an input to the state machine that should be generated from a 4-bit counter indicating the count is equal to 7 = 0 2. TC is also generated from the counter indicating the Terminal Count (for a 4-bit counter = 2 ) has been reached. Last Revised: /3/204

2 The outputs of the entire design are described in the table below: Output CNT(3:0) WALK HAND NUM_ON NUM(3:0) Description The current value of the 4-bit counter (for debug purposes only) Output to control when the walk icon should appear on the display. For our system we will use LED 3 and a 7- Segment display with the letter G for Go to indicate the walk state. Output to control when the hand icon should appear (either during its blinking phase or solid phase). For our system we will use LED and a 7-Segment display with the letter S for Stop to indicate the blinking or nowalk state. Output to control whether the don t walk countdown timer should be displayed. Value of the don t walk countdown timer. Table - Crosswalk System Outputs 7-Seg. 7-Seg. 2 7-Seg. 4 NUM(3:0) NUM(3:0) S = Stop G = Go / Walk LED LED3 NUM_ON HAND WALK NUM_ON HAND WALK Figure 2 - Traditional Crosswalk Display and our modified FPGA I/O display Note: The state machine controller includes another output, EN, that is used in the datapath to control the counter but is not an output of the overall system. 2. The Crosswalk Datapath To help implement the overall system we will need a few datapath components. The first one that has already been mentioned is a 4-bit counter to keep track of time. The Xilinx tools include a 4-bit counter that is similar to the 74LS63 counter studied in class. It is called the CB4CLE (B=Binary, 4=4-bits, C=Clearable, L=Parallel Load Inputs, E=Enable). A block diagram and function table are shown below. 2 Last Revised: /3/204

3 Notes: CB4CLE D0 Q0 D D2 D3 L CE CLK CLR Q Q2 Q3 CEO TC CLR CLK L CE Q* , - - Q 0 - D 0 0 Q Q TC = Q3 Q2 Q Q0 CEO = TC CE Figure 3 - Block Diagram and Function Table for 4-bit CB4CLE Counter Unlike the 74LS63, TC for the CB4CLE is a Moore-style output that checks if the Q value is at the maximum count = 2, while the CEO (Count Enable Out) is a Mealy output that corresponds to the TC output of the 74LS63. For this design we will use the TC output of the counter. Information on a Xilinx component can always be found by right-clicking on the symbol and selecting Symbol..Symbol Info. In addition to the counter, a 4-bit adder will be needed to generate the countdown digit to be displayed on the seven segment display. We will use the basic ADD4 component. Note that it produces an output OFL = Overflow and CO = Carry-out that we will not need in this design. This adder is necessary because we have a counter counting up from 0-5 0, while we want a single digit counting down from 8-0. Think how you can achieve this conversion using the current count and the adder. 4 Procedure You will design and implement the crosswalk system including the control unit / FSM and the datapath. A testbench will be provided to give some confidence that your system is working. Then you will implement the design on the FPGA board to see it in action.. Download the ee0_lab7_cwalk project.zip file from Blackboard. Extract the files to a folder. 2. The crosswalk project has a completed top-level schematic, a skeleton datapath schematic (ee0_lab7_cwalk.sch) and a skeleton control unit / state machine schematic (ee0_lab7_cwalk_fsm.sch). The top-level schematic generates a slower clock signal, the reset signal, as well as converting all the outputs to appropriate 7-Segment display values (i.e. you will output a signal like WALK Last Revised: /3/204 3

4 and our top-level schematic will convert that to G for Go). No changes should be made to the top-level schematic. 3. On paper, design the crosswalk state machine using the state diagram provided in Figure. Use D-FF s and a state assignment of: WALK=00, BLINKOFF=0, BLINKON=, and NOWALK=0. The initial state should be WALK. The inputs C7 and TC should control the transitions. Your outputs should be WALK, EN, HAND, and NUM_ON. 4. Implement your FSM design in the ee0_lab7_cwalk_fsm.sch file (which is under the ee0_lab7_cwalk component under the top-level schematic). Note: The FF s used in this design have an active-high CLR input and we have provided you an active-high reset signal. 5. Open the ee0_lab7_cwalk.sch file. Make the necessary connections to the 4- bit counter (CB4CLE component) grounding unused inputs. Use the counter to generate the C7 signal. The TC signal is already labeled and need not be changed. Also, make the necessary connections to the 4-bit adder compute the output digit to be displayed. 6. Check your schematics and synthesize your design. Fix any errors, but ignore warnings in the top-level design. 7. Simulate your design using the provided testbench. Click over to Simulation, select the ee0_lab7_cwalk_tb and use it to simulate your design. (Note: This simulates your cwalk design, not the top-level design which is complete and valid). Right-click on Simulate Behavioral Model.. Process Properties. Ensure Simulation Run Time is 7500ns or more. Now double-click Simulate Behavioral Model. The testbench runs for 7500 ns which is enough time to go through at least one full Walk, Blinking, Don t Walk sequence. Verify the correctness of your design. 8. Click back to Implementation. Translate and Generate the Programming File. Connect the programming cable to the FPGA board and download/program your design. Ensure it works as you expect. 9. Demonstrate your design to your TA/instructor & get their initials. 5 Review See questions posed in the next section. 4 Last Revised: /3/204

5 6 Lab Report Name(s): Due: Score: (Detach and turn this sheet along with any other requested work or printouts). TA/Instructor initials of completed demo: 2. Turn in a printout of your FSM schematic (ee0_lab7_cwalk_fsm.sch) and crosswalk datapath schematic (ee0_lab7_cwalk.sch). 3. Suppose rather than counting down from 8 to on our display we wanted to count down from 7 to 0. Would you still need an adder, or could you generate NUM[3:0] (really NUM[2:0] since now we just want 7 downto 0) more efficiently? Draw a new, minimal, logic implementation for NUM[2:0] below using any bits of CNT[3:0] as inputs. 4. Understand the difference between the TC and CEO outputs of the CB4CLE counter. Then complete the waveform below assuming CLR, L, and other inputs not shown are inactive. After completing the waveform, answer the following question. Would your state machine operate any differently (go through a different state sequence) if we had used the CEO counter output as the TC input to the state machine rather than the TC output of the counter? Explain. CLK Q[3:0] EN TC CEO Explanation for question about using CEO vs. TC as TC input to FSM. Last Revised: /3/204 5

6 7 EE 0 Lab 7 Grading Rubric Student Name: Item Outcome Score Max. All schematic & waveform hard copies provided FSM Correctness D0 NSL D NSL WALK Output EN Output HAND Output NUM_ON Output Datapath Correctness Counter o Enabled correctly o Count 7 implemented correctly o Other inputs connected safely NUM generation o Input Logic correct Review Questions Q3: New NUM logic is correct Q3: New NUM logic is minimal Q4: TC Output is correct Q4: CEO Output is correct Late Deductions (- pts. per day) Open Ended Comments: SubTotal 5 Total 5 6 Last Revised: /3/204