Lab #10 Hexadecimal-to-Seven-Segment Decoder, 4-bit Adder-Subtractor and Shift Register. Fall 2017

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1 University of Texas at El Paso Electrical and Computer Engineering Department EE 2169 Laboratory for Digital Systems Design I Lab #10 Hexadecimal-to-Seven-Segment Decoder, 4-bit Adder-Subtractor and Shift Register. Fall 2017 Adder-Subtractor Subtraction of binary numbers is most easily accomplished by adding the complement of the number to be subtracted. To compute A B, add the complement of B to A. This gives the correct answer because A + ( B) = A B. Either 1 s or 2 s complement is used depending on the type of adder employed. The 2 s complement can be obtained by taking the 1 s complement and adding 1 to the least significant pair of bits. The 1 s complement can be implemented with inverters, and a 1 can be added to the sum through the input carry. 4-bit Adder-Subtractor (with overflow detection) The circuit for subtracting A - B consists of an adder with inverters placed between each data input B and the corresponding input of the full adder. The input carry C0 must be equal to 1 when subtraction is performed. The operation thus performed becomes A, plus the 1 s complement of B, plus 1.This is equal to A plus the 2 s complement of B. Registers Several D flip-flops may be grouped together with a common clock to form a register. Because each flip-flop can store one bit of information, this register can store four bits of information. This register has a load signal that is ANDed with the clock. When Load = 0, the register is not clocked, and it holds its present value. When it is time to load data into the register, Load is set to 1 for one clock period. When Load = 1, the clock signal (Clk) is transmitted to the flip-flop clock inputs and the data applied to the D inputs will be loaded into the flip-flops on the falling edge of the clock. 1

2 4-bit D Flip-Flop Registers with Data, Load, Clear, and Clock Inputs Shift Register A shift register is a register in which binary data can be stored, and this data can be shifted to the left or right when a shift signal is applied. Bits shifted out one end of the register may be lost, or if the shift register is of cyclic type, bits shifted out one end are shifted back in the other end. 4-bit Right-Shift Register with Serial Input and Output Constructed from D Flip-Flops When Shift = 1, the clock is enabled and shifting occurs on the rising clock edge. When Shift = 0, no shifting occurs and the data in the register is unchanged. The serial input (SI) is loaded into the first flip-flop (Q3) by the rising edge of the clock. At the same time, the output of the first flip-flop is loaded into the second flip-flop, the output of the second flip-flop is loaded into the third flip-flop, and the output of the third flip-flop is loaded into the last flip-flop. Because of the propagation delay of the flip-flops, the output value loaded into each flip-flop 2

3 is the value before the rising clock edge. The timing when the shift register initially contains 0101 and the serial input sequence is 1, 1, 0, 1. The sequence of shift register states is 0101, 1010, 1101, 0110, Register Data Transfer Communications The datapath of a digital system is said to operate in serial mode when information is transferred and manipulated one bit at a time. Information is transferred one bit at a time by shifting the bits out of the source register and into the destination register. This type of transfer is in contrast to parallel transfer, whereby all the bits of the register are transferred at the same time. Parallel Data Transfer 3

4 Serial Data Transfer For this laboratory assignment you will continue working with the code developed on the laboratory 6 assignment. The modifications are as it follows: 1. The 3-bit inputs will become 4-bit inputs 2. The BCD-to-seven-segment decoder will become a Hexadecimal-to-seven-segment decoder. 3. You will add the subtraction operation to the code 4. You will design and show the operation of a 4-bit shift register Pre-Lab Part 1 (HEX to SSD) A Hexadecimal-to-seven-segment decoder is a combinational circuit that converts a hexadecimal digit to an appropriate code for the selection of segments in an indicator used to display the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the corresponding LEDs in the display, as shown in figure below. The numeric display chosen to represent the hexadecimal digit is shown as well. Write the truth table relating the four binary inputs to the 7 LED outputs of the BCD-to-seven-segment decoder. DO NOT use K-Maps. There s no need for logic expressions. Draft the Verilog code using behavioral modeling. Use a Case Statement relating the binary number input to it seven-segment representation. Part 2 (SHIFT LEFT REGISTER) Draft the Verilog code for a 4-bit shift left register with Positive-Edge Clock, Serial In, and Serial Out. Don t forget to properly define the input and sum registers. Hint: Register Verilog Code Examples: Online Compiler: 4

5 Lab Part A Start a new project on Xilinx and named it EE2169Lab7A_Lastname. Use your code from the previous lab exercise as a template. Implement the 4-bit adder-subtractor and seven segment hexadecimal display decoder using Verilog HDL on the NI Digital Electronics FPGA Board (DEFB). Assign switches SW7 SW4 as your binary inputs for one number (LEFT) and SW3 SW0 for the other (RIGHT). The NI FGPA Board has two independent, seven segment displays; assign each input to display the number to be added or subtract. Use the BTN0 for the addition operation and BTN1 for the subtraction operation. Modify the constraints file as necessary. The sum of the two numbers, including the carry over bit, should be displayed on the LED displays. Be aware that if A < B in A-B you will get a negative binary value. Hint: Use If-Else statements for the addersubtractor section. Part B Start a new project on Xilinx and named it EE2169Lab7B_Lastname. Implement an 8-bit Shift-Left Register with Positive-Edge Clock, Synchronous Parallel Load, Parallel In, and Serial Out. Use the code below to setup the system inputs and outputs. Display the loaded data on the LED section of the FPGA Board. Use switches SW3 SW0 for your data. Use BTN3 for your load input and SW7 for your shift left operation. Hint: Use your code from Part 2 of the Prelab as a reference and the constraints file will be provided on the Wiki page. Shift Register Figure 1: Serial Transmitter with Parallel Load //HEADER FILE module EE2169Lab7B_Lastname ( input [3:0] sw, // input switches SW0-SW3 input load, // load BTN3 input shift, // shift input SW7 input clk, // clock input from GPIO29 or GPIO31 5

6 //output out, // Serial data output to GPIO0 output [7:0] ld // LED outputs ); // Internal Registers reg [7:0] shiftreg; reg [3:0] Q; // Serial register outputs // Parallel load register outputs Board Connections: Using the provided jumper cables connect the clock according to the figure below. DO NOT TURN THE DEFB ON UNTIL YOU HAVE SHOWN THE TEACHING ASSISTANT YOUR CONNECTIONS! or clk (GPIO29) The clock (clk) signal: The clock pulse (clock) will be generated by a program called the NI ELVISmx Function Generator on the PC, then routed to the DEFB, we first have to set up the generator to produce the approximately 1Hz TTL square wave needed by the digital circuit. 1. Open the function generator by typing NI ELVISmx Function Generator in the Start Menu. 2. Once, open Select the Square wave button, set the Amplitude to 5Vpp, the DC Offset to 2.5V, and the Frequency to 1Hz. Your set up should look like the figures below. Once ready, hit the Run button. 3. The function generator will look like the image to the right while running. To physically verify you have a 1 sec clock, connect pin 6 on BB4 (FGEN) to any LED pin in BB3 (seven segment LEDs). You should see the LED flash about 1 time per second. 6

7 Extra Challenge (Transmitting the adder-subtractor data) For an Extra Point combine Part A and Part B. Load to the register the result from your adder-subtractor and simulate its transmission on the LEDs using the shift left operation at every clock cycle. It will require the addition of an external LED (under the TAs supervision) to simulate the transmitting bit through GPIO0. Use the switches to input the numbers data and the buttons for the addition, subtraction, load and shift left operations. Hint: Try using only behavioral coding to avoid issues with the FPGA resources. 7