CARLETON UNIVERSITY. Facts without theory is trivia. Theory without facts is bull 2607-LRB

Transcription

1 CARLETON UNIVERSITY Deparment of Electronics ELEC 267 Switching Circuits February 7, 25 Facts without theory is trivia. Theory without facts is bull Anon Laboratory 3.: The T-Bird Tail-Light Control Using a CPLD FIGURE 3. The focal point for this lab: 267-LRB Overview The T-Bird of this lab, has two sets of three tail lights in a row. The direction signals of this car sequence in. Thus before a right turn, the right lights would flash in the following sequence. There is half a second between each step in the sequence. Then the sequence repeats. The lights are controlled by three switches, labeled L, R, and B. Turning on both L and R turns on the emergency flashers. Then all six lights flash are on for half-a-second and off for half-a-second. When L and R are both off, pushing B lights all six lights. If L or R (not both) is on with B, the tail lights on the appropriate side should flash as for a turn. The lights on the other side should be steady light to show braking The steady brake light overrides the ency flashers. L B R Left signal Brake Right signal The designs will use a continuously running clock which is not turned on and off.. Some usually reliable people say this should be a Cougar. SWITCHING CIRCUITS J.Knight, 2/7/5

2 3. A Block Diagram of a Possible Circuit One always tries to design a circuit by partitioning it into smaller circuits. One partitioning gives three subcircuits:. A counter which emits four signals that go on and off at the proper s for controlling the lights. 2 and 3. Left and right control boxes that apply the counter signals to the correct lights. FIGURE 3.shows such a partition. FIGURE 3. The block diagram of a possible implementation of the T-Bird tail lights. BULB_L3 BULB_L2 LEFT CONTROL BOX BULB_L 3-wires in a cable BULB_R BULB_R2 RIGHT CONTROL BOX BULB_R V CLOCK 8 to 6 HZ Lite_! L B Left signal f Clock divider Slows the clock ~ HZ clk COUNTER R Brake Right signal The counter uses a flip-flop to generate the four waveforms from the clock. The control boxes take the waveforms and route them to the proper lights. There are no flip-flops in the control boxes. For example, for the emergency flashers, (L and R both on), the control boxes would send the waveform to all the tail lights. Alternately, when L is on, it would send to BULB_L, to BULB_L2, and to BULB_L3 The COUNTER circuit generates all four waveforms from the square wave, and a halffrequency signal obtained by dividing the clock by two. See FIGURE 3.2. FIGURE 3.2 Inside COUNTER, there is a flip-flop which divides the input clock by two. This gives a signal of half the clock frequency. This and the clock signal are used to generate the other four signals. ency Q = divide by two.s Q The clock is a square wave. The circuit shown here differs slightly from the one you will be building. In the lab, you may have to add the two redundant inverters shown, because the software does not like wires to go directly from an input to an output. Department of Electronics February 7, 25 2

3 3.2 The T-Bird COUNTER Circuit During turns, the lights must sequence - -> -> -> -> {4-state sequence} These are four different sets of output values which come at four different s, the last is a repeat. One must have some way to tell which of the four steps one is in. The signal is a square wave. One can use = to distinguish one interval and = to distinguish another. But this only distinguishes two different intervals. Here we use another signal Q, which runs at half the clock frequency. The combination of the and Q lets us distinguish 4 unique intervals which can be used to generate,, and The Q signal sequence used in FIGURE 3.2 gave the sequence - Q steps: -> -> -> -> This system could be said to have 4 states. Here this is done using the and one flip-flop The Design of The Divide by Two Circuit In order to divide by two, one must have a circuit that can remember. The most common memory element in logic circuits is called the D flip flop. The D Flip-Flop. FIGURE 3.3 Rising edge This flip-flop has two inputs, D and C, and an output Falling edge D Q usually called Q. The C or clock input has a square wave applied to it. The D input receives the signal to be remembered. 3 C indicates D just before the clock rises. When the clock rises (goes from to ) the flip flop output Q will capture the value of the D input just before and at shows how long Q remembers that D. show where Q starts to remember that D the of this rising clock edge. It remember that value of D D for the rest of the clock cycle. After that rising edge, D can change, and the clock can fall back to zero. Nothing will change Q until another rising clock edge. Then, if D has changed, Q will change. Q =C The Divide By Two Circuit The clock is a square wave. The rising clock edge here is called the active edge. This circuit generates a square wave at half the clock FIGURE 3.4 D Q frequency. It does this by making a flip-flop change the Q C value on every second rising clock edge. Q will change if and only if D changes. Values of D needed to make Q run at half the clock frequency. We only care about D just Thus one needs a D signal that inverts every rising clock before and at the rising clock edge (green line) edge. This turns out to be easy to find. Look just before the clock edge. What is the relationship between the desired D and the value of Q before the edge.? D Q =C 2. In ELEC35 you will be taught that the clock should go only to the flip-flop clk inputs, and not to the D input, or gates that feed the D input of other flip-flops. To do otherwise can cause timing problems. The circuits in the lectures all send the clock only to flip-flop clock inputs. However it is all right for the clock to feed gates that only go to outputs, and these gates never fed into the D inputs of other flip-flops. For the T-Bird lights, we save half the flip-flops ( in this case) by letting the clock directly feed the gates that control the output lights. 3. Many flip-flops also have a reset input, R which will come up later. They may also have a Q output. Department of Electronics February 7, 25 3

4 Remember it does not matter where the D signal changes as long as it has the desired value just before and at the rising clock edge. If D changes just after the clock edge, Q does not change. Thus to divide the clock frequency by two one connects Q back to the D input. The Timing Circuit Signals, Q, You will need to work out the exact waveforms for Q and. /2 will have a different phase relationship with, than that shown in FIGURE Fill in the waveform for Q and D in the space given in FIGURE 3.5. Take Q = at the start as shown, and then take D = Q. (D is already done at the start.) () From D at the st clock edge, you can tell what Q will be for the rest of the cycle. (2) From this Q, you can tell what D will be for the rest of the st clock cycle. (3) The D during this first cycle will be the D at the next rising clock edge. From this D you can tell what Q will be for the 2nd clock cycle. (4) Continue; one waveform error will mess up the rest of the lab big. Flip Flop Reset Besides and D, practical flip-flops have one other input called Reset or R. Whenever R= the Q output immediately and unconditionally goes to. You will be connecting your reset pin to a wire called RST which will allow you to reset Q to when you press a button COUNTER Outputs The clock is a square wave. The active clock edge here is the rising edge. D The box called COUNTER has four outputs. Three of the outputs are used to flash the turn signals in the proper sequence. The signal flashes the lights on and off every cycle. If the flashing cycle starts at Q = all four signals should be off. Assuming you got Q = at the end of your flashing sequence, then all three LITE signals and should be on. FIGURE 3.6 Q,,,, Q. s D Q Q = /2 /2 FIGURE 3.5 The signals Q and. One must know exactly where the Q =/2 signal rises, in order to derive the logic to generate the Lite and signals. D=Q,,,,,, Q R divideby two Fill in Q, simultaneously fill in D= Q Table : State Truth table with values of Q shown in sequence Outputs Q From FIGURE 3.5, you can fill in values for Q. From FIGURE 3.6, you can fill in the values for the various LITE_ signals. Department of Electronics February 7, 25 4

5 From the truth table (Table I), derive the equations for the outputs, much like you did in the last two labs. = = = = Q 3.3 The Left Control Box The four inputs from COUNTER to the control box are:,,, and. There are also three switch inputs: L, left turn signal R, right turn signal B, brake Table 2: shows the type of output for the left side, for different switch inputs. From the table, and the Overview on page, it is relatively easy to derive the left-side output signals. Switches B L R Table 2: Flash Turn Sig The Left Side Output Type for Various Switch Inputs Type of outputs for (Left side) Flash Steady Brake Fill in the blank spots. If the L is on alone (BLR) or with B signal (BLR), then flash BULB_L in with the signal. If both L and R are on with no brake (BLR), then flash BULB_L in with the signal. With B and L, hold a steady on BULB_L Also if all three are on (BLR) the brake overrides the ency flashers. These three statements are described in the equation BULB_L = ()(BLR + BLR) + ()(BLR) + (BL R + BLR + BLR) (Equ ) This equation can be reduced easily(?) with a variable entered Karnaugh map as described in the lectures. The variables and, which only appear once each, are entered as variables on the map. This avoids a 32 square 5-variable map. Use the map to reduce the equation to BULB_L = ()LR + ()(BLR) + (BL + BR) If you can t figure out this map, use a 32 square map, or simplify by algebra. In the same way as for (Equ ), the other bulbs should light when: LR B BULB_L2 = ()(BLR + BLR) + ()(BLR) + (BL R + BLR + BLR) (Equ 2) BULB_L3 = ()(BLR + BLR) + ()(BLR) + (BL R + BLR + BLR) (Equ 3) Do a logic reduction on the expressions for BULB_L2 and BULB_L3. Department of Electronics February 7, 25 5

6 3.4 The Prelab (This must be prepared prior the scheduled lab session.). Design the divide-by-two circuit. Draw the schematic. 2. Derive the waveform for Q, the output of the divide-by-two circuit, and D, in relation to the signal; use a rising-edge-triggered flip-flop. 3. Derive the logic to calculate the three Lite_- and the signals from Q and. Draw the circuit. 4. Finish the derivation and simplification of the equations for the Left Control Box relating BULB_L, BULB_L2, BULB_L3 to the B, L and R switches as well as to the three Lite_- and the signals. Q D=Q Draw the circuit.. s 5. Derive the equations for the Right Control Box. Draw the circuit. 6. Look at the sample test fixture file shown on page 6. You will be given a file like that one. How many input combinations can be done with three input switches? Which tests should be added? Write down what must be added to the Test Fixture file to include them. 3.5 In the Laboratory The software used will be the Xilinx ECS Graphic Entry System, and the logic will be simulated using the ModelSim simulator. In your schematics, use the fdc flip-flop symbol You will be then programming hardware on a CPLD (complex Programmable Logic Device), so you can see the lights flashing. Unfortunately a T-Bird is not supplied Simulation The Verilog test fixture file To simulate your circuit, you need a file to generate the clock and switch signals. This file is usually called a test bench file. The ECS software calls it a.tf or test fixture file. This file is given at the end of the lab. // precedes a comment. #3 means a delay of 3 units before the next instruction is simulated. The units for this simulation are seconds, as given by the `scale s / ms command. The delays accumulate., thus #7 x= ; #5 y = ; give a total delay of 2 before the simulator finishes making y zero. The included test fixture file generates signals for only four of the possible button combinations. You must add statements to test the others. Print out a copy of your revised test fixture file (up to the $stop) for your report. Department of Electronics February 7, 25 6

7 Sample Verilog Test Fixture File for the Simulator // Verilog tbirdtestfixture.tf - Feb 5, 25 `scale s / ms // Means # represents a sec delay, min resolvable is ms. (#.) module TBirdTestFixture; // Outputs from your circuit wire BULB_L, BULB_L2, BULB_L3, BULB_R, BULB_R2, BULB_R3; // Inputs to your circuit reg, L, R, B, RST; // Generate a clock initial =; always #.5 =~ initial begin // Set all the switches low initially L=; R=; B=; // An initial reset makes Q = at the start of the simulation. RST = ; #. RST = ; // Set RST high after a. s delay #.7 RST = ; // Set RST low after an additional.7 s delay //Test : No switches on L = ; R = ; B = ; #5 // Delay 5s for a total of 6.8s #3 // Delay 3s for a total of 9.8s //Test : Left signal; // These tests start about sec. L = ; // B and R are still at #7 // Delay 7s for a total of 6.8s L = ; #3 // Delay 3s for a total of 9.8s //Test 2: Right signal on, Left off; 2 sec R = ; L = ; #7 // Delay 7s for a total of 26.8s R = ; #3 // Delay 3s for a total of 29.8s B R BULB_L //Test 3: Brake; 3 sec BULB_L2 B = ; R = ; #7 // Delay 7s for a total of 36.8s B = ; #3 // Delay 3s for a total of 39.8s BULB_L3 BULB_R BULB_R2 //Test 4: Brake and left flashers; 4 sec B = ; L = ; #7 // Delay 7s for a total of 46.8s BULB_R3 L = ; B = ; #3 // Leave some flat space between tests // It is easy to find test 5 if it starts at about 5 s // Test 5: Q L The actual test fixture uses f which is 8Hz. A divider in tbirdtop.sch divides this frequency by 8 to generate a Hz clock called. This test fixture pretends it generates a Hz here, which is what you may pretend when adding your tests RST Typical simulation results for L only followed by L and B, followed by B alone. Your simulation will be longer, and differ in detail, from these. Left signal turned on brake pushed right signal off Left turn Left turn and Brake left signal off # $stop; // When one reaches here, the simulation is over. end Department of Electronics February 7, 25 7

8 3.5.2 Implementation This program was intended to be implemented a Complex Programmable Logic Device (CPLD). The particular device will be a Xilinx XCR364XL-6 PC44, 44-pin logic-array. They run from a 3.3 V power supply and have a pin-to-pin delay of 2ns. Obviously your tail lights will not need to run that fast. It is basically a large collection of ANDs feeding a smaller collection of ORs, which feed flip-flops. How these arrays work will be described later in the Array Logic course notes. f and The circuit board containing the CPLD has a clock generator on it. This generator is set up for the MIDI lab and is so fast that the tail-light flashes become a blur. For this reason there is a frequency divider circuit built into the tbirdtop.sch file, which divides down the 8 Hz f signal to a Hz for flash timing. Department of Electronics February 7, 25 8