SignalTap: An In-System Logic Analyzer

Transcription

1 SignalTap: An In-System Logic Analyzer I. Introduction In this chapter we will learn 1 how to use SignalTap II (SignalTap) (Altera Corporation 2010). This core is a logic analyzer provided by Altera that is compiled with your design. A block diagram view of the system is shown in Fig. 1. Fig. 1. Block diagram of a design that has SignalTap compiled as a separate design partition (Altera Corporation 2010). The goals of this chapter are: 1. To guide the reader in downloading and verifying a simple design on the DE1 board via SignalTap. 2. To explain the concepts of clock, trigger and buffer in SignalTap. 3. To help the reader understand different areas of the SignalTap main window. 1 As usual, this tutorial refers to version 10.0 of Quartus and the associated tools.

2 II. The System The design to be analyzed configures a Cyclone II Phase Locked Loop (PLL) via the MegaIP Wizard to step up the 50 MHz DE1 board clock to 100 MHz 2. We use a counter to step down the 50 MHz clock to 1 Hz and output the slow clock to a green LED on the DE1. We use the same counter, but the input clock is 100 MHz. We output this clock to a red LED on the board. Visually, the red LED will appear to flash twice as fast as the green LED. A top-level FSM waits for the user to press KEY(0) on the DE1 board before running the design. We confirm the 100 MHz clock frequency using SignalTap. A top-level RTL output of the project is shown in Fig. 2. Note that to avoid confusion, Fig. 2 does not include the SignalTap core. Fig. 2. The top level RTL view of the signaltapdemo project To continue, please open the signaltapdemo Quartus project. III. Starting SignalTap Note that before we can use SignalTap we need to enable the TalkBack feature in Quartus. Refer to Appendix A at the end of this chapter to enable the TalkBack feature. There are many ways to start SignalTap. The easiest way is to add a SignalTap (.stp) file to our project. We will then configure SignalTap, compile SignalTap with our design and download the resulting.sof file to the DE1 board. Note that every time we change settings in SignalTap, we need to recompile the entire project since we are using the free web edition of Quartus. The subscription edition of Quartus has the incremental compilation feature that enables us to recompile only modified elements of our design. First, to start SignalTap, add the.stp file to our project as follows: 1. Once you open the signaltapdemo project, left-click File New. 2 We will use faster clocks in later chapters to output higher VGA resolutions.

3 2. The window in Fig. 3 should pop up. Left-click on as shown in Fig. 3 and left-click. Fig. 3. Adding the.stp file to your project The SignalTap window in Fig. 4 appears. The different sub-windows of SignalTap have been labeled in Fig. 4. We will use these sub-windows to understand some of the basic concepts behind SignalTap.

4 IV. Basic Concepts behind SignalTap Fig. 4. SignalTap main window There are three main concepts behind SignalTap: the clock signal, the trigger and the buffer. Please refer to Fig. 4 throughout the discussion below. 1. The Clock Signal provides the source of the sampling clock for your design. In this case, we will use a 300 MHz sampling clock. According to the Nyquist-Shannon sampling theorem (Varaiya and Lee 2002), to avoid aliasing, the sampling clock needs to be at least twice as fast as the highest frequency in the system. In our project the fastest clock has a frequency of 100 MHz. Hence we need a sampling clock with a frequency of at least 200 MHz. 2. The Trigger source starts the sampling of the specified signals (using the sampling rate of the Clock Signal in 1.). In the case of our project we will trigger on the start button. That is, SignalTap will wait till the user presses KEY0 on the board to start sampling at the rate specified by the clock signal. 3. The Buffer is where the data is stored. We will use a buffer size of 4K. The size of the buffer and the number of signals that we monitor determine the amount of time for which data can be stored.

5 Based on the discussion above we will configure SignalTap to use the 300 MHz clock as the sampling clock, KEY(0) as the trigger and a buffer size of 4K. To configure SignalTap to use the 300 MHz clock: 1. Left-click on the next to The Clock Signal label in Fig. 4. The Node-finder window in Fig. 5 appears. Fig. 5. The node finder window The node finder window can be used to add clock sources, signals and triggers. We will add the 300 MHz clock signal first. First, make sure the default setup of the node finder window matches the settings in Fig. 6. Fig. 6. Default setup of the node finder window, compare to Fig The default setup indicates that we are going to list all names from our design entry. Left-click in the node finder window. Fig. 5 changes to Fig. 7.

6 Fig. 7. The node finder window listing all signals in our design entry Scroll down the as shown in Fig. 8. list till you can select clockpll:pllrealization c1 signal Notice that Quartus synthesized away the node name specified in our project. The reason is that the 300 MHz clock is not driving any input.

7 Fig. 8. Selecting the 300 MHz clock signal. The format of the node is <component name>:<instance name> port 3. Left-click to move the node to. Next, left-click. This should bring up the SignalTap main window. The relevant part of this window is shown in Fig. 9. Fig. 9. The Clock source is selected to be the second output of the PLL, the 300 MHz clock Now we will configure the sample depth or Buffer size. Simply select 4K from the drop down box in Fig. 9.

8 Finally we will add the signals that we want to sample and select one of them as the trigger source. A very important note about SignalTap is that it is not possible to display or trigger on the clock source. To add signals to be monitored: 4. Right-Click in the Trigger Sources and Signals to be Monitored sub-window (refer to Fig. 4). This should bring up the menu shown in Fig. 10. Fig. 10. We will use the Node Finder to add signals and trigger sources

9 5. Left-click. The Node finder window appears again. Select nodes such that the Node finder window matches Fig. 11 shown below. Fig. 11. Selecting the signals to monitor and our trigger source We have elected to monitor three signals: KEY(0) 3, the 50 MHz clock and the 100 MHz clock. The node for the 100 MHz clock is. 6. Left-click the Trigger Sources. This should bring back the SignalTap main window but now and Signals to be monitored is filled. Refer to Fig. 12. Fig. 12. The setup window configured with our nodes to be monitored 3 We use the VHDL notation for KEY: KEY(0) instead of SignalTap s square bracket notation: KEY[0].

10 7. We will trigger on a falling edge (active low) of KEY(0). Right-Click the under Trigger Conditions for KEY(0) and select as shown in Fig. 13. Fig. 13. Configuring KEY(0) as the trigger 8. Uncheck for the other signals. The final result should be Fig. 14. Fig. 14. Trigger and signals are selected We are almost ready to simulate. First, notice that the amount of memory (M4K) blocks required by our.stp file is reported under the SignalTap Memory Usage section in Fig. 4. Fig. 15 below shows only this section from Fig. 4 but with the relevant information filled in. Fig. 15. Trigger and signals are selected Finally we need to save, compile and download our design. This is done in the next section. V. Running SignalTap

11 1. Save your.stp file by selecting File Save. Use the default name, a dialog box asks if you want to enable SignalTap for the current project. Select yes and open the minimized Quartus Window. You should see the stp1.stp under Project Navigator and the design ready to be compiled as shown in Fig. 16. Fig. 16. Quartus project with SignalTap module added Double-click on and wait for the synthesis to finish.

12 2. Once synthesis is complete, maximize the SignalTap window again and browse for the.sof file by left-clicking next to the.sof file information box (refer to Fig. 4). Choose the signaltapdemo.sof file, the result is shown in Fig. 17. Fig. 17. signaltapdemo.sof selected for download 3. Now power on the DE1 board by connecting the USB cable to your laptop. Left-click (in Fig. 17) to bring up the Hardware Setup window shown in Fig. 18. Use the drop-down box as shown in Fig. 18 to select the USB-Blaster. Left-click to go back to the SignalTap main window. Fig. 18. Selecting the USB blaster 4. Use the drop down box (refer to Fig. 19) to select USB-Blaster in the SignalTap main window. Fig. 20 shows the result.

13 Fig. 19. Enabling USB blaster in SignalTap Fig. 20. USB blaster enabled in SignalTap 5. SignalTap should now be ready to acquire. Left-click the tab under the Trigger Sources and Signals to be monitored and Left-click on the SignalTap instance under SignalTap Memory Usage (refer to Fig. 4). Fig. 21 shows the result. 6. Left-click on Run-Analysis button. SignalTap will interface to the DE1 and wait for you to press KEY(0). Once you press KEY(0), you should obtain Fig In order to zoom in and confirm that we have a doubled clock, move your mouse cursor over the any of the signals in the Data window. The cursor will change to a zoom icon. Repeatedly left-click till you can visually confirm that you have a doubled clock, refer to Fig. 23. Now, it would be useful if the time units were in seconds instead of sample numbers. To change the units, right-click on the scale. Enter 3.33 ns since we have a 300 MHz sampling clock and leftclick and select. Figure 24 shows the result.

14 Fig. 21. SignalTap ready to acquire Fig. 22. Data acquired in SignalTap, after pressing KEY(0)

15 Fig. 23. Zoomed in signals. Notice that the clocks are not synchronized Fig. 24. Axis scale adjusted to display time units. Notice that the PLL clock out has twice the frequency as the 50 MHz clock VI. Conclusions In this chapter, we introduced you to SignalTap. We downloaded a simple clock doubler design on the DE1 board and confirmed the functionality of our design. SignalTap has advanced features like segmented buffering, advanced trigger conditions like state-based triggering etc. The SignalTap user s manual from Altera (Altera Corporation 2010) is a good starting point for advanced functionality in SignalTap. VII. References Altera Corporation. "Quartus II 10.0 handbook - Design Debugging Using the SignalTap II Logic Analyzer." July (accessed July 2010). Varaiya, Pravin P, and Edward A Lee. Structure and Interpretation of Signals and Systems. Addison- Wesley, VIII. Revision History Date August 2010 Author/Comments Dr. Muthuswamy/initial documentation

16 Appendix A Enabling the TalkBack Feature Before we begin, we need to enable the TalkBack feature of Quartus II web edition so we can use SignalTap. Follow the steps below to enable the TalkBack feature. Step 1: Start Quartus and select Tools Options Internet Connectivity. You should see the window in Fig. A1. Fig. A1. Enabling TalkBack Select and enable the feature. Save your settings and restart Quartus. You should now be able to use SignalTap.