ARTICLE IN PRESS. Nuclear Instruments and Methods in Physics Research A

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Nuclear Instruments and Methods in Physics Research A 598 (2009) 591 597 Contents lists available at ScienceDirect Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.

Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa 229-8510, Japan b Department of Physics, The University of Tokyo, Bunkyo, Tokyo 113-0033, Japan c RIGAKU Co.

1 Nuclear Instruments and Methods in Physics Research A 598 (2009) Contents lists available at ScienceDirect Nuclear Instruments and Methods in Physics Research A journal homepage: Development of a low-noise, two-dimensional amplifier array Tetsuichi Kishishita a,b,, Hirokazu Ikeda a, Takuto Sakumura c, Ken-ichi Tamura a,b, Tadayuki Takahashi a,b a Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa , Japan b Department of Physics, The University of Tokyo, Bunkyo, Tokyo , Japan c RIGAKU Co., Ltd., Akishima, Tokyo , Japan article info Article history: Received 21 April 2008 Received in revised form 12 August 2008 Accepted 24 September 2008 Available online 17 October 2008 Keywords: ASIC VLSI Analog front-end Low noise CdTe X-ray Gamma-ray abstract This paper describes the recent development of a low-noise, two-dimensional analog front-end ASIC for hybrid pixel imaging detectors. Based on the Open-IP LSI project, the ASIC is designed to meet a lownoise requirement of better than 100e (rms) with self-triggering capability. The ASIC is intended for the readout of pixel sensors utilizing silicon (Si) and cadmium telluride (CdTe) as detector materials for spectroscopic imaging observations in the X-ray and gamma-ray regions. The readout chip consists of a 4 4 matrix of identical 270 mm 270 mm pixel cells and was implemented with TSMC 0:35-mm CMOS technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, shaper, comparator, and peak hold circuit. Preliminary testing of the ASIC achieved an 88e (rms) equivalent noise charge and a 25e =pf noise slope with power consumption of 150 mw per pixel. & 2008 Elsevier B.V. All rights reserved. 1. Introduction The development of hybrid pixel detectors for particle detection with high spatial resolution in high energy physics experiments has spun off a number of developments with applications in imaging, most notably biomedical imaging, and also imaging in X-ray astronomy. Particularly, in high-energy astrophysics, the hard X-ray imagers that can reconstruct hard X-ray images originating from astronomical point sources with high spatial and high energy resolution at a moderate data rate are the focus of development in studying the non-thermal universe. So far, cadmium telluride (CdTe) pixel detectors, with high stopping power and good energy resolution, are one of the principal detector materials for the next-generation hard X-ray imager. The hard X-ray imager consists of a super-mirror hard X-ray telescope and CdTe pixel detectors on a focal plane [1]. A two-dimensional readout ASIC assembled with CdTe pixel detectors using the stud-bump technique provides a signal processing circuit for each pixel of the detector. To take advantage of the mirror, the readout ASIC must meet several requirements as follows: (a) low-noise performance better than 100 electrons Corresponding author at: Institute of Space and Astronautical Science, Japan Aerospace Exploration Agency, Sagamihara, Kanagawa , Japan. address: kisisita@astro.isas.jaxa.jp (T. Kishishita). (rms) with self-trigger capability and a timing resolution of a few tens of microseconds, (b) pixel size of about 250 mm 250 mm to assemble with CdTe pixel detectors, and (c) low power consumption of about 200 mw per pixel to comply with a limited power budget. Thus, a two-dimensional readout ASIC with excellent spectroscopic performance is a key element for hard X-ray imagers. In the past few years, we developed several prototype ASICs to establish circuit designs and readout architectures in the Open-IP LSI project led by JAXA (see Ref. [2]). As the first step of prototyping, we developed a two-dimensional analog ASIC with TSMC 0:25-mm CMOS technology [3,4]. Each pixel cell contains a charge-sensitive amplifier (CSA), three-stage shaping amplifiers and comparator circuits, with special care taken in the layout to set the circuits in pixel cells of 200 mm 200 mm. In the preliminary tests of the ASIC, we demonstrated a twodimensional pixel readout scheme and obtained a mean noise level of 279e (rms) with power consumption of 110 mw per pixel [5]. We subsequently fabricated an eight-channel low-noise analog ASIC with TSMC 0:35-mm CMOS technology [6]. The main objective for the ASIC is to construct a set of verified designs of circuit blocks to be used for two-dimensional ASICs and establish a low-noise architecture. In the performance measurements, we obtained an equivalent noise level of 130e (rms) and an energy resolution of 2.4 kev for 60 kev gamma rays with a CdTe diode detector [7] /$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi: /j.nima

2 592 T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) In order to improve the analog performances of the twodimensional ASIC [5], we developed a new 4 4 two-dimensional analog ASIC by utilizing the low-noise circuit architecture of the one-dimensional ASIC [6]. Our objective mainly places emphasis on achieving good energy resolution from detectors in the energy range of kev, with a typical counting rate less than 100 cnt/s per pixel. The ASIC is designed to meet a low-noise requirement of better than 100e (rms) with a detector capacitance of 1 pf, self-triggering capability, and a power consumption of 150 mw per pixel. This paper reports the design and preliminary test results of our low-noise, two-dimensional readout ASIC. Section 2 describes the basic structure of the ASIC and details the circuit schematics. Although the circuit architecture in the shaper circuit is the same as in the previously developed low-noise ASIC [6], we employed a transfer gate-type FET as a feedback component in the CSA circuit, which is not employed in the previous ASIC, and also included a pole-zero cancellation (PZC) circuit. Section 3 presents the setup of the performance measurements. Section 4 gives the preliminary experimental results of the ASIC. Finally, Section 5 gives a summary and conclusion. 2. Circuit description 2.1. Overview of the ASIC The readout ASIC is implemented with TSMC 0:35-mm CMOS technology and has a chip size of 2:95 mm 2:95 mm. In the ASIC, 16-channel pixel cells of 270 mm 270 mm are arranged in a 4 4 matrix. Fig. 1 shows a photograph of the ASIC. Each pixel cell has a bonding pad area of 40 mm 40 mm for assembly with a pixel detector. The peripheral circuits contain bias circuits and shift registers used for pixel selection (Fig. 2). Among the 16 channels, the outer four pixel cells are connected to bonding pads and the other 12 channels are isolated. These four channels can be used for evaluating spectral performance when connected to the Si and CdTe detectors. The power consumption in each pixel cell is Fig. 1. Photograph of the two-dimensional ASIC. The chip size is 2:95 2:95 mm 2 with 16-channel pixel cells of mm 2 arranged in a 4 4 matrix. Each pixel cell has a bonding pad for assembling with a pixel detector.

3 T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) Fig. 2. Block diagram of the ASIC. Bias voltages are supplied from the bottom module. Shift registers used for pixel selects are contained in CAPTOP and CAPLEFT modules. Analog inputs of the outer four pixel cells are connected to bonding pads. Table 1 Overview of the ASIC Fabrication process TSMC 0:35-mm CMOS Chip size 2:95 2:95 mm 2 Number of channels 16 Pixel size mm 2 Power consumption in each pixel 150 mw Total power consumption 9.9 mw Power rail 1:65 V 150 mw and the total power consumption including the peripheral circuits is 9.9 mw for the power rails of 1:65 V. LVDS digital signals are used to control the ASIC (Table 1) Analog processing Fig. 3 shows the analog circuit in a pixel cell. The signal processing chain consists of a CSA, PZC circuit, shaper, comparator, and peak hold circuit. To achieve lower power consumption and plug into a limited pixel space, we modified the overall architecture in comparison with the previous ASIC designs [6]. The key changes are as follows: (a) two shaper circuits with different shaping time constants are unified to a common circuit, (b) CMOS switches are inserted in front of the buffer circuits provided for monitoring analog output signals (with the switches activated only when the monitor pixel is selected), and (c) ESD protection circuits were not employed at CSA inputs. Fig. 4 shows the schematic of the preamplifier circuit employed for the CSA. The preamplifier circuit is based on a

4 594 T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) TPENB Cin Cf VDD Cdif BAND-PASS FILTER R1 C1 R2 D[0:3] DAC Buffer Comparator POS TRK HITX HITY V bias NOTA POS VGG Rf Rpz C2 OP1 TRK HOLD Buffer Analog Out OP2 Ch POS Fig. 3. Signal processing chain for each pixel cell. Here, typical values of the capacitors and resistors are C in ¼ 0:1 pf, C f ¼ 0:02=0:04 pf, C dif ¼ 1:2 pf, C 1 ¼ C 2 ¼ 0:2 pf, R 1 ¼ 6M O, R 2 ¼ 1:5M O. R f and R pz are in the range of several M O adjusted with gate voltage VGG. AIN VL VH M3 M2 M1 VDD AOUT constant is set at 5 ms. The output of the shaper circuit is split into the peak hold circuit and comparator circuit. The peak hold circuit consists of a peak-detect circuit and a hold circuit. In the peakdetect circuit, we employed different operational amplifiers to construct CMOS diode configurations for each polarity of the input signals. The peak-detect circuit is enabled by releasing the TRK signal and the peak-detect circuit output can be quickly held in a MOS capacitor by a properly timed external HOLD signal in concert with the comparator hit signals. The output of the peak hold circuit is fed into a multiplexer to be sequentially processed by an external A-to-D converter. The hit signals are generated in the comparator block by referring to an analog ground level. Baseline adjustment is achieved with a current DAC controlled by signals provided by control registers. The output of the adjustment DAC is summed with the shaper circuit output and fed to the reference terminal of the discriminator Transfer function The transfer function of the CSA is given as Fig. 4. Schematic of the preamplifier circuit. conventional cascade configuration with an input PMOS transistor. We chose a PMOS transistor as an input transistor (i.e. M1) in terms of 1=f noise. In order to optimize low-noise performance, we allocated a large value of 8 mm to the gate width, and 18 to the M value (denoting the number of transistors arranged in parallel). The gate length is 1:8 mm. In order to maintain the low-noise characteristics, we also inserted MOS capacitors M2 and M3 to stabilize the voltage between VH and VDD, and between VL and. As shown in Fig. 3, we employed a transfer gate-type FET for the feedback component as is often used in several low-noise ASICs (see Refs. [8 13]). However, the nonlinear response of the feedback component generates waveform distortion that results in undershoot or overshoot at shaper circuit output. To eliminate undershoot, we inserted a capacitor C dif and FET R pz to configure a PZC circuit (e.g. Refs. [14 16]). The architecture of the shaper circuit fundamentally adheres to that of the previously designed ASIC [6], and the shaping time R f T 1 ðsþ ¼ (1) 1 þ sc f R f where s denotes the complex angular frequency, R f the feedback resistance, and C f the feedback capacitance. The PZC network shown in Fig. 3 modifies the transfer function as R f T 1 ðsþ 0 ¼ Q in 1 þ sc difr pz (2) 1 þ sc f R f R pz where C dif and R pz denote capacitance and resistance in the PZC circuit, respectively. By setting the parameters as C dif R pz ¼ C f R f (3) the pole associated with the signal decay of the CSA is compensated by zero of the PZC, and undershoot can be eliminated [17]. The above equation can be rewritten as T 1 ðsþ 0 C ¼ Q dif in. (4) C f For impedance matching, we set the M values of R f and R pz, which indicate the number of FET gates arranged in parallel, at 1:30.

5 T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) The transfer function of the shaper circuit shown in Fig. 3 can be written as R 1 T 2 ðsþ ¼ s 2 C 1 C 2 R 1 R 2 þ sr 1 C 1 þ 1. (5) By setting the parameters as C 1 R 1 ¼ 4C 2 R 2, the above equation can be rewritten as R 1 ð2sc 2 R 2 þ 1Þ. (6) 2 This circuit has a degenerated pole at s ¼ 1=2C 2 R 2 and functions as low-pass filter. Eventually the entire transfer function of the signal processing chain is given by T 1 ðsþ 0 T 2 ðsþ, which yields Q in C dif C f R 1 ð2sc 2 R 2 þ 1Þ. (7) Control scheme Each pixel cell contains a 10-bit configuration register. Four bits are used for coarse baseline equalization (35 mv/bit), four bits for fine adjustments (5 mv/bit), one bit for masking noisy channel, and one bit to enable test pulse input. Entire bits are stored in D-type flip flops that can be accessed by using peripheral shift registers, which also consist of D-type flip flops and are aligned in X and Y coordinates for pixel selection. A simple protocol is used to operate configuration registers along with three control lines (for data input, write clock signals and write-enable signals). The polarity of input signals and the gain of preamplifiers (C f ¼ 0.02 or 0.04 pf) can be selected by a common setting over all the channels. The sparse readout scheme is borrowed from the previously designed two-dimensional ASIC [5]. The readout sequence proceeds in two steps: reading the hit pattern and reading out analog outputs from selected pixels. The outputs of the comparator circuit are summed over the entire chip to be fed into an external trigger circuit. The trigger signals are also summed over row and column, with x-hit and y-hit signals being projected into the peripheral circuits to be recorded in a X Y coordinate register for the corresponding event. Then the hit pattern is read out, the hit pixel selected, and the A-to-D conversion cycle activated according to the hit pattern. is comparable with the shaping time constant of the shaper circuit. The upper and lower panels in Fig. 6 show the outputs of the shaper and peak hold circuit, respectively. The dot-dash lines indicate the SPICE simulation results. The shaper and peak hold circuits are operated properly for either positive or negative input signals. The shaping times are a bit longer than the simulation and a small overshoot is observed. The difference of the shaping times comes from a variation in resistance values of R 1 and R 2 in Fig. 3. Since the high-resistance circuits for the shaper include a 20 ko polysilicon resistor [6], the effective resistance value suffers from a semiconductor process variation and results in a longer shaping time. As for the small undershoot, the waveform of the SPICE simulation does not show any significant overshoot for a relative fluctuation of C f, C dif in Eq. (2), and VGG. One possible interpretation comes from interferences between the monitor line of the shaper output and the input pad of the CSA. However, our application does not require high counting rate and these influences can be negligible. Fig. 5. Measured analog waveform traces of the outputs of the CSA and shaper circuit. The injected charges were 2 fc. 3. Setup for performance measurements The ASIC placed in a QFP ceramic package was held in a burnin socket mounted on a test board. The interface with a computer was established using a National Instruments PCI-7833R board containing a reconfigurable FPGA and A-to-D converters. LabVIEW software tools were used to control the readout sequence. 4. Experimental results 4.1. Waveforms of analog outputs We have confirmed basic operation of the ASIC by injecting test pulses and checking analog signals from the monitor outputs for 10 chips (i.e. total of 160 channels). Fig. 5 shows the outputs of the CSA and shaper circuit with three different decay time constants (C f R f ). Test pulses equivalent to input charges of 2 fc are injected with C f ¼ 0:02 pf in each measurement. The PZC is successfully operated to suppress undershoot even if the decay time constant Fig. 6. Measured analog waveform traces of the outputs of the shaper and peak hold circuits. The dot-dash lines indicate the SPICE simulation results. The injected charges were 2 fc.

6 596 T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) Fig. 9. Input capacitance versus equivalent noise level. The dot line shows results from a circuit simulation. Fig. 7. Linearity curve of a typical channel. The measured data points (red: C f ¼ 0:02 pf, blue: C f ¼ 0:04 pf) are shown. The lower plots indicate the residuals between the data points and linear functions. Fig. 10. Baseline distributions before and after adjustment. of 1% in a range of 6 to +5 fc with C f of 12 to +9 fc with C f ¼ 0.04 pf. ¼ 0.02 pf, while in a range 4.3. Noise performance Fig. 8. Equivalent noise distribution Linearity and dynamic range Fig. 7 shows the linearity curves of a typical channel. The configuration settings are the same for both negative and positive input signals. The lower panel shows the residuals between the measured data points and linear functions. Different linear functions are used for calculating the residuals between positive and negative polarities. Except for a small range of positive input charges, good linearity is maintained with an integral nonlinearity Fig. 8 shows the equivalent noise distribution for input capacitance of 0 pf. Electronic noise is normalized by the response to a test pulse. The injected charge was 2 fc with the feedback capacitor of 0.02 pf. We used 12 isolated channels per chip over a total of five chips for the measurement. The mean noise level is 88 7:6e (rms) with power consumption of 150 mw per pixel, while the theoretically expected noise level is 48e (rms). The noise performance highly improved from the previously designed ASIC [6], however, there is still some room for noise improvement in the experimental setup. The current ASIC assembled in a ceramic package is tested with a burn-in socket and exposed in an exogenous noise environment. The ESD protection circuit at the input node of the CSA is removed in this design to eliminate possible origin of noise source. Since the capacitance of the CdTe

7 T. Kishishita et al. / Nuclear Instruments and Methods in Physics Research A 598 (2009) pixel detector is about 1 pf per pixel, the total noise level will satisfy our noise requirement of less than 100e. We measured the noise slope using the outer four channels connected to a DIP socket mounted on the test board. Fig. 9 shows the input capacitance versus noise level (ENC). Although the noise slopes are nearly consistent with the simulation results, the curves have excess noise of 380e. That excess noise does not originate from parasitic noise due to an assembly issue. It turns out that the wiring trace for the pixel to the bonding pad capacitively introduces positive feedback to the CSA input and then, it results in circuit oscillation Baseline distribution Fig. 10 shows the distribution of the output baselines. We adjusted the baselines to analog ground level to confirm the baseline adjustment range. Except for a few channels, the baseline distribution after applying the baseline adjustment is 1.66 mv, which is comparable with noise fluctuation. 5. Summary We developed a low-noise, 16-channel two-dimensional amplifier array with TSMC 0:35-mm CMOS technology in the Open-IP LSI project for future use in hard X-ray astronomy. The entire chip consists of 4 4 matrix of identical 270 mm 270 mm pixel cells, each of which includes a charge-sensitive amplifier, shaper, comparator, and peak hold circuit. In the preliminary test of the ASIC, the mean equivalent noise level reached 88e þ 25e =pf (rms) with power consumption of 150 mw per pixel. Except the pixel size, the analog performances satisfy our noise requirement of less than 100e with a detector capacitance of 1 pf, and power limits of 200 mw per pixel. In the following step, we will bump the ASIC with a CdTe pixel detector and evaluate its spectroscopic properties. Since the circuit designs are developed in each function block, we can easily apply these circuit architectures to multichannel ASICs for X-ray and gamma-ray imaging applications. This easy-to-use expandability supported by the good performance levels of the ASIC will lead to more applications in addition to astrophysical ones, including medical and industrial applications. Acknowledgments The authors would like to express their sincere gratitude for the financial support of JAXA with regards to the Steering Committee of Space Engineering. T. Kishishita is supported by research fellowships of the Japan Society for the Promotion of Science for Young Scientists. References [1] T. Takahashi, K. Makishima, Y. Fukazawa, M. Kokubun, K. Nakazawa, M. Nomachi, H. Tajima, M. Tashiro, Y. Terada, New Astron. 48 (2004) 269. [2] H. Ikeda, Nucl. Instr. and Meth. A 569 (2006) 98. [3] K. Tamura, T. Hiruta, H. Ikeda, H. Inoue, T. Kiyuna, Y. Kobayashi, K. Nakazawa, T. Takashima, T. Takahashi, IEEE Trans. Nucl. Sci. NS-52 (2004) [4] T. Hiruta, K. Tamura, H. Ikeda, K. Nakazawa, T. Takashima, T. Takahashi, Nucl. Instr. and Meth. A 565 (2006) 258. [5] T. Kishishita, H. Ikeda, K. Tamura, T. Hiruta, K. Nakazawa, T. Takashima, T. Takahashi, Nucl. Instr. and Meth. A 578 (2007) 218. [6] T. Kishishita, H. Ikeda, T. Kiyuna, K. Tamura, K. Nakazawa, T. Takahashi, Nucl. Instr. and Meth. A 580 (2007) [7] T. Kishishita, H. Ikeda, T. Kiyuna, H. Yasuda, K. Tamura, T. Takahashi, Jpn. J. Appl. Phys. 47 (5) (2008) [8] E. Beuville, K. Borer, E. Chesi, E.H.M. Heijne, P. Jarron, B. Lisowski, S. Singh, Nucl. Instr. and Meth. A 288 (1990) 157. [9] O. Toker, S. Masciocchi, E. Nygård, A. Rudge, P. Weilhammer, Nucl. Instr. and Meth. A 340 (1994) 572. [10] E. Nygård, P. Aspell, P. Jarron, P. Weilhammer, K. Yoshioka, Nucl. Instr. and Meth. A 301 (1991) 506. [11] P. Aspell, R. Boulter, A. Czermak, P. Jalocha, P. Jarron, A. Kjensmo, W. Lange, E. Nyġard, A. Rudge, O. Toker, M. Turala, H. Von Der Lippe, U. Walz, P. Weilhammer, K. Yoshioka, Nucl. Instr. and Meth. A 315 (1992) 425. [12] G.D. Geronimo, P. O Connor, J. Grosholz, IEEE Trans. Nucl. Sci. NS-47 (2000) [13] W.R. Cook, J.A. Burnham, F.A. Harrison, Proc. SPIE 3445 (1998) 347. [14] G. De Geronimo, P. O Connor, IEEE Trans. Nucl. Sci. NS-47 (2000) [15] P. Grybos, R. Szczygiel, IEEE Trans. Nucl. Sci. NS-55 (2008) 583. [16] C. Fiorini, M. Porro, Nucl. Instr. and Meth. A 568 (2006) 101. [17] C.H. Nowlin, J.L. Blankenship, Rev. Sci. Instr. 36 (1965) 1830.

Nuclear Instruments and Methods in Physics Research A

Nuclear Instruments and Methods in Physics Research A 623 (2) 24 29 Contents lists available at ScienceDirect Nuclear Instruments and Methods in Physics Research A journal homepage: www.elsevier.com/locate/nima