Towards Trusted Devices in FPGA by Modeling Radiation Induced Errors

Transcription

1 Digital Design and Dependability Research Group FIT, CTU in Prague Towards Trusted Devices in FPGA by Modeling Radiation Induced Errors Tomáš Vaňát, Jan Pospíšil, Jan Schmidt {vanattom, In close collaboration with Jozef Ferencei Department of Nuclear Spectroscopy, NPI of ASCR

2 Problem definition FPGA Programmable logic device Lot of memory cells Logic functions and interconnection - Configuration D Flip-flops for sequential logic - Data 2

3 Hierarchy of FPGA interconnection Switch blocks global connections Logic Block LB Logic Block LUT LB D Interconnecting network Configuration of function LUT D Connection Blocks LB LB LB LB connected to net 3

4 Problem definition FPGA Programmable logic device Lot of memory cells CMOS Logic functions and interconnection - Configuration D Flip-flops for sequential logic - Data Small structures Controlled by voltage Ionizing radiation Transferring energy through matter Depositing charge inducing current voltage change Problem: Single-event effects (SEE), mainly upsets (SEU) 4

5 SEU in FPGA Change of Function (LUT) Structure (interconnection) Data (D-FF) Locally unpredictable can hit any location Can influence dependability of the circuit/application But fightable by Redundancy Self check Self repair (reconfiguration, ECC, ) Need of quantitative characteristic 5

6 Quantitative characteristic Deep simulation to the level of CMOS technology Unusable for real system size Accelerated life testing (ALT) Unusable for real system too specific, too expensive Combination? Partial simulation and Partial ALT 6

7 Proposed Method 1. Create quantitatively described platform model a) Based on higher-level simulation b) Calibrated by Accelerated Life Tests 2. Use the model to predict any future design s behavior on this platform 7

8 Proposed Method a) Higher-level simulation Based on VTR framework Custom FPGA architecture Timing-driven place-n-route on given platform Defect injection Fault simulation a) Calibration by Accelerated Life Tests Only on several special designs Only for model calibration 8

9 Test Circuit Example Tests all LUTs and flip-flops Propagates any error to output Ai Bi LUT4 D-FF Slice Ao Bo Forms a long pipeline LUT4 D-FF Is preloaded with data upon flip-flops reset Detects fault rate on the particular device under particular conditions Ci Di Co LUT4 D-FF Do LUT4 D-FF Slice One pipeline stage Pipeline 9

10 Test Circuit Example Code Symmetric After odd number of conversions, the output is same as input Any bit flip in any LUT appears as a change in the sequence Code 1 Code 2 Code 1 Code

11 Entire Test System Based on Spartan 3 Starter Kits Two parts One under radiation One away from radiation Connected trough 16 differential lines Radiated part is controlled from the shielded one Remote monitoring, reset, reload 11

12 Cyclotron Isochronous cyclotron U-120M At NPI Řež, ASCR Up to 37 MeV protons Intensity from 10 4 p/cm 2 /s 12

13 Irradiation Setup 13

14 Irradiation Setup 14

15 Spartan3 Irradiation Xilinx SRAM FPGA Starter Kit used XC3S200 device 90 nm CMOS technology Only SEU in configuration memory (CMem) counted 15

16 Error rate [1/s] Error rate [1/s] Spartan3 Irradiation 1,6 1,4 1,2 1 0,8 0,6 0,4 Configuration error rate vs. proton flux 34,05 MeV 28,242 MeV 18,004 MeV 0,35 0,3 0,25 0,2 0,15 0,1 Configuration error rate vs. energy 0,4 Mp/cm^2/s 2,5 Mp/cm^2/s 8,7 Mp/cm^2/s 50 Mp/cm^2/s 105 Mp/cm^2/s 0,2 0, Proton flux [Mp/cmM^2/s] Energy [MeV] 16

17 SmartFusion2 Irradiation Microsemi FLASH SoC Only FPGA part tested Starter Kit used M2S050-FGG484 device 65 nm CMOS technology No SEU in configuration memory Some SEU in data flipflops (D-FFs) 17

18 Error rate [1/s] Error rate [1/s] SmartFusion2 Irradiation D-FF error rate vs. proton flux D-FF error rate vs. energy 0,3 34,745 MeV 0,07 1 Mp/cm^2/s 0,25 28,169 MeV 0,06 8 Mp/cm^2/s 0,2 17,613 MeV 0,05 50 Mp/cm^2/s 0,04 0,15 0,03 0,1 0,02 0,05 0, Proton flux [Mp/cmM^2/s] Energy [MeV] 18

19 Current work Preparing the same test for the IGLOO2 FLASH based FPGA Precise monitoring of the total dose Upgrade the communication module Synchronization of the FPGAs clock with cyclotron frequency Improving model of architecture, collect another data and calibrate the model 19

20 Conclusions We have proposed new method for predicting quantitative characteristics of SEU sensitivity of digital circuits implemented in FPGA. We have completed the first runs of ALT. We are currently working on the simulation model, improving the ALT system and preparing the tests for other devices. This method can be used for verifying dependability and security parameters of various designs implemented in FPGA 20

21 Conclusions FLASH based SmartFusion 2 (65 nm) has better resistance to Single Event Effects than Spartan 3 (90 nm) Configuration memory completely safe D flip-flops less vulnerable, although it is a smaller technology But the SmartFusion 2 has a very low total ionizing dose to permanently destroy to destroy the FLASH programming controller. ~4 krads for SF2 Spartan 3 already survived several hundreds of krads without permanent error noticed 21

22 Digital Design and Dependability Research Group FIT, CTU in Prague Thank you! Tomáš Vaňát, Jan Pospíšil, Jan Schmidt {vanattom, Special thanks to Jozef Ferencei Department of Nuclear Spectroscopy, NPI of ASCR