Digital Integrated Circuits EECS 312

Transcription

1 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) NTT Fujitsu M-780 IBM RY5 Jayhawk(dual) IBM RY7 Prescott T-Rex Mckinley Squadrons IBM GP Pentium Radio Receive for Mesh Maintenance 2-6 ma Typical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and Radio Transmission 9-15 ma Low Power Sleep ma Heartbeat 1-2 ma Time (seconds) Digital Integrated Circuits EECS Teacher: Robert Dick Office: 2417-E EECS dickrp@umich.edu Phone: Cellphone: GSI: Shengshou Lu Office: 2725 BBB luss@umich.edu HW engineers SW engineers Current (ma) IBM ES9000 Bipolar CMOS Power density (Watts/cm 2 ) Year of announcement IBM Z9

2 Review Latches and flip-flops What is charge sharing? Why are there two different expressions for the voltage to which V out settles? Is leakage a significant factor in charge sharing? How can it be prevented? What is volatile memory? What is non-volatile memory? What is static memory? What is dynamic memory? Derive and explain. 2 Robert Dick Digital Integrated Circuits

3 Lecture plan Latches and flip-flops 1. Latches and flip-flops Robert Dick Digital Integrated Circuits

4 Combinational vs. sequential logic No feedback between inputs and outputs combinational Outputs a function of the current inputs, only D flip flops q plain old combinational logic 4 Robert Dick Digital Integrated Circuits

5 Combinational vs. sequential logic No feedback between inputs and outputs combinational Outputs a function of the current inputs, only Feedback sequential clock D flip flops q plain old combinational logic 4 Robert Dick Digital Integrated Circuits

6 Combinational vs. sequential logic No feedback between inputs and outputs combinational Outputs a function of the current inputs, only clock D flip flops q plain old combinational logic 4 Robert Dick Digital Integrated Circuits

7 Sequential logic Latches and flip-flops Outputs depend on current state and (maybe) current inputs Next state depends on current state and input For implementable machines, there are a finite number of states Synchronous State changes upon clock event (transition) occurs Asynchronous State changes upon inputs change, subject to circuit delays 5 Robert Dick Digital Integrated Circuits

8 Flip-flop introduction Stores, and outputs, a value. Puts a special clock signal in charge of timing. Allows output to change in response to clock transition. More on this later. Timing and sequential circuits 6 Robert Dick Digital Integrated Circuits

9 Introduction to sequential elements Feedback and memory. Memory. Latches. 7 Robert Dick Digital Integrated Circuits

10 Feedback and memory Feedback or physical state are the root of memory. Can compose a simple loop from inverters. 8 Robert Dick Digital Integrated Circuits

11 Feedback and memory Feedback or physical state are the root of memory. Can compose a simple loop from inverters. However, there is no way to switch the value. 8 Robert Dick Digital Integrated Circuits

12 Bistability Latches and flip-flops 9 Robert Dick Digital Integrated Circuits

13 TG and NOT-based memory Can break feedback path to load new value However, potential for timing problems 10 Robert Dick Digital Integrated Circuits

14 TG and NOT-based memory Can break feedback path to load new value. How can this be made more area-efficient? Resize transistors, remove transistors, use state? 11 Robert Dick Digital Integrated Circuits

15 Section outline Latches and flip-flops 1. Latches and flip-flops 12 Robert Dick Digital Integrated Circuits

16 Reset/set latch Latches and flip-flops R S Q R Q S Q 13 Robert Dick Digital Integrated Circuits

17 Reset/set timing Latches and flip-flops 100 Reset Hold Set Reset Set Race R S Q Q Unstable state Unstable state 14 Robert Dick Digital Integrated Circuits

18 RS latch state diagram output=q Q input=r S Robert Dick Digital Integrated Circuits

19 Clocking terms Latches and flip-flops T su T h Input Clock Clock Rising edge, falling edge, high level, low level, period Setup time: Minimum time before clocking event by which input must be stable (T SU ) Hold time: Minimum time after clocking event for which input must remain stable (T H ) Window: From setup time to hold time 16 Robert Dick Digital Integrated Circuits

20 Gated RS latch Latches and flip-flops S Q R ENB Q 17 Robert Dick Digital Integrated Circuits

21 Gated RS latch Latches and flip-flops S R ENB Q Q 18 Robert Dick Digital Integrated Circuits

22 Memory element properties Type Inputs sampled Outputs valid Unclocked latch Always LFT Level-sensitive latch Clock high LFT (T SU to T H ) around falling clock edge Edge-triggered flip-flop Clock low-to-high transition Delay from rising edge (T SU to T H ) around rising clock edge 19 Robert Dick Digital Integrated Circuits

23 Section outline Latches and flip-flops 1. Latches and flip-flops 20 Robert Dick Digital Integrated Circuits

24 Active high transparent Active low transparent D Q D Q CLK CLK Positive (rising) edge Negative (falling) edge D Q D Q CLK CLK 21 Robert Dick Digital Integrated Circuits

25 Timing for edge and level-sensitive latches D Clk Q edge Q level 22 Robert Dick Digital Integrated Circuits

26 Latch timing specifications Minimum clock width, T W Usually period / 2 Low to high propegation delay, P LH High to low propegation delay, P HL Worst-case and typical 23 Robert Dick Digital Integrated Circuits

27 Latch timing specifications Example, negative (falling) edge-triggered flip-flop timing diagram D T su 20 ns T h 5 ns T su 20 ns T h 5 ns Clk Q T w 20 ns T plh C» Q 27 ns 15 ns T phl C» Q 25 ns 14 ns T plh D» Q 27 ns 15 ns T phl D» Q 16 ns 7 ns 24 Robert Dick Digital Integrated Circuits

28 FF timing specifications Minimum clock width, T W Usually period / 2 Low to high propagation delay, P LH High to low propagation delay, P HL 25 Robert Dick Digital Integrated Circuits

29 FF timing specifications Example, positive (rising) edge-triggered flip-flop timing diagram D T su 20 ns T h 5 ns T su 20 ns T h 5 ns Clk T w 25 ns Q T plh 25 ns 13 ns T phl 40 ns 25 ns 26 Robert Dick Digital Integrated Circuits

30 RS latch states Latches and flip-flops S R Q + Q + Notes 0 0 Q Q unstable 27 Robert Dick Digital Integrated Circuits

31 Section outline Latches and flip-flops 1. Latches and flip-flops 28 Robert Dick Digital Integrated Circuits

32 Falling edge-triggered Use two stages of latches When clock is high First stage samples input w.o. changing second stage Second stage holds value When clock goes low First stage holds value and sets or resets second stage Second stage transmits first stage Q + = D One of the most commonly used flip-flops 29 Robert Dick Digital Integrated Circuits

33 Edge triggered timing 100 Positive edge t riggered FF Negative edge t riggered FF 30 Robert Dick Digital Integrated Circuits

34 RS clocked latch Latches and flip-flops Storage element in narrow width clocked systems. Dangerous. Fundamental building block of many flip-flop types. 31 Robert Dick Digital Integrated Circuits

35 Latches and flip-flops Minimizes input wiring. Simple to use. Common choice for basic memory elements in sequential circuits. 32 Robert Dick Digital Integrated Circuits

36 Toggle (T) flip-flops State changes each clock tick Useful for building counters Can be implemented with other flip-flops D with XOR feedback 33 Robert Dick Digital Integrated Circuits

37 Asynchronous inputs How can a circuit with numerous distributed edge-triggered flip-flops be put into a known state? Could devise some sequence of input events to bring the machine into a known state. Complicated. Slow. Not necessarily possible, given trap states. Can also use sequential elements with additional asynchronous reset and/or set inputs. 34 Robert Dick Digital Integrated Circuits

38 Section outline Latches and flip-flops 1. Latches and flip-flops 35 Robert Dick Digital Integrated Circuits

39 Schmitt triggers Latches and flip-flops A B A 36 Robert Dick Digital Integrated Circuits

40 Schmitt triggers Latches and flip-flops A B A 36 Robert Dick Digital Integrated Circuits

41 Schmitt triggers Latches and flip-flops A B A 36 Robert Dick Digital Integrated Circuits

42 Schmitt triggers Latches and flip-flops A B A transition 36 Robert Dick Digital Integrated Circuits

43 Schmitt triggers Latches and flip-flops A B A transition B 36 Robert Dick Digital Integrated Circuits

44 Reason for gradual transition A logic stage is an RC network Whenever a transition occurs, capacitance is driven through resistance Consider the implementation of a CMOS inverter 37 Robert Dick Digital Integrated Circuits

45 Debouncing Latches and flip-flops Mechanical switches bounce! What happens if multiple pulses? Multiple state transitions Need to clean up signal 38 Robert Dick Digital Integrated Circuits

46 Debouncing Latches and flip-flops 5 4 Schmidt trig. RC V e e e e e e-03 T (s) 39 Robert Dick Digital Integrated Circuits

47 Latch and flip-flop equations RS Q + = S + R Q D Q + = D T Q + = T Q 40 Robert Dick Digital Integrated Circuits

48 Review Latches and flip-flops What are t su and t h? Define Level-sensitive. Edge-triggered. Latch. Flip-flop. What is the symbol for a falling edge triggered? Show a circuit design for a Schmitt-trigger inverter. Derive and explain. 41 Robert Dick Digital Integrated Circuits

49 Distributed loads and Elmore delay Derive the propagation delay of an aluminum wire that is 2cm long and 500 nm wide. Does using a lumped model introduce significant error? You may assume a sheet resistance of 0.075Ω/. Derive the propagation delay of a copper wire with the same shape. State, and verify, any assumptions. Derive and explain. 42 Robert Dick Digital Integrated Circuits

50 More on transistor sizing f(a,b,c) = ab +c Derive and explain. 43 Robert Dick Digital Integrated Circuits

51 Lecture plan 1. Latches and flip-flops Robert Dick Digital Integrated Circuits

52 Volatile memory SRAM cell and architecture overview. DRAM cell and architecture overview. 45 Robert Dick Digital Integrated Circuits

53 Non-volatile memory ROM. EPROM. EEPROM. Flash. 46 Robert Dick Digital Integrated Circuits

54 Floating gate technology UV erase. Electrical erase. Block erase. 47 Robert Dick Digital Integrated Circuits

55 Hot floating gate implementation Was once difficult to design uniform-thickness thin oxide layers. Tunneling-based programming was difficult. Avalanche injection (hot electron) based programming used. UV erasure. Pure tunneling later became practical (EEPROM). Flash uses hot electrons for programming and tunneling for erasing. 48 Robert Dick Digital Integrated Circuits

56 Array memory architecture 49 Robert Dick Digital Integrated Circuits

57 Block-based memory architecture 50 Robert Dick Digital Integrated Circuits

58 Memory timing 51 Robert Dick Digital Integrated Circuits

59 Review Latches and flip-flops What are the different ways a floating-gate memory cell can be erased? What are the different ways a floating-gate memory cell can be programmed? What are the two main DRAM bit cell organizations, and their advantages? Why is it difficult to economically put DRAM on the same die as a processor? Why are decoders and MUXs used in memory arrays? Derive and explain. 52 Robert Dick Digital Integrated Circuits

60 Lecture plan 1. Latches and flip-flops Robert Dick Digital Integrated Circuits

61 NOR ROM schematic 54 Robert Dick Digital Integrated Circuits

62 NOR ROM layout Program using active layer. 55 Robert Dick Digital Integrated Circuits

63 NOR ROM layout Program using contacts. 56 Robert Dick Digital Integrated Circuits

64 NAND ROM schematic 57 Robert Dick Digital Integrated Circuits

65 NAND ROM layout Program using metal layer. 58 Robert Dick Digital Integrated Circuits

66 NAND ROM layout Program using implants. 59 Robert Dick Digital Integrated Circuits

67 Lecture plan 1. Latches and flip-flops Robert Dick Digital Integrated Circuits

68 DRAM Latches and flip-flops 61 Robert Dick Digital Integrated Circuits

69 DRAM Latches and flip-flops 62 Robert Dick Digital Integrated Circuits

70 DRAM side view 63 Robert Dick Digital Integrated Circuits

71 Differential sense amplifier Useful for SRAM, can use two stages. 64 Robert Dick Digital Integrated Circuits

72 Latch sense amplifier Useful for DRAM. 65 Robert Dick Digital Integrated Circuits

73 Charge pump 66 Robert Dick Digital Integrated Circuits

74 Upcoming topics Theoretical foundations for sizing. 67 Robert Dick Digital Integrated Circuits

75 Lecture plan 1. Latches and flip-flops Robert Dick Digital Integrated Circuits

76 assignment I 31 October: Read Sections 6.3 and 7.1 in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, November: Read Sections 7.2.2, 7.2.3, 7.3.1, 7.3.2, and in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, November: Project Robert Dick Digital Integrated Circuits

77 assignment II 12 November: Read Sections , , and in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, November: Read Sections , , , and in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, November: Robert Dick Digital Integrated Circuits