Lecture 6: Simple and Complex Programmable Logic Devices. EE 3610 Digital Systems

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1 EE 3610: Digital Systems 1 Lecture 6: Simple and Complex Programmable Logic Devices

MEMORY 2 Volatile: need electrical power Nonvolatile: magnetic disk, retains its stored information after the removal of power Random access: memory locations can be read or written in a random order

2 MEMORY 2 Volatile: need electrical power Nonvolatile: magnetic disk, retains its stored information after the removal of power Random access: memory locations can be read or written in a random order Sequential access: access pattern, video memory streaming, first-in-first-out (buffer), last-infirst-out (stack), shift register, content-addressable memory EPROM: erasable programmable read-only memory EEPROM: electrically erasable programmable read-only memory FLASH: memory stick, USB disk Ref: M. Tehranipoor, ECE 3401 Lecture Notes, University of Connecticut

3 Programmable Logic Devices 3

4 Programmable Logic Devices 4

5 Read Only Memory (ROM) Example: 8-word x 4-bit ROM 5

6 Read Only Memory (ROM) 6 1. Each output pattern stored in the ROM is called a word 2. Each input combination serves as an address which can select one of the words which is stored in the memory. 3. We defined a ROM (2 n x m ROM), means an array of 2 n words and each word is m bits long.

7 Read Only Memory (ROM) 7

8 ROM Structure 8 Figure 9.19 Basic ROM Structure A ROM basically consists of a decoder and a memory array When a pattern is applied to the decoder input, exactly one of the 2 n decoder output is 1, this decoder output line selects one of the words in the memory array, and the bit pattern is transferred to the memory output lines Cengage Learning Engineering. All Rights Reserved.

11 The internal structure of the 8-word X 4 bit ROM Figure 9.20 An 8-Word X 4-Bit ROM The memory array forms the 4 output functions by ORing together selected miniterns from the truth table 11 ORing for F 0

12 Usefulness of ROM ROM can Figure model 9.20 any An n-input, 8-Word m-output X 4-Bit combinational ROM logic problem Example: BCD to 7-Segment Display Inputs: 4 bit BCD code Outputs: 7 control signals for the display 12

13 Usefulness of ROM Example: Figure Sort rods 9.20 of varying An 8-Word length (+/-10%) X 4-Bit on ROM conveyor belt Inputs: Three sensors A,B,C (light sources and photodiodes) Outputs: Two arm control signals First mechanical arm pushes rods within spec (+/-5%) to one side Second mechanical arm pushes rods too long to other side 13 A spec - 5% Too Long Within Spec Too Short spec + 5% B C Suketu 9-13Naik

house Inputs: Three switches in different positions Outputs:

14 14 Usefulness of ROM Example: Figure Wifi enabled 9.20 An lighting 8-Word control X in 4-Bit a large ROM room or a house Inputs: Three switches in different positions Outputs: Three different modes of light = three different control signals Suketu 9-14Naik

15 How to utilize ROM 15 Convert a 4-bit binary code to a hexadecimal, and output the 7-bits ASCII code. A4=A5, A6=A4 So we only need five ouputs 4 address, creating 16 words; each words shows a 7-bit pattern Suketu 9-15Naik

16 VHDL for ROM library IEEE; use IEEE.std_logic_1164.all; Figure 9.20 An 8-Word X 4-Bit ROM ENTITY rom8x4 IS PORT ( addr: in std_logic_vector(2 downto 0); q: out std_logic_vector(3 downto 0)); END rom8x4; ARCHITECTURE behav OF rom8x4 IS BEGIN PROCESS(addr) BEGIN CASE addr IS when "000" => q <= "0001"; when "001" => q <= "0000"; when "010" => q <= "0111"; when "011" => q <= "1101"; when "100" => q <= "1000"; when "101" => q <= "1100"; when "110" => q <= "0110"; when "111" => q <= "1011"; when others => NULL; END case; END process; END behav; 16

17 17 VHDL for ROM: declare constants library Figure ieee; 9.20 An 8-Word X 4-Bit ROM use ieee.std_logic_1164.all; entity rom16x8 is port(addr: in integer range 0 to 15;---can also have bits here instead data: out std_ulogic_vector(7 downto 0)); end entity; architecture sevenseg of rom16x8 is type rom_array is array (0 to 15) of std_ulogic_vector (7 downto 0); constant rom: rom_array := ( , , , , , , , , , , , , , , , ); begin data <= rom(addr);-may have to use to to_integer if bits end architecture;

18 18 Programmable Logic Array (PLA) Programmable logic array(pla) : functions as ROM For a ROM, we implement a truth table For a PLA, we implement a sum-of product expression Generic AND/OR logic Fused link or FET based 2010 Cengage Learning Engineering. All Rights Reserved.

21 21 Programmable Array Logic (PAL) Figure 9.28 PAL Segment PAL(Programmable Array Logic): Special case of PLA OR array is fixed, we only program the AND array fixed

22 Example: Programming a PAL to implement a full adder 22

23 Programmable Logic Device (PLD) 23 Programmable logic device (PLD) 1.Capable of being programmed to provide a variety of different logic functions. 2. Combinational PLD 3. Lower cost design Example: Generic Array Logic (GAL) Just like PALs but reprogrammable 2010 Cengage Learning Engineering. All Rights Reserved.

25 GAL Segment: Output Logic Macrocell (OLMC) 1) Register 2) Feedback 3) I/O: e.g. 12 input pins, 10 I/O pins 4) -S 1 S 0 =10 : FF is bypassed, output from OR, inverted and fed back to AND -S 1 S 0 =01 : output from FF, not inverted and fed back to AND -S 1 S 0 =00 : dashed lines 25 -When tri-state buffer is in high-z mode, OR and FF are disconnected and pin can be used for input To AND OR FF 10 01

26 GAL Segment: Output Logic Macrocell (OLMC) 1) Register 2) Feedback 3) I/O: e.g. 12 input pins, 10 I/O pins 4) -S 1 S 0 =10 : FF is bypassed, output from OR, inverted and fed back to AND -S 1 S 0 =01 : output from FF, not inverted and fed back to AND -S 1 S 0 =11 : dashed lines 26 -When tri-state buffer is in high-z mode, OR and FF are disconnected and pin can be used for input To AND OR FF 10 01

27 Complex Programmable Logic Devices (CPLD) Outputs from 1 PLD can be routed to inputs of another PLD using interconnect array Maximum clock speed is fixed (as long as registerd are used for each term) 27 I/O PLD PLD I/O Interconnect Array (IA) I/O PLD PLD I/O

28 Complex Programmable Logic Devices (CPLD) 28 Many PLA Figure or PAL 9.30 can Architecture be included in of a CPLD AsXilinx chip CPLD is actually a small digital system Xilinx CoolRunner XCR3064XL CPLD XCR3064XL contain 4 function blocks -Each block is a PLA: programmable AND-OR array -Each block has 16 macrocells (MC)

29 Complex Programmable Logic Devices (CPLD) Function block and Macrocell 29 MUX2: Select either combinational out put(g) or the flip-flop(q) Bi-directional Pin MUX1: Select OR-gate output(f) or it s complement (F )

30 Field Programmable Gate Arra (FPGA) FPGAs contain Figure an 9.32 array Layout of logic cells of called a Typical configurable FPGA logic blocks CLB 30 Programmable Interconnect Area

31 SIDE NOTES: INSIDE THE FPGA 31 CLB=Configurable Logic Block=4 Slices Slice=> two Look Up Table (LUT)s and two Flip Flops

32 A 4-input reprogrammable ROM FPGA: Simplied SLICE This SLICE shows outputs: X, Y, XQ, YQ 2. H1 can select the function generator Suketu 9-32Naik

33 Look Up Table (LUT) FPGAs contain one basic "logic-cell" duplicated thousands of times 33 Logic-cell: Small Look-Up Table (LUT), D flip-flop and 2-to-1 MUX (to bypass the flip flop if needed) Each logic-cell can be connected with other logic-cell through interconnect resources Complex logic can be implemented

34 Xilinx's CLB 34

35 16:1 MUX LUT Implementation: Shift Register 35 16:1 Addressable Shift Register LUT (64-bit Shift Register is max possible) Address (A[3:0]): (1) Dynamically changes the length of the shift register (2) Asynchronous path to D (output)

36 LUT Implementation: Shift Register Shift Register LUT (SRL) Structure 36

37 Library Primitives 37

38 VHDL Template for SRL -- Module: SHIFT_REGISTER_C_16 -- Description: VHDL instantiation template -- CASCADABLE 16-bit shift register with enable (SRLC16E) -- Device: Spartan-3 Generation Family Components Declarations: component SRLC16E -- pragma translate_off generic ( -- Shift Register initialization ("0" by default) for functional simulation: INIT : bit_vector := X"0000" ); -- pragma translate_on port ( D : in std_logic; CE : in std_logic; CLK : in std_logic; A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; Q : out std_logic; Q15 : out std_logic ); end component; -- Architecture Section: -- Ref: Xilinx App Note xapp465, "Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs" 38

39 VHDL Template for SRL -- Attributes for Shift Register initialization ( 0 by default): attribute INIT: string; -- attribute INIT of U_SRLC16E: label is 0000 ; ShiftRegister Instantiation U_SRLC16E: SRLC16E port map ( D =>, -- insert input signal CE =>, -- insert Clock Enable signal (optional) CLK =>, -- insert Clock signal A0 =>, -- insert Address 0 signal A1 =>, -- insert Address 1 signal A2 =>, -- insert Address 2 signal A3 =>, -- insert Address 3 signal Q =>, -- insert output signal Q15 => -- insert cascadable output signal ); 39 Ref: Xilinx App Note xapp465, "Using Look-Up Tables as Shift Registers (SRL16) in Spartan-3 Generation FPGAs"

40 LUT Implementation: RAM LUT is implemented with small RAM Four input bits act as an address bus: select output bit based on four input bits addressing one of 16 stored bits 40 Io I1 I2 I3 Out

41 LUT Implementation: Distributed RAM Types of available RAM in Xilinx FPGAs 41 Single-port RAM: Synchronous write port and asynchronous read port Synchronous reads are possible using the flip-flops Dual-port RAM: One synchronous write and two asynchronous read ports Synchronous reads are possible using the flip-flops Ref: Xilinx App Note xapp464, "Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs"

42 Library Primitives 42 Ref: Xilinx App Note xapp464, "Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs"

43 VHDL Template for Distributed RAM -- Module: RAM_16S -- Description: VHDL instantiation template -- Distributed RAM -- Single Port 16 x 1 -- Can also be used for RAM16X1S_1 -- Device: Spartan-3 Family Components Declarations: component RAM16X1S -- pragma translate_off generic ( -- RAM initialization ( 0 by default) for functional simulation: INIT : bit_vector := X"0000" ); -- pragma translate_on port ( D : in std_logic;we : in std_logic;wclk : in std_logic;a0 : in std_logic; A1 : in std_logic;a2 : in std_logic;a3 : in std_logic; O : out std_logic ); end component;

44 VHDL Template for Distributed RAM Architecture section: Attributes for RAM initialization ("0" by default): attribute INIT: string; -- attribute INIT of U_RAM16X1S: label is "0000"; Distributed RAM Instantiation U_RAM16X1S: RAM16X1S port map ( D =>, -- insert Data input signal WE =>, -- insert Write Enable signal WCLK =>, -- insert Write Clock signal A0 =>, -- insert Address 0 signal A1 =>, -- insert Address 1 signal A2 =>, -- insert Address 2 signal A3 =>, -- insert Address 3 signal O => -- insert Data output signal );

45 Programmable Interconnect 45 Interconnects are restricted and prop delays are more predictable in CPLD Propagation delays are not predictable in FPGA Mapping of Logiconto Logic blocks plays a big role in determining prop delays

46 Interconnect: Programming Technologies Static Random Access Memory (SRAM): mainly used in FGPA 46 SCAN Path SRAM Cells LUT Entry SRAM Cells Programmable Interconnect Scan Path is like a large shift register SRAM Cells Combination/Sequential Selection (part of slice)

47 Interconnect: Programming Technologies Static Random Access Memory (SRAM): mainly used in FGPA 47

48 Interconnect: Programming Technologies SRAM Cell Two cross-coupled inverters (Q1-Q2 and Q3-Q4) 48 Inverter Inverter

49 Interconnect: Programming Technologies Electrically erasable programmable ROMs(EEPROM): Using special charge-strorage mechanism to enable or disable the switching elements

used in CPLDs and some FPGAs Isolated or floating

50 Interconnect: Programming Technologies Electrically Erasable Programmable Read-Only Memory (EEPROM): used in CPLDs and some FPGAs Isolated or floating gate Stranded charge on the gate keeps the device 'on' 50

Interconnect: Programming Technologies EEPROM Usage for programming Unprogrammed state: the floating gate is uncharged Insulating oxide layers surrounding the floating gate are very much thinner: can

51 Interconnect: Programming Technologies EEPROM Usage for programming Unprogrammed state: the floating gate is uncharged Insulating oxide layers surrounding the floating gate are very much thinner: can be easily charged In the write mode, the floating-gate is charged negatively by electrons that tunnel from the drain to the floating gate: +15V voltage to the control gate and connecting both the drain and source to ground. In the read mode, the second transistor can discharge the floating gate 51

52 Interconnect: Programming Technologies EEPROM: Write Operation 52

53 Interconnect: Programming Technologies EEPROM: Read Operation 53 If the floating gate is charged with electrons, 5 volts on the control line will not be enough to turn that transistor on: thus the output will be high or '1' If the floating gate is discharged with electrons the 5 volts on the control line will turn that transistor on: thus the output will be low or '0'

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

DIGITAL CIRCUIT LOGIC UNIT 9: MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES 1 Learning Objectives 1. Explain the function of a multiplexer. Implement a multiplexer using gates. 2. Explain the