ADOSE DELIVERABLE D6.9; PUBLIC SUMMARY SRS Testing of components and subsystems

Transcription

1 RELIABLE APPLICATION SPECIFIC DETECTION OF ROAD USERS WITH VEHICLE ON-BOARD SENSORS ADOSE DELIVERABLE D6.9; PUBLIC SUMMARY SRS Testing of components and subsystems Issued by: AIT Austrian Institute of Technology September INTRODUCTION Deliverable D6.9 summarizes the testing efforts and results on the silicon retina stereo sensor (SRS) subsystems and components used in the ADOSE project. All tests conducted where performed with respect to the ADOSE specifications and other ADOSE documents. The recommendations that are given are based on the evaluation of the test results. The SRS final prototype does not fulfil completely all requirements due to a reduced resolution of the used image sensor. However, the proof of concept for the device functionality can be performed with the system. 2. SYSTEMS, SUBSYSTEMS AND COMPONENTS DEFINITION For a concise testing of the ADOSE SRS a clear definition and identification of the systems under test (SUT) and their components was necessary. The following sections identify the systems and their components by summarising their architecture and the consequent needs for testing. According to the hierarchy in their respective architecture we defined three system levels: system under test (SUT) subsystem under test (SSUT) component under test (CUT) In the ADOSE SRS developments two individual SUT can be identified Embedded Laboratory Prototype (ELP) Final Prototype (FP) Public Page 1 of 5

2 The objective of deliverable D6.9 is to report on the testing of subsystems and components of the systems levels. Architecture of the Embedded Laboratory Prototype (ELP) The ELP consists of two separate ATIS camera modules and an embedded data processing unit containing three embedded boards for signal acquisition and processing. Table 1 identifies the subsystems and components of the ELP. Each subsystem and components were referred to later in the tests with a unique ID. Table 1: ELP Design structure and Components Name Level ID Embedded Lab.Prototype SUT ELP ATIS-Camera SSUT ELP-CAM ATIS Image Sensor CUT ELP-CAM-IS (=IS) Data processing SSUT ELP-DP FIFO board CUT ELP-DP-FI TI-DSP board A CUT ELP-DP-TIA TI-DSP board B CUT ELP-DP-TIB (a) (b) Figure 1: Photographs of ELP-CAM (a) and of ELP-DP (b) Public Page 2 of 5

3 Architecture of the Final Prototype (FP) Table 2 shows the components of the FP system with subsystems identified. The FP consists of a subsystem main board holding the components FPGA-, DSP-board and the two ATIS image sensors. Figure 2 shows photographs of FP-C and FP-MB. Table 2: FP Design structure and Components Name Level ID Final Prototype SUT FP Main board SSUT FP-MB FPGA board CUT FP-MB-FP TI DSP board CUT FP-MB-TI ATIS Image Sensor CUT FP-MB-IS (=IS) Case SSUT FP-C (a) (b) (c) Figure 2: Photographs of FP-MB (a) and FP-C front and backside (b),(c) sub systems under test. Public Page 3 of 5

4 3. TEST STRATEGY AND SPECIFICATIONS Test strategy The systems have been tested versus the requirements and specifications defined in existing ADOSE documents. Subsystem and component tests were conducted as measurements resulting in a measured value that is compared against a target value, which is either stated directly in the specification or requirement documents or derived from them. Figure 3 shows the applied test strategy process. Requirements Direct or derived values Test Plan Specifications Test configuration (S)SUT/CUT Measured test value Target value Test Equipment/ Method Pass/fail Test result Test Protocol Figure 3: Test strategy The test protocol documented the results for each test listed in the test plan. The result consist of the measurement result (a value) and the test result, stating whether the test passed or failed. Given the experimental nature of the project a conditional pass ( c/passed ) was considered also an acceptable test result for the tests but a detailed statement on the conditions and explanation of the reasoning and consequences had to be supplied. Public Page 4 of 5

5 4. CONCLUSIONS AND RECOMMENDATIONS Conclusions: 1. The stereo depth resolution of the FP was sufficiently smaller than required but still sufficient for the final demonstration. This is a direct consequence of the reduced stereo base line. The stereo baseline of the FP is sufficiently smaller than specified as a larger base line would have caused unacceptable cost increase and bulky design for the embedded device, resulting in a problematic incar integration. A proof of concept is still possible with the present resolution. 2. The image sensor horizontal resolution is smaller than required as a larger chip would have caused unacceptable cost increase. For the proof of concept within the research project the horizontal resolution of 304 pixel is sufficient. 3. The operation temperature range of the FP is smaller than required. The realization of a wider temperature range would have caused increased effort and unacceptable cost increase. 4. The communication between the DSP and FPGA of the FP is still not fully working due to electronic design errors in the first version of the FP. Recommendations: 1. The required depth resolution can be achieved with a 23 cm baseline and a higher resolution imager (see 2). 2. For a final product version an imager design with a reduced pixel pitch of ~13µm and an increased horizontal resolution of ~512 pixel would be required. 3. An extended temperature range can be achieved by selecting suitable electronic components and by an automated control of the imager operating point by the embedded system SW (adaptation and control of sensor bias voltages). The onboard temperature sensing of the FP can be utilized for this functionality. 4. DSP-FPGA data communications will have to be fixed by means of HW workarounds. Public Page 5 of 5