MicroLED Displays 2018

Transcription

1 From Technologies to Market MicroLED Displays 2018 Courtesy of Sony Sample

2 OBJECTIVE OF THE REPORT Everything You Always Wanted to Know About µled Displays! Understand the Current Status of the µled Display Technologies: What are microled? What are the key benefits? How do they differ from other display technologies? What are the cost drivers? What are the remaining roadblocks? How challenging are they? Deep understanding of the technology, current status and prospects, roadblocks and key players. Detailed analysis of key technological nodes: epitaxy, die structure and manufacturing, front plane structure and display designs, color conversion, backplanes, massively parallel pick and place and continuous assembly processes, hybridization, defect management, light extraction and beam shaping. Which applications could µled display address and when? Detailed analysis of major display applications: TV, smartphones, wearables, augmented and virtual reality (AR/VR/MR), laptops and tablets, monitors, large LED video displays... What are the cost targets for major applications? How do they impact technology, design and process choices? How disruptive for incumbent technologies: LCD, OLED, LCOS MicroLED display application roadmap, forecast and SWOT analysis Competitive Landscape and Supply chain Identify key players in technology development and manufacturing.who owns the IP? Potential impact on the LED supply chain: epimakers, MOCVD reactor and substrate suppliers. Potential impact on the display chain: LCD and OLED panel makers. Scenario for a µled display supply chain. 2

3 Biography & contact Eric Virey - Principal Analyst,Technology & Market, Sapphire & Display Dr. Eric Virey serves as a Senior Market and Technology Analyst at Yole Développement (Yole), within the Photonic & Sensing & Display division. Eric is a daily contributor to the development of LED, OLED, and Displays activities, with a large collection of market and technology reports as well as multiple custom consulting projects. Thanks to its deep technical knowledge and industrial expertise, Eric has spoken in more than 30 industry conferences worldwide over the last 5 years. He has been interviewed and quoted by leading media over the world. Previously Eric has held various R&D, engineering, manufacturing and business development positions with Fortune 500 Company Saint-Gobain in France and the United States. Dr. Eric Virey holds a Ph-D in Optoelectronics from the National Polytechnic Institute of Grenoble. 3

4 COMPANIES CITED IN THE REPORT Aixtron (DE), Aledia (FR), Allos Semiconductor (DE), AMEC (CN), Apple (US), AUO (TW), BOE (CN), CEA-LETI (FR), CIOMP (CN), Columbia University (US), Cooledge (CA), Cree (US), CSOT (CN), elux (US), emagin (US), Epistar (TW), Epson (JP), Facebook (US), Foxconn (TW), Fraunhofer Institute (DE), glō (SE), GlobalFoundries (US), Goertek (CN), Google (US), Hiphoton (TW), HKUST (HK), HTC (TW), Ignis (CA), InfiniLED (UK), Intel (US), ITRI (TW), Jay Bird Display (HK), Kansas State University (US), KIMM (KR), Kookmin U. (KR), Kopin (US), LG (KR), LightWave Photonics Inc (US), Lumens (KR), Lumiode (US), LuxVue (US), Metavision (US), Microsoft (US), Mikro Mesa (TW), mled (UK), MIT (US), NAMI (HK), Nanosys (US), NCTU (TW), Nichia (JP), Nth Degree (US), NuFlare (JP), Oculus (US), Optovate (UK), Osterhout Design Group (US), Osram (DE), Ostendo (US), PlayNitride (TW), PSI Co (KR), QMAT (US), Rohinni (US), Saitama University (JP), Samsung (KR), Sanan (CN), SelfArray (US), Semprius (US), Smart Equipment Technology (FR), Seoul Semiconductor (KR), Sharp (JP), Sony (JP), Strathclyde University (UK), SUSTech (CN), Sun Yat-sen University (TW), Sxaymiq Technologies (US), Tesoro (US), Texas Tech (US), Tianma (CN), TSMC (TW), Tyndall National Institute (IE), Uniqarta (US), U. Of Hong Kong (HK), U. of Illinois (US), Veeco (US), VerLASE (US), V-Technology (JP), VueReal (CA), Vuzix (US), X- Celeprint (IE) and more. 4

5 TABLE OF CONTENTS Executive summary p10 Introduction to microled displays p51 Definition and history What is a microled display? Comparisons with LCD and OLED Assembly Display structure SWOT analysis MicroLED display manufacturing yields p63 Overview Individual die testing. KGD mapping and individual transfer Transfer fields and interposers Defect management strategies Yield roadmap Redundancy Conclusions MicroLED epitaxy (FE Level 0) p79 Wafer size Wavelength homogeneity Epitaxy defects Cycle time and thickness Blue shift Wafer flatness GaN-based red chips Conclusions and impact on supply chain Chip manufacturing and singulation (FE Level 1) p96 MicroLED singulation p97 Impact on cost related to the epiwafer Illustrations MicroLED efficiency p104 LED and microled efficiency Development thrust areas Current confinement structures Status MicroLED chip manufacturing p112 Example of process flow Apple 6 masks Lithography Fab types comparison: infrastructure & equipment MicroLED in CMOS fabs Transfer and assembly technologies p124 5

6 TABLE OF CONTENTS Overview p125 Major types and key attributes of transfer processes Challenges Pick and place processes p129 Sequence and challenges Transfer sequences Transfer array Vs. display pixel pitch Throughput and cost drivers Direct transfer vs. interposer Interposer and yields Other use of interposers. Example (X-CeLeprint) Continuous/ semi-continuous assembly p141 Overview Laser-based sequential transfer QMAT-TESORO Uniqarta GLO Optovate Self assembly p150 Fluidic self assembly Example: Sharp/ELUX Summary p154 Intellectual property landscape Selectivity Major transfer processes: most mature Transfer processes: others Conclusion Transfer and assembly equipment p165 Introduction Traditional single chip tools Assembly environment Specific challenge for mass transfer Bulk microled arrays p171 Full array level microdisplay manufacturing. Hybridization & bonding process Wafer level bonding Monolithic integration of LTPS TFT: lumiode 3D integration: Ostendo Yields and costs Color generation in bulk arrays 6

7 TABLE OF CONTENTS Pixel repair p183 Emitter redundancy Example of repair strategies Defect management strategies Light extraction and beam shaping p189 Optical crosstalk Emission pattern, viewing angle and power consumption Emission pattern and color mixing Die-level light management Array-level beam shaping Color conversion p204 Overview Phosphors Quantum dots Flux requirements Patterning and deposition Backplanes and pixel driving p214 Introduction Channel materials for microled displays Mobility vs display specifications Stability and signal distortion Pixel density Analog driving: microled driving regime MicroLED-specific challenges Illustration: 75 4K TV, QHD smartphone Digital driving: introduction Digital driving: benefits & challenges Hybrid driving Analog Vs digital: summary TFT versus discrete micro IC. Cost zspects Cost reduction path Conclusions Economics of microled cost down paths p240 Baseline hypothesis and sensitivity Television p247 Cost target and price elasticity 75 TV panel assembly strategies Yield impact Very large panels Benefit of sequential transfer Interposers Die size Cost-down path 7

8 TABLE OF CONTENTS Smartphones p265 Cost target Illustration: 6 QHD phone panel Key outputs Die size optimization Interposers Applications and markets for microled displays p277 MicroLED attributes vs application requirement Application roadmap SWOT per application Key hypothesis for equipment forecast microled adoption forecast AR, MR and VR p284 The reality-to-virtual-reality continuum. Market volume headset forecasts for VR and ar MicroLED adoption and volume forecast Head up displays Smartwatches p290 Smartwatch volume forecast MicroLED Adoption and volume forecast Smartphones p294 Who can afford a smartphone? Smartphone panel volume forecast Mobile phones: display for differentiation Foldable smartphones MicroLED adoption and volume forecast TVs p301 The Better Pixel Resolution TV panel forecast 8K adoption MicroLED adoption and panel volume forecast Others: tablets, laptops, monitors p310 Overview Tablets Laptop and convertibles Desktop monitors Wafer and equipment forecast p315 Epiwafer MOCVD Transfer equipment 8

9 TABLE OF CONTENTS Competitive landscape p322 Time evolution of patent publications Leading patent applicants What happened In the last 18 months Time evolution of patent applications per company Breakdown by company headquarters Positioning of established panel makers Breakdown by company type Supply chain p332 Overview Capex aspects Supply chain requirement Front END (LED Manufacturing) Back end: backplane, assembly and module. Supply chain scenarios Intellectual property Conclusion 9

10 SCOPE OF THE REPORT This report provides an extensive review of µled display technologies and potential applications as well as the competitive andscape and key players. Smartwatches and wearables Virtual reality Oculus Apple Augmented/Mixed Reality TV LG MicroLED TV prototype (Sony, CES 2012) Smartphones Samsung Laptops and convertibles Contrary to the 2017 edition, this report does not cover applications in large LED videowalls: those will be discussed extensively in our upcoming report on miniled applications and technologies Large video displays Microsoft Automotive HUD BMW Tablets Acer HP The report does not cover non-display applications of µled: AC-LEDs, LiFi, Optogenetics, Lithography, lighting 10

11 Chips (to scale) Packages (Not to scale) SCOPE OF THE REPORT 11

12 WHO SHOULD BE INTERESTED IN THIS REPORT LED supply chain: sapphire makers, MOCVD suppliers, epi-houses. Understand the µled display opportunity What does it entail for the LED supply? What are the technical challenges? How can my company participate in this emerging opportunity? Who should we partner with? R&D Organizations and Universities Understand the market potential of your technologies for this emerging market Identify the best candidates for collaboration and technology transfer. OEMs/ODMs What are the potential benefits of µled displays? Are they a threat or an opportunity for my products? When will they be ready Should I get involved in the supply chain. Display Makers and supply chain Hype versus reality: what is the status of µled displays? What can we expect in the near future? Are they a threat to my LCD and OLED investments? Which display applications and markets can µled displays address? A detailed roadmap. Find the right partner: detailed mapping of the µled ecosystem and supply chain OSAT and foundries Are µled a new opportunity for my company? Venture capital, financial and strategic investors. Hype versus reality. Understand the technology and the real potential. How is the supply chain shaping up? Identify the key players and potential investment targets. Could µled hurt my existing investments? 12

13 MAJOR MANUFACTURING TECHNOLOGY BRICKS Substrate Epitaxy & wafer processing Pixel Assembly Defect Management Color Light Extraction & shaping Pixel Driving mm Sapphire mm Silicon Epi Litho Single wafer Multi wafer Mask Aligners Steppers Testing and binning Die-level (KGD map) Monolithic Arrays Hybridization Monolithic Integration Massively Parallel Pick and Place Electrostatic Electromagnetic Magnetic Adhesive Fluidic assembly Film cartridges Flexographic Laser Test Binning Repair Contactless Optical (PL) Contactless Electrical (EL) Interposers with KGD KGD transfer only [1] Pixel Redundancy Pixel Repair Pick and replace Add repair Color conversion Direct RGB LED Quantum dots Nanophosphor Optically pumped quantum wells Die Level (shaping, mirrors) Pixel bank level (mirrors, black matrix) External optics Backplanes Semicontinuous Si- CMOS TFT LTPS Oxide Micro Drivers Transfer field level [1]: need Known Good Die (KGD) map and addressable transfer process 13

14 MicroLED DISPLAYS TECHNOLOGY EVOLUTION Cree: Micro-led arrays with enhanced light extraction University of Strathclyde: active matrix and color conversion HKUST: Full color with phosphor conversion Sony: 55 FHD microled TV at 2012 CES LETI: Monochrome active matrix > 2000 PPI Ostendo: full RGB 5000 PPI 14

15 ASSEMBLY The art of making µled displays consists in processing a bulk LED substrate into an array of micro-leds which are poised for pick up and transfer to a receiving substrate for integration into heterogeneously integrated system: the display (which integrates, LEDs, transistors, optics, etc.). Epiwafers can accommodate 100 s of millions of µled chips compared to 1000 s with traditional LEDs. Monolithic integration of µled arrays is preferred for the realization of displays with high pixel densities. The micro-leds can be picked up and transferred individually, in groups, or as the entire array of 100,000 s of µleds: Low to Mid Pixel density: Pick and Place Laptop/ TV Wearable Smartphones VR Tablets Samsung Apple Oppo Oculus High Pixel Density: Monolithic Array Integration Projection micro display µled array AR/MR Microsoft Si-CMOS Backplane µled epiwafer LTPS or Oxide TFT backplane µled epiwafer Backplane Hybridization Pixel Per Inch

16 TRANSFER FIELDS AND INTERPOSERS Epiwafer wavelength homogeneity and defective die map. If individual functional die testing not available, use PL + traditional surface inspection. Yield loss = hatched surfaces + transfer fields where the number n of KBD and point defects exceeds specification. Transfer field with n point defect are eliminated. Interposer with only good transfer fields Transfer directly to backplane or create interposers with transfer fields that are within the wavelength bin and n KBD/point defects. Some bad die are transferred and need to be repaired. 16

17 DEFECT DENSITY For the smallest die required for TV or smartphone applications, the largest allowable defect size will fall below 1 µm The actual specification and the maximum acceptable defect size will depend on: The die size The chip structure The yield and defect management strategy adopted by each manufacturer: driven by cost of ownership (cost of increasing yield vs managing defects) A plot of a simple Murphy defect density model with a triangular distribution shows that to get 90% of 1x1 cm 2 transfer fields defect free, the defect density needs be 0.1/cm 2. For 2x2 cm 2 transfer fields, the requirement increases to <0.03 defect/cm 2. Larger stamps quickly lead to unacceptable wafer yield losses and/or unrealistic demands on defect density and can only be envisioned if efficient downstream yield management and repair techniques can be deployed. Regarding defect size, abiding by the 1/5 th rule used in semiconductor manufacturing, a 3x3 µm µled will likely require ~1 µm features or less, which could be bringing the acceptable defect size to about 0.2 um. Even if more relaxed targets are acceptable, µm seems like a reasonable range. Above: plot of a simple Murphy defect density model with a triangular distribution. This model is widely used in the semiconductor industry for estimating the effect of process defect density. More complex models should be used to account from the fact that defects often ten d to appear in clusters etc. 17

18 EXAMPLE OF PROCESS FLOW APPLE 6 MASKS Carrier Substrate p-gan MQW n-gan Substrate Mask#5: opening of the sacrificial layer (about 1 x 1 µm), dry etching (CF4 or NF3) or wet etching (more likely to produce the overhang) p-gan MQW n-gan Substrate Stabilization layer deposition: Spin coating of thermosetting material such as benzocyclobutene (BCP) + adhesion layer (e.g.: AP3000 from Dow chemical). Cured to 70% so it doesn t reflow p-gan MQW n-gan Substrate Carrier wafer bonding (Semi-cured stabilization layer provides sufficient adhesion) Ohmic contacts n-gan MQW p-gan n-gan MQW p-gan n-gan MQW p-gan Carrier Substrate Epitaxial substrate removal (LLO) Carrier Substrate n-gan dry etching or CMP Carrier Substrate Mask #6: deposition and patterning of ohmic contacts (NiAu or NiAl, typ. 50 Å thick) Annealing at 320 deg. C. for 10 minutes n-gan MQW p-gan n-gan MQW p-gan n-gan MQW p-gan Carrier Substrate ITO deposition (typ. 600 Å thick) Carrier Substrate Planarization resist Carrier Substrate Resist is stripped (wet etching or plasma ashing) until the ITO and the passivation layers are removed from the bottom of the large mesa, exposing the sacrificial layers. Residual resist is then fully stripped 18

19 CHIP MANUFACTURING: SUMMARY Substrate platform Traditional LED Manufacturing Sapphire dominant Little opportunity for Silicon µled Display Manufacturing xxxxxxxxxxx µled displays might require a paradigm shift from traditional LED manufacturing to silicon CMOS-type of environment and tools. Clean Room Lithography Plasma Etching Laser Lift Off (sapphire-based platform) Class 10,000 and above Mask aligners, single shot Sidewall quality not critical to LED efficiency. High tolerance for particles Marginal Paradigm shift? xxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx xxxxxxxxxxxx Wafer Bonding Marginal xxxxxxxxxxxx Testing PL + EL Probe testing xxxxxxxxxxxxx 19

20 KEY ATTRIBUTES OF TRANSFER PROCESSES Throughput Yields Capability KGD compatibility Intellectual Property Cost Cycle time Number of die per cycle Pick up Drop off Assembly/Interconnect Die size Die Shape Placement accuracy Individual die addressability Interfacing with inspection/test equipment KGD map Freedom of exploitation Licensing Equipment cost Footprint Consumables (transfer stamp etc.) Cost of Ownership 20

21 DIRECT TRANSFER VS. INTERPOSER Interposers (intermediate carriers) or various forms of pixel banks can be used for: - Binning / yield management purpose - Intermediate pitch step up - Pre-assembly of RGB or RGB + driver IC sub-assembly Red, Green, Blue LED Epiwafers Transistor backplane (TFT, direct hybridization on Silicon ) 21

22 TRANSFER AND ASSEMBLY Massively parallel P&P technologies are the most mature. As of Q2-2018, massively parallel pick and place methods are the most mature, lead by X-Celeprint and Apple with passive (PDMS stamps) and active (MEMS) transfer head respectively. Various other companies have demonstrated display prototypes assembled with similar technologies: XXX, XXX, XXX and probably more who haven t publically shown their work. Semi-continuous or self assembly processes have also been pitched and/or demonstrated by a variety of companies including Vuereal and elux. Semi-continuous process reduce the cycle time by reducing or eliminating the X-Y print-head motion steps between donor and receiver substrate (see discussion in the Cost Analysis section of this report). Laser transfer potentially offers compelling benefits such as high throughput and compatibility with KGD yield management strategies. But development is less advanced than massively parallel P&P. To our knowledge, glō is so far the only company to have realized display prototypes using the concept. Massively Parallel P&P Leading companies Continuous/Semi-Continuous and self assembly Laser Processes 22

23 TRANSFER PROCESSES: MOST MATURE xxxxxx xxxxxxx xxxxxxxxxx xxxxxxxx Type Pick & Place Pick & Place Self Assembly Sequential Sub-type xxxxx xxxxxx xxxxxx xxxxxx Cycle time 10-15s (est) 30s, target 10s Continuous Continuous Scalability Placement accuracy Constrain on die structure Yield status (Q12018) Small to mid size stamps (1-2?) Probably challenging to scale up ( Up to XX cm stamp demonstrated but unknown impact on yield, placement accuracy and cycle time Current work on XXX tool delivers 50M die/hr throughput.? ±1.5µm 3 ~ ± 2.5 µm (determined by xxxxx) ±1.0 µm Flat top surface required Horizontal or vertical Flat top surface required Tether and anchors Horizontal or vertical Horizontal LED Circular geometry preferred.? 3N to 4N 2N8 > 4N Die Size As small as 3 µm As small as 3 µm As small as 10 µm but perform better above µm Wafer size (up to 6 ) Vertical LEDs 2 to 20 µm Active stamp [2] xxxxxxxx No NA Yes. Placement selectivity KGD management xxxx Strengths Possible high accuracy Limitations High cost stamps Scalability (large areas?) Via additional step to eject bad die from the stamp. Low cost stamp Possibly scalable Not addressable Die size can affect cycle time Die binned/sorted upstream (laser lift off) Yes (placement selectivity) Potentially very cost-effective KGD management, throughput Best for low PPI (0.2 to 1 mm pitch) Large die Need transparent substrate (sapphire or interposer) 23

24 HYBRIDIZATION: EXAMPLES OF BONDING PROCESS Hybrid bonding: Cu + oxide Microtube bonding Hybrid bonding: Cu + Polymer Hybridized active-matrix GaN 873 x 500 pixel microdisplay at 10 μm pitch using microtube bonding (LETI) 24

25 EMISSION PATTERN AND COLOR MIXING If the red, green and blue emitters have different light emission patterns, the color calibration performed at one angle (typically perpendicular to the display plane) will shift when viewed off-angle as the relative intensities of R,G,B viewed in that given direction will changes. This issue often occurs when the red emitter is formed from a different material (InGaAlP) and has a different structure than the green and blue die (InGaN) [1]: Hypothetical beam pattern of Red, Blue and Green emitters (not actual, illustration purpose): the relative intensity of the red green and blue emitters at 0 degree and 30 or 60 degrees varies, resulting in a shift of color balance at those different angles. (Source: Yole Development) 25

26 FLUX REQUIREMENTS Max Display Brightness (Cd/m 2 ) Pixel Density (PPI) LED Chip Size Optical Flux at LED surface [1] (W/cm 2 ) Driving current (A/cm 2 ) TV 4k X µm xxx-xxx xxx-xxx Likelihood that quantum dots color conversion be adopted TV 8K X µm xxx-xxx xxx-xxx Wearable X µm xxx-xxx xxx-xxx Smartphone X µm xxx-xxx xxx-xxx RGB AR/MR (State of the art) 5, X um xxx-xxx xxx-xxx RGB AR/MR (Goal) 500, X µm xxx-xxx xxx-xxx [1]: for all applications, it is assumed that the downconverter is deposited directly at the surface of the pixel (discussion next page). In addition, an overall optical efficiency of 60% for the red and green pixels and 80% for blue (unconverted) was assumed. [2]: optimal efficiency with GaN LED is achieved with current density in the 1-10 A/cm2 range. For applications where the required driving current is significantly below that range, the LED will likely be driven in pulsed mode, ie at higher current density with a low duty cycle 26

27 INTRODUCTION Driving emissive displays (OLED, µled) requires complex compensation schemes The different functions required for active display driving are shared between discrete ICs positioned at the edges or behind the panel and Thin Film Transistor (TFT) circuitry deposited directly onto the display substrate (=backplane). Emissive displays such as OLED or microled are current-driven. The simplest mode of operation for the TFT circuit requires 2 transistors and 1 capacitor (2T1C). However, very small variations in current result in visible brightness differences visible by the human eye. The 2T1C simple design doesn t compensate for pixel to pixel variations in the threshold voltage, carrier mobility, or series resistance that result from TFT processing or from variability in the emitters (LED or OLED) Compensation schemes relying on a larger number of transistors per pixel (up to 7 in some designs) are therefore used. The complexity of the TFT however can be reduced in some designs by offloading some of the compensation function onto external ICs [1]. Row Driver Column Driver Timing Controller Gamma circuit Test circuits etc. Simple, non compensated pixel circuit with 2 transistors [1] TFT Pixels Other circuits Simple block diagram for display driving Power Example of a 4 transistor compensated circuit [1] [1]: Source: AM backplane for AMOLED ; Min-Koo Han, Proc. of ASID 06, [1]: LG OLED TV for example are driven by 2T1C circuit with compensation performed by external ICs 27

28 ILLUSTRATION: 75 4K TV MicroLED makers usually strive to: Use the smallest die possible to minimize cost. Operate close to peak efficiency in the typical brightness range of the display. For a 75 4K TV, a 1000 Nits brightness can be achieved with XX µm die operated near peak efficiency at XX A/cm2 (blue and green chips). At this average brightness level, the current per chip is XX µa. For the lowest and highest brightness levels, the current range between XX na and XX na Panel characteristics Die size Peak Brightness Average Brightness Lowest brightness LED emission pattern Optical efficiency (Photon losses in pixel cavity, external optic etc..) 75 Inch diagonal 4K resolution (3840x2160) 5 x 5 um 3000 nits 1000 nits 3 nits Lambertian (120 APEX angle) 80% Display Brightness Current Density Current EQE Low (3 Nits) XXX A/cm2 XX µa 14% 20% Average (1000 Nits) Peak (3000 Nits) XXX A/cm2 XX µa 22% XXX A/cm2 XX µa 19% 10% 28

29 TFT VERSUS DISCRETE MICRO IC. Another debate is whether TFT used for OLED panel driving (LTPS for smartphones and wearable, Oxide for TVs) are suitable for microled. Due to the non linear characteristics of microled, the different ranges of operating currents and the added complexity of using 2 types of semiconductors in RGB solutions (InGaN and InGaAlP), driving circuits will likely be more complex than OLED and integration with traditional TFT be more challenging. Apple/Luxvue and X-Celeprint have both suggested using discrete Si-Based microdrivers to drive the pixels. X- Celeprint has demonstrated multiple display prototypes using this concept. Sub pixel with 2x µled redundancy IC driver A µled display where discrete ICs positioned on the front face drives groups of 12 subpixels featuring a 2x redundancy. (Source: LuxVue patent US 9,318,475) Patent XXX from XXX [1] [1]: we believe that XXX is a company created by Apple and under which name its has been filing its microled patents after

30 COST ANALYSIS: INTRODUCTION Many unknowns in term of technological choices prevent detailed cost modeling but a high level analysis can still provide valuable insights At the current stage of maturation of the industry, there are still many plausible technology and process choices. This precludes comprehensive cost modeling. However, there are some fundamentals that anchor all those processes: alignment dominates assembly cycle times, die size can t get infinitely small, and epitaxy has already been through a more than 20 years cost reduction curve. Basic cost analysis can therefore be performed to narrow the process space to a more economically realistic window. The objective of this section is to provide such analyses for the major building blocks and cost contributors in to order validate the fundamental economics of microled displays and identify credible cost-down paths and targets. The effort is focused on the 2 high volume applications where microleds have the most potential to both disrupt the existing display chain and generate large, new business opportunities:tv and Smartphones. Die: Size, cost, redundancy, yield By defining cost targets and performing a basic cost analysis within realistic process parameters, it is possibly to narrow the size of the process windows compatible with economical targets for each application. Current microled process window Realistic process window narrowed down with high level cost analyses Product and volume manufacturing -compatible process window Assembly: Cycle time, yield, stamp size, sequential/continuous, self assembly, redundancy 30

31 75 TV PANEL ASSEMBLY STRATEGIES We first consider the following 3 assembly scenario with increasing transfer stamp sizes and no interposers: x mm 2 transfer stamps 86 transfer fields per wafer 86% of the wafer surface used 9694 transfer cycle per color x mm 2 transfer stamps 75 TV Panel 18 transfer field per wafer 72% of the wafer surface used 2442 transfer cycle per color x mm 2 transfer stamps 1 transfer field per wafer 64% of the wafer surface used 170 transfer cycle per color Drawings approximately to scale 31

32 SEQUENTIAL TRANSFER 4N YIELD 32

33 CAPEX Investment to set up a microled fab should be at least on par and most likely lower than that of an OLED or even Oxide TFT LCD Fab 33

34 COST TARGET The microled die + assembly budget to strictly match OLED by 2022 is around ~$XX. If microled can deliver unique and desirable features that no other panel technologies can offer (e.g.: sensing functionalities, superior and local brightness adjustment, reduced power draw etc.), this cost budget could increase up to $XX, after budgeting for additional cost related to those new functionalities (microsensors etc) 34

35 MICROLED APPLICATION ROADMAP Now (2018) Longer term Small pitch (<2mm) large video displays. Brings significant performance improvement (contrast) and potential cost reduction (eliminates LED package) Large die OK (30 µm) but low transfer efficiency. Available from Sony since 2017: Smartwatch and wearables xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxx. xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxx. xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxx. AR/MR HMDs xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxx. xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxx. xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxx. xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxx. Virtual Reality (VR) High cost. Limited benefits vs OLED. High end TVs and monitors (4K, HDR) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxx. Smartphone xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx. xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxx. Tablets and laptop xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx. Xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx. Automotive HUD Xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx. Other Automotive Displays xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx 35

36 MICROLED TV PANEL VOLUME FORECAST Distinguishing 8K is important since they feature 4x more microled die than 4K panels 36

37 BREAKDOWN BY COMPANY TYPE 37