Logic synthesis for post-cmos technologies

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1 Logic synthesis for post-cmos technologies Eleonora Testa Integrated Systems Laboratory EPFL, Lausanne, Switzerland Joint work with Mathias Soeken and Giovanni De Micheli February, 2017

2 Logic synthesis HDL module function ( a, b, c, f); input a, b, c; output f; wire w0, w1, w2; assign w0 = a & b; assign w1 = a b& c; assign w2 = w0 w1; assign f = w2; endmodule a c Translate into gate level f b c Optimization &technology mapping a f Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

3 Logic synthesis Optimization I Technology independent optimization 3 more strategies 7 not specific does not consider the technology I Technology aware optimization 3 better results 7 not general different for each technology Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

4 Technology aware optimization CMOS Technologies: NAND/NOR-based VDD Emerging Technologies: 1. different primitives A B B OUT 2. technological constraints A Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

5 Outline Majority-based optimization Constraint-based logic synthesis Conclusions Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

6 Outline Majority-based optimization Constraint-based logic synthesis Conclusions Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

Majority-based optimization QCA [1] SWD [2] INV INV F F Z ZN A B C A A B

, Genetic Algorithm based Logic Optimization for Multi-Output Majority

7 Majority-based optimization QCA [1] SWD [2] INV INV F F Z ZN A B C A A B C IN [1] M. Houshmand et al., Genetic Algorithm based Logic Optimization for Multi-Output Majority Gate- Based Nano-electronic Circuits. In ICIS, [2] O. Zografos et al., Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS. In NANO, Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

Majority-based optimization RRAM [3] Internal resistance state Z n is a function of the previous resistance state Z, the voltage at terminal P, and the voltage at Q Z n = hpqzi Z n P Q

8 Majority-based optimization RRAM [3] Internal resistance state Z n is a function of the previous resistance state Z, the voltage at terminal P, and the voltage at Q Z n = hpqzi Z n P Q Z [3] P.-E. Gaillardon et al., The programmable logic-in-memory (PLiM) computer. In DATE, Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

9 Majority-based optimization Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

10 Majority-based optimization Majority logic: I hxyzi = xy _ xz _ yz =(x _ y)(x _ z)(y _ z) I hxy0i = x ^ y hxy1i = x _ y I Axiomatic system.c : Commutativity hxyzi = hyxzi = hzyxi.m : Majority hxxzi = x hx xzi = z.a : Associativity hxuhyuzii = hzuhyuxii.d : Distributivity hxyhuvzii = hhxyuihxyvizi.i : Inverter propagation h xȳ zi = hxyzi Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

11 Majority-based optimization I Data structure for Boolean functions based on majority logic: Majority-Inverter Graphs (MIGs) [4] L. Amarú et al., Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. In DAC, Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

12 Majority-based optimization I Homogeneous logic network consisting of 3-input majority nodes and regular/complemented edges I Optimization of functions thanks to majority logic properties [5] f f 1 z 1 y Optimization z 1 w x 1 w x 1 y z [5] L. Amarú et al., Boolean logic optimization in Majority-Inverter Graphs. In DAC, Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

13 Results: SWD I Majority enables SWD synthesis Benchmark ADPP SWD 10nm Ref. Impr. (x) BKA HCA CSA DTM WTM DTM GFMUL MAC DIV CRC Average ADPP: Area-Delay-Power-Product, Impr: improvement. [2] O.Zografos et al.. Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS. In NANO, Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

14 Results: RRAM I RRAM-based circuit benefits from MIG synthesis Benchmark naïve Rewriting and compilation #N #I #R #I Impr. #R Impr. adder % % log % % max % % multiplier % % sin % % sqrt % % square P % % % % #N: number of MIG nodes, #I : number of instructions, #R: number of RRAMs. [6] M. Soeken et al, An MIG-based compiler for programmable logic-in-memory architectures. In DAC, Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

15 Inversion minimization.i : Inverter propagation h xȳ zi = hxyzi f = x y z f = x y z x x z x y z x y z x y z x y Inversion minimization 1. Tree based exact algorithm 2. SAT based exact algorithm 3. Heuristic algorithm by local rewriting Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

16 Results: QCA I QCA-based circuits benefit from inverter minimization Benchmark #N #L #E MIG Optimized MIG Impr. #INV #QCA cells #INV #QCA cells adder % log % max % multiplier % sin % sqrt % square % Average 4.9% #N: number of MIG nodes, #L: number of levels in the MIG not considering inverters, #E: number of edges, #INV : number of inverters, #QCA cells: number of QCA cells, Impr: improvement of the minimal values with respect to the initial MIG. [7] E. Testa et al., Inverter Optimization in Majority-Inverter Graphs. In NANOARCH, 2016 Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

17 Outline Majority-based optimization Constraint-based logic synthesis Conclusions Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

18 Constraint-based logic synthesis Emerging Technologies: 2. technological constraints Some examples I Limited number of outputs for each node = limited fan-out (e.g. optical devices) I Limited depth (e.g. quantum computing) I Inversion distribution (e.g. RRAMs) I More than one constraint (current work) Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

19 Constraint-based logic synthesis Emerging Technologies: 2. technological constraints Conventional approach When considering constraints: a b a c f Optimization a b a c f Optimization & Constraints b c a f? Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

20 Constraint-based logic synthesis Problem: Given some constraints and a Boolean function f,doesthereexist acircuitthatcan realize the function f within the given constraints? Constraint-solver SAT-solver b c 3 SAT 7 UNSAT a f Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

21 Outline Majority-based optimization Constraint-based logic synthesis Conclusions Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

22 Conclusions Majority-based optimization: 3 fast 3 abstract, applicable to a variety of technology 7 almost everything changes for each set of primitives 7 abstract Constraint-based logic synthesis: 3 general approach and easily extensible 3 exact solution 7 resource intensive, slow 7 requires new way of thinking Eleonora Testa - LSI/EPFL - Logic synthesis for post-cmos technologies - February,

23 Logic synthesis for post-cmos technologies Eleonora Testa Integrated Systems Laboratory EPFL, Lausanne, Switzerland Joint work with Mathias Soeken and Giovanni De Micheli February, 2017

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