Department of Computer Science and Engineering Question Bank- Even Semester:

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1 Department of Computer Science and Engineering Question Bank- Even Semester: CS6201& DIGITAL PRINCIPLES AND SYSTEM DESIGN (Common to IT & CSE, Regulation 2013) UNIT-I 1. Convert the following hexadecimal numbers into decimal numbers: i) 263 ii) 1C3 2. Plot the following function by using a K-map and determine its minterm and maxterm F= AB + BC. 3. What is the need for Gray code? 4. Simplify the following Boolean expression to minimum number of literals: xyz+x y+xyz. 5. What are universal gates? why are they named so? 6. Prove that a+a b=a+b. 8. What are the limitations of karnaugh map.? 9. Perform the following code conversions: ( ) 16 to binary, octal and decimal. 10. State the different ways for representing the signed binary numbers. 11. convert Y=A+Bc'+AB+A'BC into canonical form? 12. find the minimum expression of Y=Π (0,1,3,5,6,7,10,14,15) 13. State and prove De-Morgan s law & consensus theorem. 14. Name the various types of number systems with their bases and give an example for each. 15. Convert the following AND-OR network into an network of NAND gates. A B C 16.State the duality principle. D E X 17. Perform subtraction by two complement method : Find the dual and complement of F=x(y z +yz) 19. The solution to the quadratic equation is x=3 and x=6. What is the base the numbers? 20.What is meant by essential prime implicant? 1

2 PART-B 1. a) State and prove DeMorgan s theorem. b) Simplify the following function using K-Map: F(A,B,C,D) = m(0,1,3,4,6,7,8,9,11,12,13,14,15) 2. Simplify the following function using karnaugh map method & Tabulation method F(A,B,C,D) = (0,2,4,5,6,7,8,10,13,15) F(A,B,C,D) = (2,3,10,11,12,13,14,15) Y=m 0 +m 2 +m 4 +m 8 +m 9 +m 10 +m 11 +m 12 +m Use Boolean theorems and prove the following i) A+BA=A ii)a+a B=A+B iii)a B+BC+B C=AB+C iv) (A+B)(A+C)=A+BC v) ABC+AB C+A BC+AB C +ABC +A BC vi) (A+B+C)(A+B+C )(A+B +C )(A+B +C). 4. (i) Implement Boolean expression for EXOR gate using NAND and NOR gates. (8) (ii) Prove that ( AB + C + D )(C + D )(C + D + E ) = ABC + D. (4) (iii) Using 2 s complement perform (42)10 (68)10. (4) 5. (i)simplify the following Boolean function by means of the tabulation method: P(A,B,C,D,E,F)= F= m(0,1,9,15,24,29,30)+ d(8,11,31). (ii)simplify xy +y z +x z to a minimum number of literals 6. Analyze the combinational circuit shown in figure. Find the Boolean functions for the outputs as function of the inputs and explain the circuit operation. A B C D F 7. Explain the conversion of regular expression into canonical expression and their simplification in SOP and POS forms. 8. Illustrate the rules for Binary Addition and Subtraction using 2 s complement arithmetic. Give examples. 9. (i) Explain about Common postulates used to formulate various algebraic structures. 2

3 (ii)simplify the following Boolean expressions to a minimum number of literals: (i) AC + ABC + AC (2) (ii) XYZ + XY + XY Z (2) (iii) XY + YZ + XY Z (2) (iv) A B + ABD + AB D + ACD + ABC (5) (v) BD + BC D + A BCD (5) 10. Simplify the given Boolean function in POS form using K-map and draw the logic diagram using only NOR gates. F(A, B, C,D)= Σm (0,1, 4,7,8,10,12, 15)+ Σd (2, 6,11,14). 1. Draw the logic diagram for half adder. UNIT-II 2. Implement a full adder with 2 half adders (OR) How will you build a full adder using 2 half adders and an OR gate? 3. Implement a 4-bit even parity checker. 4. Write down the truth table of Full Subtractor & half sub tractor 5. What is the difference between decoder and demultiplexer? 6. Obtain the truth table for BCD to Excess-3 code converter. 7. Draw the circuit diagram for 3-bit parity generator. 8. Write down the difference between sequential and combinational circuits. 9. What do you mean by Combinational Logic Circuits? 10. Write the function of Multiplexers. 11. What is a Decoder & Priority Encoder? 12. Draw 4 bit binary parallel adder 13. What do you mean by carry look head adder and carry propagation delay? 14. What is code converter? 15. What do you mean by HDL? & List the modeling techniques available in HDL 16. Implement the function G= m(0,3) using a 2X 4 decoder. 17. Give short notes on Logic simulation and Logic synthesis 18. What do you mean by functional and timing simulation? 19. What do you mean by test bench? 20. Write the HDL description for the following circuit. 3

4 PART-B 1. (i)discuss the principle of operation of Carry-Look Ahead Adders with neat sketches. (ii) Implement the Switching Function F= Σ m (0,1,3,4,12,14,15) using 8-input MUX. (OR) Implement the following Boolean function with 16 X 1 Multiplexer F(A,B,C,D) = Σ(0,1,3,4,8,9,15). 2. (i) Show how to build a 4-to-16 decoder, using only 2-to-4 decoders. (ii) Explain full sub tractor & Half Subtractor circuit with diagram. 3. Design a BCD adder circuit 4. Design a combinational circuit for BCD to Excess-3 code converter (OR) Design a combinational circuit which accepts 3 bit binary number and converts its equivalent excess 3 codes 5. Design a magnitude comparator with three outputs: A>B, A=B and A<B (OR) Design a 4 bit magnitude comparator to compare two 4 bit number 6. Design a BCD to 7- Segment code converter. 7. Construct a 4-bit odd parity generator circuit using gates. 8. (i) Design a combinational logic circuit whose outputs are F1 = a'bc + ab'c and F2 = a' + b'c + bc' (ii) Realize the full adder circuit using 3-to-8 Decoder 9. Using a single 7483, Draw the logic diagram of a 4 bit adder/sub tractor 10. Construct a Full adder, Full sub tractor, Multiplexer and write a HDL program module for the same. UNIT-III 1. Convert a JK flip flop to T flip flop. 2. What is race around condition? 3. Differentiate Flip-Flop from Latches. 4. Draw the excitation table and state diagram for JK and SR Flip-Flop. 5. How many flip-flops are required to design a synchronous MOD 60 counter? 6. Write down the characteristics equation for J-K and T flip flops. 7. What is a Ring Counter and ripple counter? 8. Realize a JK flip-flop using D flip-flop be and gates (OR) Convert a JK flip flop to T flip flop. 9. Write the HDL code for counter using behavioral model. 10. What is a Binary Counter? 11. What is modulo n Counter? 12. What is meant by synchronous Sequential Circuits? 13. What do you meant by State Reduction 14. Define State Assignment 15. Define Shift Register 16. List out the classification of Shift Register 4

5 17. Write the HDL code for Shift register using behavioral mode 18. What is an excitation table? 19. Define sequence detector 20. What do you mean by Sequential Circuits? PART-B 1. (i) Explain the different types of shift registers with neat diagram. (ii) Discuss the operation of SR flip-flop with the help of a state diagram. 2. Design a sequence detector to detect the sequence Design and implement a Mod-5 synchronous counter using JK flip-flop. Draw the timing diagram also (OR) Design a MOD 5 asynchronous counter. Using a code converter at the output of the counter to convert the up counter into a down counter. (OR) Design a 3-bit Up/Down Counter. 4. (i) Explain the working of master slave JK flip-flop. (ii) Draw the diagram for a 3 bit ripple counter & UP/DOWN Counter. 5. Design a synchronous sequential circuit using JK flip-flop to generate the following sequence and repeat. 0,1,2,4,5,6 6. Design a MOD 16 up counter using JK flip-flops (OR) Design a synchronous counter with the following sequence: 0,1,3,7,6,4 and repeats. Use JK flip-flops. (OR) Design a Synchronous Counter that goes through the sequence 2,6,1,7,5,4 and repeat. Use J-K flip-flops. 7. (i) With suitable example explain state reduction and state assignment. (OR) (ii) Minimize the following state table Present State Next State,Z (Output) X(Input) 0 1 A A,0 B,0 B C,0 D,0 C A,0 D,0 D E,0 F,1 E A,0 F,1 F G,0 F,1 G A,0 F,1 (OR) Minimize the following state table Next state Present state Output 0 1 A D,0 C,1 B E,1 A,1 C H,1 D,1 D D,0 C,1 E B,0 G,1 5

6 F H,1 D,1 G A,0 F,1 H C,0 A,1 I G,1 H,1 (ii) Write the HDL description of counter/shift register. 8. Write the HDL description of T flip-flop and JK flip-flop from D flip-flops and gates. 9. Using the D flip-flop, design a synchronous counter which counts in the sequence 000, 001, 010, 011, 100, 101, 110, 111, and An asynchronous sequential circuit is described by the following excitation and output functions Z1 = x1x2'+(x1 + x2' )y & Z2 = y (i) Draw the logic diagram of the circuit. (ii) Derive the transition table and output map. (iii) Obtain 2 state flow table. (iv) Describe in words the behavior of the circuit. UNIT-IV 1. Distinguish between fundamental mode and pulse mode operation of asynchronous sequential circuits 2. What are races and cycles? 3. What is meant by critical race? 4. What is meant by race condition in digital circuit? 5. Define the critical rate and non critical rate 6. What is the significance of state assignment? 7. What are the steps for the analysis of asynchronous sequential circuit? 8. Write short notes on (a) Shared row state assignment (b) One hot state assignment 9. What are Hazards and List out the types of hazards? 10. What is a static 1/0 hazard? 11. What is dynamic hazard? 12. Describe how to detect and eliminate hazards from an asynchronous network?(or) How to eliminate the hazard? 13. Draw a circuit that has no static hazards and implement the boolean function F (A, B, C, D) = S (0,2,6, 7, 8, 10, 12) 14. Draw the wave forms showing static 1/0 hazard? 15. What are the assumptions that must be made for fundamental mode circuit? 16. What is meant by lockout condition? 6

17. What happens when a Hazard happens in a logic circuit? 18. Distinguish between the conventional flow table and primitive flow table. (OR) What is transition table?

(OR) What are the models used to represent clocked sequential circuits? PART-B 1. Explain essential, static and dynamic hazards in digital circuit.

7 17. What happens when a Hazard happens in a logic circuit? 18. Distinguish between the conventional flow table and primitive flow table. (OR) What is transition table? How it is differ from flow tables. 19. What is Primitive Flow Table? 20. What are the two types of Asynchronous Circuits? How do they differ? (OR) What are the models used to represent clocked sequential circuits? PART-B 1. Explain essential, static and dynamic hazards in digital circuit. Give hazard-free realization for the Boolean function. F(I, J, K, L) = Σ(1, 3, 4, 5, 6, 7, 9, 11, 15) 2. An asynchronous sequential circuit is described by the following excitation and output function. X = (Y1Z1 W2) + (Y1 Z1W2 ) & S = X (i) (ii) (iii) Draw the logic diagram of the circuit. Derive the transition table and output map. Describe the behavior of the circuit (OR) Derive a circuit specified by the following flow table. 3. With suitable example and diagram explain the hazards in combinational and sequential logic circuits. 4. (i) With necessary example and diagram explain the concept of reduction of state and flow tables. (ii) Find a critical race free state assignment for the reduced flow table shown. 5. Explain the steps for the design of Asynchronous Sequential circuits. 7

8 6. What is the objective of state assignment in asynchronous circuit? Explain race-free state assignment with an example 7. Design an asynchronous sequential circuit with inputs xl and x2 and one output z. Initially and at any time if both the inputs are 0, output is equal to 0. When xl or x2 becomes 1, z becomes 1. When second input also becomes 1, z = 0; The output stays at 0 until circuit goes back to initial state. 8. Draw the structure of fundamental mode synchronous sequential logic circuits and define the term input states, secondary (internal states), excitation variables and stable state. 9. Develop the state diagram and primitive flow table for a logic system that has 2 inputs,x and y and an output z.and reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z ot remains in the previous state. The logic system has edge triggered inputs with out having a clock.the logic system changes state on the rising edges of the 2 inputs. Static input values are not to have any effect in changing the Z output 10. Obtain the primitive flow table for an asynchronous circuit that has two inputs x,y and one output Z. An output z =1 is to occur only during the input state xy = 01 and then if the only if the input state xy =01 is preceded by the input sequence.(or) Design an asynchronous sequential circuit with two inputs X and Y and with one output Z. Whenever Y is 1, input X is transferred to Z.When Y is 0,the output does not change for any change in X. UNIT-V 1. How does ROM retain information? 2. Distinguish between PAL and PLA 3. Give the classification of memory 4. What is refreshing? How it is done? 5. Write a short notes on memory decoding 6. List the basic types of programmable logic devices 7. What is PAL? How it differ from PROM and PLA? 8. Write a short notes on PROM,EPROM,EEPROM 9. How many parity bits are required to form Hamming code if massage bits are 6? 10. How to find the location of parity bits in the Hamming code? 11. Generate the even parity Hamming codes for the following binary data 1101, A seven bit Hamming code is received as What is the correct code? 13. Compare static RAMs and dynamic RAMs 14. Define PLD and Combinational PLD 8

9 15. What is a decoder and obtain the relation between the number of inputs 'n' and outputs 'm' of a decoder? 16. Draw and explain the basic structure of ROM. 17. Draw the logic diagram of one bit static RAM cell. 18. Differentiate between EPROM and EEPROM. 19. What are the different types of PLDs? 20. Distinguish between SRAM and DRAM PART-B 1. Draw a neat sketch showing implementation of Z1 = ab'd'e + a'b'c'e' + bc + de, Z2 = a'c'e, Z3 = bc +de+c'd'e'+bd and Z4 = a'c'e +ce using a 5*8*4 PLA 2. The following messages have been coded in the even parity hamming code and transmitted through a noisy channel, decode the messages, assuring that atmost a single error has occurred in each code word (i) (ii) (iii) (iv) Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using ROM array 4. Design a combinational circuit using a ROM,that accepts a 3- bit number and generates an output binary number equal to the square of the given input number 5. Write notes on RAM, its operation and its types. 6. Draw the PLA structure for the following multiple o/p function using switching elements. i. F1 = AB + AC ii. F2 = BC + AC 7. Write short notes on: i. (i) Programmable logic devices. (08) ii. (ii) comparison between PROM, PLA, PAL. (08) 8. Design a BCD to gray code converter and implement using PLA.(OR) Design a BCD to excess-3 code converter and implement using PLA. 9. Implement the two following Boolean functions using 8X 2 PROM. F1= m(3,5,6,7) and F2= m(1,2,3,4). 10. A combinational circuit is defined by the functions 1. F 1 = Σm(3,5,7) 2. F 2 = Σm(4,5,7) Implement the circuit with a PLA having 3 inputs, 3 product terms and two outputs. 9

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7).

CS6201 UNIT I PART-A. Develop or build the following Boolean function with NAND gate F(x,y,z)=(1,2,3,5,7). VALLIAMMAI ENGINEERING COLLEGE SRM Nagar, Kattankulathur-603203 DEPARTMENT OF COMPUTER SCIENCE AND ENGINEERING Academic Year: 2015-16 BANK - EVEN SEMESTER UNIT I PART-A 1 Find the octal equivalent of hexadecimal