Lab2: Cache Memories. Dimitar Nikolov

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1 Lab2: Cache Memories Dimitar Nikolov

2 Goal Understand how cache memories work Learn how different cache-mappings impact CPU time Leran how different cache-sizes impact CPU time Lund University / Electrical and Information Technology / 1

3 Tools Tools used for this exercise: MipsIt.exe Used for program editing Mips.exe Used for simulation Lund University / Electrical and Information Technology / 2

4 Online test The online test is scheduled on Monday 11th November Access the test from the course web-page Example of an online test is provided Lund University / Electrical and Information Technology / 3

5 Overview Background Simulation Lund University / Electrical and Information Technology / 4

6 Programmers vs. CPU Programmers view: Very large continuous memory space CPU view: Registers Cache Memory Main Memory Hard drive Lund University / Electrical and Information Technology / 5

7 Locality of references Programs access a small proportion of their address space at any time Temporal locality Items accessed recently are likely to be accessed again soon e.g., instructions in a loop, induction variables Spatial locality Items near those accessed recently are likely to be accessed soon E.g., sequential instruction access, array data Lund University / Electrical and Information Technology / 6

8 Locality of references Memory hierarchy Store everything on disk Copy recently accessed (and nearby) items from disk to smaller DRAM memory Main memory Copy more recently accessed (and nearby) items from DRAM to smaller SRAM memory Cache memory attached to CPU Lund University / Electrical and Information Technology / 7

9 Memory Hierarchy Lund University / Electrical and Information Technology / 8

10 Memory Hierarchy Lund University / Electrical and Information Technology / 9

11 Memory access CPU fetches data and instructions from memory CPU issues a memory address to fetch the information The information (data or instruction) may be present in: Cache memory (low size) Main memory (medium size) Secondary memory (hard drive) (Laaarge size) Where to search??? How to search the information based on a given address??? Lund University / Electrical and Information Technology / 10

12 Cache memory vs. Main memory Cache memory Main Memory Cache line Memory block... Lund University / Electrical and Information Technology / 11

13 Cache memory vs. Main memory Cache memory Main Memory Cache line Memory block... Size of a cahce line in Bytes Few cache lines Address: Depends on mapping = Size of a memory block in Bytes Many memory blocks Address: Memory block + byte Lund University / Electrical and Information Technology / 12

14 Cache mapping Where in the cache memory a memory address resides Direct mapping A memory block maps into one cache line Fully associative mapping A memory block maps into ANY cache line Set-associative mapping (N-way associative) A memory block maps into N cache lines Lund University / Electrical and Information Technology / 13

15 Direct-mapped cache Compare the TAG with TAG of the cache line Address: TAG Cache Line Byte Memory block Cache memory TAG Main memory... Lund University / Electrical and Information Technology / 14

16 Fully associative cache TAG Cache Main... Compare TAG for each cache line Address: TAG Byte Lund University / Electrical and Information Technology / 15

17 Set Associative cache Address: TAG Set Byte TAG Compare TAG only for cache lines that belong to the same SET Cache Main... Number of cache lines in each set Lund University / Electrical and Information Technology / 16

18 Overview Background Simulation Lund University / Electrical and Information Technology / 17

19 Create New Project Lund University / Electrical and Information Technology / 18

20 Add a code source file Lund University / Electrical and Information Technology / 19

21 Compile & Build Lund University / Electrical and Information Technology / 20

22 Open MIPS Lund University / Electrical and Information Technology / 21

23 Upload the program Lund University / Electrical and Information Technology / 22

24 Configure the cache Lund University / Electrical and Information Technology / 23

25 Configure the I-cache (Instruction Cache) Size of the cache in words Size of the cache line in words associativity Replacement algorithm Lund University / Electrical and Information Technology / 24

26 Configure the D-cache (Data cache) Size of the cache in words Size of the cache line in words Associativity Replacement algorithm Write policy Lund University / Electrical and Information Technology / 25

27 Instruction cache (I-cache) Lund University / Electrical and Information Technology / 26

28 Data cache (D-cache) Lund University / Electrical and Information Technology / 27

29 Cache statistics Hit rate changes over time Lund University / Electrical and Information Technology / 28

30 Lund University / Electrical and Information Technology / 29

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