Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics

Size: px

Start display at page:

Download "Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics"

Silvia Chloe Henderson
5 years ago
Views:

1 Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 3 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and Technology cetinkayae@mst.edu 25 April 2018 rev Egemen K. Çetinkaya

2 Exam3 Logistics Overview Exam 3 will be held on 27 April 2018 It will be in room ECE101 & EMGT 201 You are responsible from all material covered chapter readings from book lecture notes in-class discussions Cheating is prohibited! read course policies as a reminder Closed notes, books, no calculator Bring pencil and eraser 2

3 Exam3 Logistics Style Exam duration will be 50 minutes Exam will include different types of questions short answer long answer Students are responsible all material covered emphasis will be on topics after exam 2 3

4 Exam1 Topics 4

5 Applications and History Binary logic is the basis for digital systems Early history goes to 1850s not much done till 1938 significant progress after World War II with invention of transistor last decade is head-spinning There are many application areas of digital systems very pervasive in our lives Analog signals are continuous signals Digital signals are discrete signals 5

6 Signals can be: analog: continuous digital: discrete Important terminology: bit, byte, nibble, LSB, MSB Number Systems Important number systems: decimal, binary, hex, octal Conversions will be needed throughout your careers: know by heart 6

7 Boolean Algebra Understand the important Boolean algebra properties commutativity distributivity associativity identity complementery null elements idempotent law involution law DeMorgan s law absorption law 7

8 Boolean Representations Three Boolean representations: circuits equations truth tables Important terminology variables/literals product term/sum term/sum-of-products/product-of-sums normal term/minterm/maxterm canonical sum (sum-of-minterms) canonical product (product-of-maxterms) 8

9 Karnaugh Maps Karnaugh maps used to simplify truth tables Group together adjacent cells containing ones 1s grouping is done for a group of: 2 0, 2 1, 2 2 1s Every one must be in at least one group Each group should be as large as possible Fewest number of groups possible Overlapping of 1s is allowed Zeros are not allowed Diagonal groupings are not allowed For DC conditions; assign a 0 or a 1 and then simplify 9

10 Electric Circuits There are two types of digital circuits combinatorial circuits: no memory sequential circuits: memory Ohm s law: V=IR Switches are basic components of digital circuits Switches have two states: on and off Transistors are basic electric circuit component CMOS have NMOS and PMOS transistors together NMOS transistors conduct when gate is on PMOS transistors conduct when gate is off 10

11 Basic Logic Gates Logic gates building blocks of complex logic circuits Gate functions can be represented via: symbols truth tables equations timing diagrams transistor circuits Important three basic gates are: AND OR NOT 11

12 Logic Gates: NAND, NOR, XOR, XNOR Basic gates are: AND OR NOT More gates: NAND NOR XOR XNOR Universal gates: NAND & NOR 12

13 Combinatorial Logic Circuit Design and Analysis Combinatorial logic circuit analysis truth table might be hard to construct for many inputs equations can be simplified via Boolean algebra circuits Combinatorial logic circuit design/synthesis capture behavior create equations simplify implement as a gate-based circuit 13

14 Real gates have delay Wires also have delay Practical Considerations Designer must consider critical path delay Attention to active-lows are required Simulations help analyze digital logic 14

15 PLDs Computing resources are: CPU, memory, BW, power IC types are: off-the-shelf vs. manufactured off-the-shelf ICs: logic IC, PLD, FPGA manufactured IC: full-custom vs. semi-custom Simple PLDs: PLA: Programmable Logic Array: OR-AND or AND-OR planes PAL: Programmable Array Logic 15

16 Exam2 Topics 16

17 Adders Adders add two N-bit numbers Half-adder: adds two bits, generates sum bit and carry-out bit Full-adder: adds three bits, generates sum bit and carry-out bit Types: carry-ripple: carry ripples through adders carry-select: for faster add operation, uses multiplexers carry-lookahead: for faster add operation Incrementer increments by 1 using half-adder 17

18 Half-subtractor: Subtractors subtracts two bits: minuend and subtrahend generates two output bits: difference and borrow Full-subtractor: subtracts three bits: minuend, subtrahend, and borrow in generates two output bits: difference and borrow out Negative binary numbers can be represented via: 1 s complements: flip all bits including the sign bit 2 s complements: 1s complement + 1 Overflow can be determined by: c n 1 c n 18

19 Comparators N-bit equality comparator (aka identity comparator) inputs: two N-bit inputs output: control bit eq=1 if two inputs are equal N-bit magnitude comparator inputs: two N-bit inputs output: three control bits eq, gt, lt staged design each bit is compared from higher order to lower order 19

20 Multipliers/Dividers Many multipliers design exists Division is a slow and expensive operation Need to preserve the sign for signed numbers when doing multiplication/division via shifting ALUs performs Boolean and arithmetic functions 20

21 Latches There are two types of digital circuits combinatorial circuits: no memory sequential circuits: memory Sequential circuit elements: latches, flip-flops, etc. Latches store a bit Latch types: basic SR latch level-sensitive SR latch level-sensitive D latch SR 11 is an issue for latches 21

22 Flip-flops store one bit Flip-Flops Latches are level-sensitive Flip-flops are edge-triggered Signal travels one cycle per flip-flop D-flip-flops are most commonly used Flip-flop types: SR, JK, D, T Two types of flip-flops: edge-triggered: active edge of the clock impacts the state master-slave: with two gated latches 22

23 Registers Registers store multiple bits a flip-flop stores only one bit Several types of registers exist serial/parallel I/O combinations directional (right or left)/bidirectional Important operations using registers: shift: right: divide operation left: multiply operation rotation does not drop LSB or MSB, substitutes 23

24 Exam3 Topics 24

25 Multiplexers Multiplexers/Demultiplexers multiplex n data inputs onto a single data output under control of the select inputs Demultiplexers places single data input onto multiple data outputs 25

26 Encoders/Decoders Encoders: makes information compact Decoders: decode encoded information convert data from some binary form to another binary form Combinations: active-low/active-high enable/outputs Larger decoders can be built from smaller decoders by utilizing enable input An AND n-to-2 n -line decoder is minterm generator A NAND n-to-2 n -line decoder is maxterm generator In addition to n-to-2 n -line decoders: function-specific decoders: e.g. BCD 4-to-10-line decoders 26

27 Counters/Timers Counters are sequential components that increments or decrements Ripple counters are known as asynchronous counters causes problems related to propagation delay Ring counter: only 1 flip-flop is in 1 state Binary patterns can be counted too Up/down counter can count both directions Timers pulse output at user-specified timer interval 27

28 Finite State Machines FSM is a mathematical formalism method FSMs are useful in designing sequential logic circuits Representations: state diagrams state transition tables timing diagrams Attention to non-exclusive and incomplete transitions! Moore: Outputs are determined by the current state Mealy: Outputs are determined by: current state and current input 28

29 Controllers Controllers are sequential logic that implements FSM Mathematical formalism that help digital design: FSM for sequential logic circuits Boolean algebra for combinatorial logic circuits Controller design steps: capture the FSM setup architecture encode states create the truth table implement the combinatorial circuit Reverse engineering is converting circuit to FSM There are practical aspects: delay, initial states 29

30 State reduction: Sequential Logic Optimizations reduces number of states without changing the behavior fewer states potentially reduces: register and circuit reducing states does not guarantee reduction in reg. & circt. State encoding: assignment of unique bits to each state may or may not reduce size of circuit and/or state register 30

31 Questions? 31

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 2 Logistics

Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 2 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and