MUX AND FLIPFLOPS/LATCHES

Transcription

1 MUX AN FLIPFLOPS/LATCHES BY: SURESH BALPANE

2 Multiplexers 2:1 multiplexer chooses between two inputs S 1 0 Y 0 X X X X S and Slide 2

3 Gate-Level Mux esign Y S S 1 0 (too many transistors) How many transistors are needed? 20 1 S 0 Y 1 S and Slide 3

4 Transmission Gate Mux Nonrestoring mux uses two transmission gates mux uses two transmission gates Only 4 transistors 0 S S Y 1 and Slide 4

5 4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Two levels of 2:1 muxes Or four tristates S0 S1S0 S1S0 S1S0 S1S0 S Y 1 2 Y 3 and Slide 5 3

6 Latch When = 1, latch is transparent flows through to like a buffer When = 0, the latch is opaque holds its old value independent of a.k.a. transparent latch or level-sensitive latch and Slide 6

7 Latch esign Multiplexer chooses or old 1 and Slide 7

8 Latch Operation = 1 = and Slide 8

9 Flip-flop When rises, is copied to At all other times, holds its value a.k.a. positive edge-triggered flip-flop, master- slave Compiled flip-flop by: Suresh S. Balpande and Slide 9

10 Flip-flop esign Built from master and slave latches Latch M M and Slide 10

11 Flip-flop Operation M = 0 M Compiled by: Suresh S. Balpande = and Slide 11

12 CMOS SR Latch: NOR Gate Version The NOR-based SR Latch contains the basic memory cell (back-to-back inverters) built into two NOR gates to allow setting the state of the latch. If Set goes high, M1 is turned on forcing low which, in turn, pulls high S=1 = 1 If Reset goes high, M4 is turned on, is pulled low, and is then pulled high Compiled by: Suresh S. R=1 Balpande = 1 If both Set and Reset are low, both M1 and M4 are off, and the latch holds its existing state indefinitely If both Set and Reset go high, both and are pulled low, giving an indefinite state. Therefore, R=S=1 is not allowed The gate-level symbol and truth table for the NOR-based SR latch are given at left To estimate Set time, add time to discharge + time to charge (pessimistic result) R. W. Knepper SC571, page 5-30

13 CMOS SR Latch: NAN Gate Version A CMOS SR latch built with two 2-input NAN gates is shown at left The basic memory cell comprised of two back-to-back CMOS inverters is seen The circuit responds to active low S and R inputs If S goes to 0 (while R = 1), goes high, pulling low and the latch enters Set state S=0 = 1 (if R = 1) If R goes to 0 (while S = 1), goes high, pulling low and the latch is Reset R=0 = 1 (if S = 1) Hold state requires both S and R to be high S = R = 0 if not allowed, as it would result in an indeterminate state R. W. Knepper SC571, page 5-32

14 Clocked CMOS JK Latch: NAN Version The SR latch has a problem in that when both S and R are high, its state becomes indeterminate The JK latch shown at left eliminates this problem by using feedback from output to input, such all states in the truth table are allowable If J = K = 0, the latch will hold its present state If J = 1 and K = 0, the latch will set on the next positive-going clock edge, i.e. = 1, = 0 If J = 0 and K = 1, the latch will reset on the next positive-going clock edge, i.e. = 1 and = 0 If J = K = 1, the latch will toggle on the next positive-going clock edge Note that in order to prevent the JK Latch above from oscillating continuously during the clock active time, the clock width must be kept smaller than the switching delay time of the latch. Otherwise, several oscillations may occur before the clock goes low again. In practice this may be difficult to achieve. R. W. Knepper SC571, page 5-35

15 CMOS -Latch Implementation A -latch is implemented, at the gate level, by simply utilizing a NOR-based S-R latch, connecting to input S, and connecting to input R with an inverter. When goes high, is transmitted to output (and to ) When goes low, the latch retains its previous state The latch is normally implemented with transmission gate (TG) switches, as shown at the left The input TG is activated with while the latch feedback loop TG is activated with Input is accepted when is high When goes low, the input is open-circuited and the latch is set with the prior data R. W. Knepper SC571, page 5-37

16 Alternate CMOS -Latch Implementation An alternate (preferred) version of the CMOS -Latch (shown at left) is implemented with two tri-state inverters and a normal CMOS inverter. Functionally it is similar to the previous chart -Latch When is high, the first tri-state inverter sends the inverted input through to the second inverter, while the second tri-state is in its high Z state. Output is following input When is low, the first tri-state goes into its high Z state, while the second tri-state inverter closes the feedback loop, holding the data and in the latch. R. W. Knepper SC571, page 5-39