Lecture 1: Intro to CMOS Circuits

Transcription

1 Introduction to CMOS VLSI esign Lecture : Intro to CMOS Circuits avid Harris Steven Levitan Fall 28 Harvey Mudd College Spring 24

2 Outline A Brief History CMOS Gate esign Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick iagrams Slide 2 2

3 A Brief History 958: First integrated circuit Flip-flop using two transistors Built by Jack Kilby at Texas Instruments 23 Intel Pentium 4 μprocessor (55 million transistors) 52 Mbit RAM (>.5 billion transistors) 53% compound annual growth rate over 45 years No other technology has grown so fast so long riven by miniaturization of transistors Smaller is cheaper, faster, lower in power! Revolutionary effects on society Slide 3 3

4 Annual Sales 8 transistors manufactured in 23 million for every human on the planet Global Semiconductor Billings (Billions of US$) ear Slide 4 4

5 Invention of the Transistor Vacuum tubes ruled in first half of 2 th century Large, expensive, power-hungry, unreliable 947: first point contact transistor John Bardeen and Walter Brattain at Bell Labs Read Crystal Fire by Riordan, Hoddeson Slide 5 5

6 Transistor Types Bipolar transistors npn or pnp silicon structure Small current into very thin base layer controls large currents between emitter and collector Base currents limit integration density Metal Oxide Semiconductor Field Effect Transistors nmos and pmos MOSFETS Voltage applied to insulated gate controls current between source and drain Low power allows very high integration Slide 6 6

7 MOS Integrated Circuits 97 s processes usually had only nmos transistors Inexpensive, but consume power while idle Intel 256-bit SRAM Intel 44 4-bit μproc 98s-present: CMOS processes for low idle power Slide 7 7

8 Moore s Law 965: Gordon Moore plotted transistor on each chip Fit straight line on semilog scale Transistor counts have doubled every 26 months Transistors,,,,,,,,,, 8286 Intel386 Intel486 Pentium 4 Pentium III Pentium II Pentium Pro Pentium Integration Levels SSI: gates MSI: gates 886,, LSI:, gates ear VLSI: > k gates Slide 8 8

9 Corollaries Many other factors grow exponentially Ex: clock frequency, processor performance,, 44 Clock Speed (MHz) Intel386 Intel486 Pentium Pentium Pro/II/III Pentium ear Slide 9 9

10 MOS transistors Types and Symbols G G S NMOS Enhancement NMOS S epletion PMOS G S Enhancement G S B NMOS with Bulk Contact o not forget: These are all 4 terminal devices EE4 igital ECE Integrated 92 Circuits Circuits 26, 2nd Steven Levitan, Introduction University of Pittsburgh Prentice Manufacturing Hall 995

11 The Basic Idea Voltage on the Gate controls the current through the source/drain path N-Channel - N-Switches are ON when the Gate is HIGH and OFF when the Gate is LOW P-Channel - P-Switches are OFF when the Gate is HIGH and ON when the Gate is LOW (ON == Circuit between Source and rain) igital EE4 ECE Integrated 92 Circuits 26, 2nd Steven Levitan, University of Pittsburgh Manufacturing

12 Transistors as Switches N Switch G S Passes good zeros P Switch G S Passes good ones 2 igital EE4 ECE Integrated 92 Circuits 26, 2nd Steven Levitan, University of Pittsburgh Manufacturing 2

13 Four Views Logic Transistor Layout Physical 3 igital EE4 ECE Integrated 92 Circuits 26, 2nd Steven Levitan, University of Pittsburgh Manufacturing 3

14 CMOS N Well Process P-Channel in an N well N-Channel in a P substrate 4 igital EE4 Integrated Circuits 2nd Manufacturing 4

15 3 Perspective Polysilicon Aluminum 5 igital EE4 Integrated Circuits 2nd Manufacturing 5

16 A Modern ual Well CMOS Process gate-oxide TiSi 2 AlCu Tungsten SiO 2 n+ p-well p-epi poly n-well p+ SiO 2 p+ ual-well Trench-Isolated CMOS Process epi epitaxial = grown with matching crystal structure TiSi silicide = low resistance coating (real trenches are much deeper) 6 igital EE4 Integrated Circuits 2nd Manufacturing 6

17 Complementary CMOS Complementary CMOS logic gates nmos pull-down network pmos pull-up network a.k.a. static CMOS inputs pmos pull-up network output Pull-down OFF Pull-up OFF Z (float) Pull-up ON nmos pull-down network Pull-down ON X (crowbar) Slide 7 7

18 Series and Parallel nmos: = ON pmos: = ON g g2 a b a b a b a b a b Series: both must be ON Parallel: either can be ON (a) g g2 a b OFF OFF OFF ON a a a a b b b b (b) ON OFF OFF OFF a a a a a g g2 b b b b b (c) OFF ON ON ON a a a a a g g2 b b b b b (d) ON ON ON OFF Slide 8 8

19 Conduction Complement Complementary CMOS gates always produce or Ex: NAN gate Series nmos: = when both inputs are Thus = when either input is Requires parallel pmos Rule of Conduction Complements A B Pull-up network is complement of pull-down Parallel -> series, series -> parallel Slide 9 9

20 CMOS Gate esign Activity: Sketch a 4-input CMOS NAN gate Slide 2 2

21 CMOS Gate esign Activity: Sketch a 4-input CMOS NOR gate A B C Slide 2 2

22 Compound Gates Compound gates can do any inverting function Ex: = A B+ C (AN-AN-OR-INVERT, AOI22) A C A C B B (a) (b) (c) A B C (d) C A B C A A B B C A B C (f) (e) Slide 22 22

23 = ( A+ B+ C) Example: O3AI Slide 23 23

24 = ( A+ B+ C) Example: O3AI A A B C B C Slide 24 24

25 Signal Strength Strength of signal How close it approximates ideal voltage source V and GN rails are strongest and nmos pass strong But degraded or weak pmos pass strong But degraded or weak Thus nmos are best for pull-down network Slide 25 25

26 Pass Transistors Transistors can be used as switches g s d g s d Slide 26 26

27 Pass Transistors Transistors can be used as switches s g d s s g = d g = d Input g = Output strong g = degraded s g d s s g = d g = d Input g = Output degraded g = strong Slide 27 27

28 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both and well Slide 28 28

29 Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both and well a g gb b g =, gb = a b g =, gb = a b Input Output g =, gb = strong g =, gb = strong a g b a g b a g b gb gb gb Slide 29 29

30 Tristates Tristate buffer produces Z when not enabled EN A A EN A EN EN Slide 3 3

31 Tristates Tristate buffer produces Z when not enabled EN A Z Z A EN A EN EN Slide 3 3

32 Nonrestoring Tristate Transmission gate acts as tristate buffer Only two transistors But nonrestoring Noise on A is passed on to EN A EN Slide 32 32

33 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output A EN EN Slide 33 33

34 Tristate Inverter Tristate inverter produces restored output Violates conduction complement rule Because we want a Z output A A A EN EN EN = = 'Z' EN = = A Slide 34 34

35 Multiplexers 2: multiplexer chooses between two inputs S S X X X X Slide 35 35

36 Multiplexers 2: multiplexer chooses between two inputs S S X X X X Slide 36 36

37 Gate-Level Mux esign = S + S (too many transistors) How many transistors are needed? Slide 37 37

38 Gate-Level Mux esign = S + S (too many transistors) How many transistors are needed? 2 S S Slide 38 38

39 Transmission Gate Mux Nonrestoring mux uses two transmission gates Slide 39 39

40 Transmission Gate Mux Nonrestoring mux uses two transmission gates Only 4 transistors S S S Slide 4 4

41 Inverting Mux Inverting multiplexer Use compound AOI22 Or pair of tristate inverters Essentially the same thing Noninverting multiplexer adds an inverter S S S S S S S S S Slide 4 4

42 4: Multiplexer 4: mux chooses one of 4 inputs using two selects Slide 42 42

43 4: Multiplexer 4: mux chooses one of 4 inputs using two selects Two levels of 2: muxes Or four tristates SS SS SS SS S S Slide 43 43

44 Latch When CLK =, latch is transparent flows through to Q like a buffer When CLK =, the latch is opaque Q holds its old value independent of a.k.a. transparent latch or level-sensitive latch CLK CLK Latch Q Q Slide 44 44

45 Latch esign Multiplexer chooses or old Q CLK Q Q CLK CLK CLK Q Q CLK Slide 45 45

46 Latch Operation Q Q Q Q CLK = CLK = CLK Q Slide 46 46

47 Flip-flop When CLK rises, is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop CLK CLK Flop Q Q Slide 47 47

48 Flip-flop esign Built from master and slave latches CLK CLK QM CLK Q CLK CLK CLK CLK CLK Latch QM Latch Q CLK CLK Slide 48 48

49 Flip-flop Operation QM Q CLK = QM Q CLK = CLK Q Slide 49 49

50 Race Condition Back-to-back flops can malfunction from clock skew Second flip-flop fires late Sees first flip-flop change and captures its result Called hold-time failure or race condition CLK CLK CLK2 CLK2 Flop Q Flop Q2 Q Q2 Slide 5 5

51 Nonoverlapping Clocks Nonoverlapping clocks can prevent races As long as nonoverlap exceeds clock skew We will use them in this class for safe design Industry manages skew more carefully instead φ 2 φ QM Q φ 2 φ 2 φ φ φ 2 φ φ φ 2 Slide 5 5