ECE 555 DESIGN PROJECT Introduction and Phase 1

Transcription

1 March 15, 1998 ECE 555 DESIGN PROJECT Introduction and Phase 1 Charles R. Kime Dept. of Electrical and Computer Engineering University of Wisconsin Madison Phase I Due Wednesday, March 24; One Week Grace Period 80 points The ECE 555 project for this semester is the design of a high-speed comparator. We assume that your team is designing the comparator for inclusion in one or more pipelines that are parts of a larger chip. The design is semi-full custom, using a hierarchical design style that resembles the standard cell approach. A major focus of the design will be meeting specifications. The project is unusual in the sense that you will complete the assignment by submitting the project in phases. Each phase has as its goal instruction in one or more aspects of the course material. In addition, submission of the project in phases insures that you do not fall behind on the project. The remainder of this handout gives a specification for the comparator and instructions for Phase I which is 1) the design and validation of the comparator at the logic level and 2) the estimation of parameters for timing calculation. SPECIFICATIONS The comparator specification has two parts, the functional specification and the static and dynamic circuit parameters. Functional Specification The comparator is to be a standard cell that can be incorporated into one or more pipelines in a chip design. It accepts two 16-bit unsigned operands A(15:0) and B(15:0) and has two outputs: EN and GL. EN = 1 if A = B and EN = 0 if A B. GL = 1 if A > B and GL = 0 if A < B. If A = B, GL = d, i. e., GL is a don t care. 1

2 SPECIFICATIONS The outputs EN and GL are to be stored in flip-flops which provide the output pipeline platform for the comparator. The inputs to the comparator are assumed to be driven by similar flip-flops. Figure 1 provides a block diagram for the comparator and its environment. Figure 1. Block Diagram of Interval Counter 16 DFFs 16 DFFs A(15:0) B(15:0) COMPARATOR LOGIC D Q D Q C C CLK EN GL Static and Dynamic Specifications The electronic circuit specifications are given for the design as well as the specification for the typical frequency of operation for the comparator. The following specifications apply to all logic gates including inverters and flip-flops. Process: ~kime/[public_html/project/scn06hp.param4+ HSPICE model: ~kime/public_html/spice_models/scn06hp.l13 V DD = 3.3 V V OH 3.2V V OL 0.1 V V th = 1.65 ± 0.55 V NM H and NM L 0.7 V λ = 0.3 µ, λ/2 = 0.15 µ L drawn,min = 0.6 µ and W drawn,min = 0.9 µ L n = 0.14 µ and W n = 0.50 µ (for manual calculations) L p = 0.21 µ and W p = 0.53 µ (for manual calculations) C int, internal,max = 30 ff (represents a long local interconnect) 2 ECE 555 DESIGN PROJECT Introduction and Phase 1

3 C output,max = 500 ff (represents a moderately long global interconnect including FO loading) f minimum = 100 MHz f typical = 120 MHz P total (evaluated at 120MHz) = minimum A (bounding box area) = minimum (bounding box -- a box just large enough to contain the entire cell) All parameters given are typical except for f minimum. You are to do a typical design. f typical is set at 1.2 times f minimum to insure that the guaranteed frequency specification f minimum is met in spite of processing variations and the commercial range of environmental variations. Note that this is not standard industrial practice! Your team is to use Mentor Graphic Design Architect and Quicksim to design and validate the comparator at the logic gate/flip-flop level. There are other constraints on your design as follows: 1) You are to use only components from Mentor Graphics genlib. 2) The only type of flip-flop to be used is a D flip-flop with asynchronous reset. The only gates permitted are NAND gates (including inverters). The gates may have no more than four (4) inputs. 3) The primary design objective will be speed. As a consequence, you cannot use a design based on 16 identical comparator cells with carry-like signals between them. Instead, you should use structures such as 2-level carry lookahead for implementing EN and GL. See for example, pages 134 through 137 of Logic and Computer Design Fundamentals by M. M. Mano and C. R. Kime. Also, you should not use subtraction followed by comparison to zero and use of sign bits to generate the outputs. Such an approach will involve excessive logic. You will need to make considerable effort to keep N crit, the number of gates along the longest path from a comparator input to a flip-flop input as small as reasonably possible and also control the value of the gate fanout. Determination of Propagation Delay Specifications Here, instructions are given to determine 1) the longest gate path N crit through the comparator, 2) the value of t P for the gates to be used in the comparator and 3) the worst case fanout FO. N crit is determined by looking for the longest path from an input to an output (flip-flop input in this case) in a design in terms of the number of gates on the path. The average propagation delay t P for your gates assuming that all gate delays are equal can be determined as follows. Recall that an inverter is just another form of gate and that ECE 555 DESIGN PROJECT Introduction and Phase 1 3

4 the gates are restricted to inverters and NANDs with four or fewer inputs. This methodology for determining t p may not be typical of that used in a real design environment. Given a desired clock frequency f, the clock period T is bounded above by 1/f, i.e., 1/f T. Based on an assumption that all gate delays are equal, the clock period for a circuit using edge-triggered flip-flops is bounded below by: T t P,FF + N crit t P + t S,FF where t P,FF is the flip-flop propagation delay and t S,FF is the flip-flop setup time. Use this equation to find the value of t P for the comparator assuming that t P,FF = 3 t P and t S,FF = 2 t P. This gives a new equation: T (N crit + 5) t P N crit is the largest number of gates in a path between a flip-flop output and a flip-flop input assuming temporarily that all inputs are driven directly by flip-flops and that all outputs directly drive flip-flops. (Considering the importance of N crit here, you might want to re-examine your logic design to see if N crit can be reduced.) This project assumes a constraint for the propagation delays of the form: t P (t PHL + t PLH )/2 Assume that t PHL and t PLH are roughly equal to find the delay specifications to be used to design the basic inverter. FO equals the maximum fanout from a gate output anywhere in your comparator design. A single gate input may count as more than 1 in FO. As a consequence, FO will be determined as the sum of the inverter equivalents (IEs) for the gates driven. The inverter equivalents for this CMOS design are: Gate Type Inverter Equivalents Inverter 1 NAND (2 inputs) (2 + 1/K D )/(1 + 1/K D ) NAND (3 or 4 inputs) (4 + 1/K D )/(1 + 1/K D ) Assume that K R = 1, K D for the inverter can be approximated as µ p /µ n. The mobility values are in the sixth row of the left column of the tn and tp models in the L13 model file. Activities a) Form a two-person design team and set up a UNIX group (See CAE handout on sharing files.) for the team. b) As a team, do the comparator design, enter it using Mentor Graphics DA and functionally simulate it using Quicksim II to validate your design. Note that your simulation must be thorough to insure that the design is correct. c) Find N crit for your design. d) Find the constraints for your design on t PHL and t PLH. e) Find the worst case value of FO for your design in terms of inverter equivalents. 4 ECE 555 DESIGN PROJECT Introduction and Phase 1

5 Submissions Phase I is due on Wednesday, March 24 with a one-week grace period. Phase I is worth 80 points. Only one project report per phase is to be submitted by each team. Duties are to be shared equitably among team members; on the final report, you will be asked to summarize in detail the contributions of each team member, so keep careful records. Each team member is to review the work of the other for correctness and design quality to insure good results. This review has two goals: 1) to improve the quality of the project and 2) to make sure that both team members are familiar with all aspects of the material the project covers. Provide originals of all logic diagrams and simulation outputs. Annotate these outputs so that it is very clear what they are, how the comparator works and that the comparator works correctly according to functional specifications. Provide the values for N crit, t p, and FO and give evidence to show how you obtained these values from your design, i. e., show your work! Keep your design available for future use; you will need it for subsequent phases. ECE 555 DESIGN PROJECT Introduction and Phase 1 5