CprE 281: Digital Logic
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1 CprE 28: Digital Logic Instructor: Alexander Stoytchev
2 Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
3 Administrative Stuff The second midterm is this Friday. Homework 8 is due today. Homework 9 is out. It is due on Mon Nov 6. No HW due next Monday
4 Midterm Exam #2 Administrative Stuff When: Friday October 4pm. Where: This classroom What: Chapters, 2, 3, 4 and The exam will be open book and open notes (you can bring up to 3 pages of handwritten notes).
5 Registers
6 Register (Definition) An n-bit structure consisting of flip-flops
7 Parallel-Access Register
8 -Bit Parallel-Access Register Load In D Out
9 -Bit Parallel-Access Register Load In D Out The 2-to- multiplexer is used to select whether to load a new value into the D flip-flop or to retain the old value. The output of this circuit is the output of the flip-flop.
10 -Bit Parallel-Access Register Load In D Out If Load =, then retain the old value. If Load =, then load the new value from In.
11 2-Bit Parallel-Access Register Out_ Out_ Load D D In_ In_
12 2-Bit Parallel-Access Register Parallel Output Out_ Out_ Load D D In_ In_ Parallel Input
13 3-Bit Parallel-Access Register Out_2 Out_ Out_ Load D D D In_2 In_ In_ Notice that all flip-flops are on the same clock cycle.
14 3-Bit Parallel-Access Register Parallel Output Out_2 Out_ Out_ Load D D D In_2 In_ In_ Parallel Input
15 4-Bit Parallel-Access Register Out_3 Out_2 Out_ Out_ Load D D D D In_3 In_2 In_ In_
16 4-Bit Parallel-Access Register Parallel Output Out_3 Out_2 Out_ Out_ Load D D D D In_3 In_2 In_ In_ Parallel Input
17 Shift Register
18 A simple shift register In D D D D Out [ Figure 5.7a from the textbook ]
19 A simple shift register In D D D D Out Positive-edge-triggered D Flip-Flop
20 A simple shift register In D D D D Out Master Slave D D m D s Clk Clk
21 A simple shift register In D D D D Out D Flip-Flop Master Slave D D m D s Clk Clk Gated D-Latch Gated D-Latch
22 A simple shift register In D D D D Out
23 A simple shift register In D D D D Out In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
24 A simple shift register In D D D D Out In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
25 A simple shift register In D D D D Out In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
26 A simple shift register In D D D D Out In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
27 A simple shift register In D D D D Out In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
28 A simple shift register In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
29 A simple shift register In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
30 A simple shift register In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
31 A simple shift register In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
32 A simple shift register In Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk Master D Clk Slave D Clk
33 A simple shift register In D D D D Out (a) Circuit t In = Out t t 2 t 3 t 4 t 5 t 6 t 7 (b) A sample sequence [ Figure 5.7 from the textbook ]
34 Parallel-Access Shift Register
35 Parallel-access shift register [ Figure 5.8 from the textbook ]
36 Parallel-access shift register When Load=, this behaves like a shift register. [ Figure 5.8 from the textbook ]
37 Parallel-access shift register When Load=, this behaves like a parallel-access register. [ Figure 5.8 from the textbook ]
38 Shift Register With Parallel Load and Enable
39 A shift register with parallel load and enable control inputs [ Figure 5.59 from the textbook ]
40 A shift register with parallel load and enable control inputs The directions of the input and output lines are switched relative to the previous slides. [ Figure 5.59 from the textbook ]
41 A shift register with parallel load and enable control inputs Parallel Input Parallel Output [ Figure 5.59 from the textbook ]
42 A shift register with parallel load and enable control inputs [ Figure 5.59 from the textbook ]
43 A shift register with parallel load and enable control inputs [ Figure 5.59 from the textbook ]
44 A shift register with parallel load and enable control inputs [ Figure 5.59 from the textbook ]
45 A shift register with parallel load and enable control inputs [ Figure 5.59 from the textbook ]
46 Multiplexer Tricks (select one of two 2-bit numbers)
47 Select Either A=A A or B=B B s A B F A B F
48 Select Either A=A A or B=B B s A B F = A A B F = A
49 Select Either A=A A or B=B B s A B F = B A B F = B
50 Multiplexer Tricks (select one of four 2-bit numbers)
51 Select A=A A or B=B B or C=C C or D=D D s s A B C F D A B C F D
52 Select A=A A or B=B B or C=C C or D=D D s s A B C F D = A A B C F D = A
53 Select A=A A or B=B B or C=C C or D=D D s s A B C F D = B A B C F D = B
54 Select A=A A or B=B B or C=C C or D=D D s s A B C F D = C A B C F D = C
55 Select A=A A or B=B B or C=C C or D=D D s s A B C F D = D A B C F D = D
56 Register File
57 Complete the following circuit diagram to implement a register file with four 2-bit registers, one write port, one read port, and one write enable line.
58
59 Register Register Register 2 Register 3
60 Register A Register B Register C Register D
61 A A Register A B B Register B C C Register C D D Register D
62 In In A A Register A B B Register B C C Register C D D Register D
63 In In A A Register A B B Register B C C Register C D D Register D Write_address_ Write_address_ Write_enable
64 In In A A Register A B B Register B C C Register C D D Register D Write_address_ Write_address_ Write_enable
65 In In A A Register A B B Register B C C Register C D D Register D Write_address_ Write_address_ Write_enable Out Out Read_address_ Read_address_
66 In In A A Register A B B Register B C C Register C D D Register D Write_address_ Write_address_ Write_enable Out Out Read_address_ Read_address_
67 In In A A B B C C D D Write_address_ Write_address_ Write_enable Out Out Read_address_ Read_address_
68 Another Register File
69 Register File Register file is a unit containing r registers r can be 4, 8, 6, 32, etc. Each register has n bits n can be 4, 8, 6, 32, etc. n defines the data path width Output ports (DATA and DATA2) are used for reading the register file Any register can be read from any of the ports Each port needs a log 2 r bits to specify the read address (RA and RA2) Input port (LD_DATA) is used for writing data to the register file Write address is also specified by log 2 r bits (WA) Writing is enabled by a -bit signal (WR) RA LD_DATA WR Reg File RA2 WA DATA DATA2
70 Register File: Exercise Suppose that a register file contains 32 registers width of data path is 6 bits (i.e., each register has 6 bits) How many bits are there for each of the signals? RA 5 RA2 5 DATA 6 DATA2 6 WA 5 LD_DATA 6 WR LD_DATA RA RA2 Reg File WR WA DATA DATA2
71 Register file design We will design an eight-register file with 4-bit wide registers A single 4-bit register and its abstraction are shown below LD D3 D2 D D D P 3 D P 2 D P D P LD D3 D2 D D 3 2 We have to use eight such registers to make an eight register file LD D3 D2 D D LD D3 D2 D D LD D3 D2 D D Clk 3 2 Clk 3 2 Clk 3 2 How many bits are required to specify a register address?
72 Reading Circuit A 3-bit register address, RA, specifies which register is to be read For each output port, we need one 8-to- 4-bit multiplier Register Address LD7 D3 D2 D D LD D3 D2 D D LD D3 D2 D D Clk 3 2 Clk 3 2 Clk RA 8-to- 4-bit multiplex DATA to- 4-bit multiplex RA2 DATA2
73 Adding write control to register file To write to any register, we need the register's address (WA) and a write register signal (WR) A 3-bit write address is decoded if write register signal is present One of the eight registers gets a LD signal from the decoder LD_DATA 3 to 8 D e c o d e r WA WR LD7 D3 D2 D D LD7 3 2 Clk LD2 LD LD LD D3 D2 D D Clk 3 2 LD D3 D2 D D RA 8-to- 4-bit multiplex 8-to- 4-bit multiplex RA2 DATA DATA2 Clk
74 Register File (More Examples)
75 Register File [
76 [
77 [
78 [
79 Counters
80 T Flip-Flop (circuit and graphical symbol) [ Figure 5.5a,c from the textbook ]
81 The output of the T Flip-Flop divides the frequency of the clock by 2
82 The output of the T Flip-Flop divides the frequency of the clock by 2
83 A three-bit down-counter [ Figure 5.2 from the textbook ]
84 A three-bit down-counter The first flip-flop changes on the positive edge of the clock [ Figure 5.2 from the textbook ]
85 A three-bit down-counter The first flip-flop changes on the positive edge of the clock The second flip-flop changes on the positive edge of [ Figure 5.2 from the textbook ]
86 A three-bit down-counter The first flip-flop changes on the positive edge of the clock The second flip-flop changes on the positive edge of The third flip-flop changes on the positive edge of [ Figure 5.2 from the textbook ]
87 A three-bit down-counter T T T 2 (a) Circuit 2 Count (b) Timing diagram [ Figure 5.2 from the textbook ]
88 A three-bit down-counter T T T 2 (a) Circuit least significant most significant 2 Count (b) Timing diagram
89 A three-bit down-counter T T T 2 (a) Circuit toggles on the positive clock edge 2 Count (b) Timing diagram
90 A three-bit down-counter T T T 2 (a) Circuit toggles on the positive edge of 2 Count (b) Timing diagram
91 A three-bit down-counter T T T 2 (a) Circuit 2 2 toggles on the positive edge of Count (b) Timing diagram
92 A three-bit down-counter T T T 2 (a) Circuit The propagation delays get longer 2 Count (b) Timing diagram
93 A three-bit up-counter [ Figure 5.9 from the textbook ]
94 A three-bit up-counter The first flip-flop changes on the positive edge of the clock [ Figure 5.9 from the textbook ]
95 A three-bit up-counter The first flip-flop changes on the positive edge of the clock The second flip-flop changes on the positive edge of [ Figure 5.9 from the textbook ]
96 A three-bit up-counter The first flip-flop changes on the positive edge of the clock The second flip-flop changes on the positive edge of The third flip-flop changes on the positive edge of [ Figure 5.9 from the textbook ]
97 A three-bit up-counter T T T 2 (a) Circuit 2 Count (b) Timing diagram [ Figure 5.9 from the textbook ]
98 A three-bit up-counter T T T 2 (a) Circuit least significant most significant 2 Count (b) Timing diagram [ Figure 5.9 from the textbook ]
99 A three-bit up-counter T T T 2 (a) Circuit The count is formed by the s 2 (b) Timing diagram [ Figure 5.9 from the textbook ]
100 A three-bit up-counter T T T 2 (a) Circuit The toggling is done by the s 2 (b) Timing diagram
101 A three-bit up-counter T T T 2 (a) Circuit toggles on the positive clock edge 2 (b) Timing diagram
102 A three-bit up-counter T T T 2 (a) Circuit toggles on the positive Edge of 2 (b) Timing diagram
103 A three-bit up-counter T T T 2 (a) Circuit 2 2 toggles on the positive edge of (b) Timing diagram
104 A three-bit up-counter T T T 2 (a) Circuit The propagation delays get longer 2 (b) Timing diagram
105 A three-bit up-counter T T T 2 (a) Circuit The propagation delays get longer 2 Count (b) Timing diagram [ Figure 5.9 from the textbook ]
106 Synchronous Counters
107 A four-bit synchronous up-counter [ Figure 5.2 from the textbook ]
108 A four-bit synchronous up-counter The propagation delay through all AND gates combined must not exceed the clock period minus the setup time for the flip-flops [ Figure 5.2 from the textbook ]
109 A four-bit synchronous up-counter T T T 2 T 3 (a) Circuit 2 3 Count (b) Timing diagram [ Figure 5.2 from the textbook ]
110 Derivation of the synchronous up-counter cycle changes 2 changes [ Table 5. from the textbook ]
111 Derivation of the synchronous up-counter cycle changes 2 changes T = T = T 2 = [ Table 5. from the textbook ]
112 A four-bit synchronous up-counter T = T = T 2 = [ Figure 5.2 from the textbook ]
113 In general we have T = T = T 2 = T 3 = 2 T n = 2 n-
114 Synchronous v.s. Asynchronous Clear
115 2-Bit Synchronous Up-Counter (without clear capability) T T
116 2-Bit Synchronous Up-Counter (with asynchronous clear) T T Clear_n
117 2-Bit Synchronous Up-Counter (with asynchronous clear) D D Clear_n This is the same circuit but uses D Flip-Flops.
118 2-Bit Synchronous Up-Counter (with synchronous clear) D D Clear_n This counter can be cleared only on the positive clock edge.
119 Adding Enable Capability
120 A four-bit synchronous up-counter [ Figure 5.2 from the textbook ]
121 Inclusion of Enable and Clear Capability Enable T T T T Clear_n [ Figure 5.22 from the textbook ]
122 Inclusion of Enable and Clear Capability This is the new thing relative to the previous figure, plus the clear_n line Enable T T T T Clear_n [ Figure 5.22 from the textbook ]
123 Providing an enable input for a D flip-flop [ Figure 5.56 from the textbook ]
124 Synchronous Counter (with D Flip-Flops)
125 A four-bit counter with D flip-flops [ Figure 5.23 from the textbook ]
126 Counters with Parallel Load
127 A 4-bit up-counter with D flip-flops [ Figure 5.23 from the textbook ]
128 A 4-bit up-counter with D flip-flops T flip-flop T flip-flop T flip-flop T flip-flop [ Figure 5.23 from the textbook ]
129 Equivalent to this circuit with T flip-flops Enable T T T T
130 Equivalent to this circuit with T flip-flops Z Enable T T T T But has one extra output called Z, which can be used to connect two 4-bit counters to make an 8-bit counter. When Z= the counter will go on the next clock edge, i.e., the outputs of all flip-flops are currently (maximum count value).
131 Counters with Parallel Load
132 A counter with parallel-load capability [ Figure 5.24 from the textbook ]
133 How to load the initial count value Set the initial count on the parallel load lines (in this case 5).
134 How to zero a counter Set "Load" to, to open the "" line of the multiplexers.
135 How to zero a counter When the next positive edge of the clock arrives, the outputs of the flip-flops are updated.
136 Reset Synchronization
137 Motivation An n-bit counter counts from,,, 2 n - For example a 3-bit counter counts up as follow,, 2, 3, 4, 5, 6, 7,,, 2, What if we want it to count like this,, 2, 3, 4, 5,,, 2, 3, 4, 5,,, In other words, what is the cycle is not a power of 2?
138 What does this circuit do? [ Figure 5.25a from the textbook ]
139 A modulo-6 counter with synchronous reset Enable D D D 2 Load 2 (a) Circuit 2 Count (b) Timing diagram [ Figure 5.25 from the textbook ]
140 A modulo-6 counter with asynchronous reset T T T 2 (a) Circuit 2 Count (b) Timing diagram [ Figure 5.26 from the textbook ]
141 A modulo-6 counter with asynchronous reset T T T 2 (a) Circuit The number 5 is displayed for a very short amount of time 2 Count (b) Timing diagram [ Figure 5.26 from the textbook ]
142 uestions?
143 THE END
CprE 281: Digital Logic
CprE 28: Digital Logic Instructor: Alexander Stoytchev http://www.ece.iastate.edu/~alexs/classes/ Registers and Counters CprE 28: Digital Logic Iowa State University, Ames, IA Copyright Alexander Stoytchev
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