AltiumLive 2017: Effective Methods for Advanced Routing

Size: px
Start display at page:

Download "AltiumLive 2017: Effective Methods for Advanced Routing"

Transcription

1 AltiumLive 2017: Effective Methods for Advanced Routing Charles Pfeil Senior Product Manager Dave Cousineau Sr. Field Applications Engineer

2 Charles Pfeil Senior Product Manager Over 50 years of experience in the PCB design and software industry. Designer and owner of service bureau. Worked for Racal-Redac, ASI, Cadence, Intergraph, VeriBest, Mentor Graphics, and now Altium. Architect of products with automation that gives the designer control, quality results, fast performance. Holder of 11 patents. Wrote a design book titled, "BGA Breakouts and Routing". Inducted into the PCB Design Hall of Fame by the UP Media Group. 2

3 Agenda 1 Routing Problems 2 3 Techniques Breakouts Fine Pitch BGAs 4 Quality 5 Rules 6 Differential Pair Routing 3

4 Routing Problems Routing can be difficult and time consuming Dense board area and limited layers Before increasing layer count, consider alternatives River routing, via-in-pad, stacked µvias Reduce trace widths, use thin dielectrics High-speed concerns Manage all concerns based on edge rates and data rates Timing Use realistic tolerances, tune gaps. Driver compensation? Crosstalk Manage clearance to aggressor relative to reference plane Impedance Realistic management of the appropriate concerns 4

5 Routing Problems Additional routing difficulties Over-constrained rules Can make design needlessly complex unnecessary rules don t improve the design Compromise in the right places identify problems and review with engineering early Fabrication requirements Know your fabricator s capabilities clarify discrepancies at the beginning of the design Create templates based on fabricator and via technology used. Investigate if HDI can be lower cost HDI Handbook, Happy Holden presentations The art of PCB design is discovering and applying the suitable compromises that enable the circuits to work as desired, while meeting the time and cost budgets. 5

6 Agenda 1 Routing Problems 2 3 Techniques Breakouts Fine Pitch BGAs 4 Quality 5 Rules 6 Differential Pair Routing 6

7 Routing Techniques Improved routing software enables productivity Take advantage of automation Does it allow designer control? Does it produce manual quality? River routing Reduce vias, manage impedance Gloss & Retrace Better diff pair quality, even over manual route Pad entry, change width gap 7 Interactive routing tools continue to increase levels of automation.

8 Routing Techniques Improved routing software enables productivity Copy & paste Simplifies fanouts and makes them consistent Use a grid! Factor of pin-pitch, reset origin to pin Pin swap Can make routing much more direct, less layers Keyboard shortcuts Learn the shortcuts, use them Create a list of the ones you use the most 8 Automated interactive routing tools increase productivity with user control and quality.

9 Agenda 1 Routing Problems 2 3 Techniques Breakouts Fine Pitch BGAs 4 Quality 5 Rules 6 Differential Pair Routing 9

10 Breakouts Fine Pitch BGAs Breakout of fine-pitch BGAs Fanout & escape tracks for.65mm pitch Difficult challenge Will get worse as pin-count increases Via-in-pad methods Best approach Location of via can improve route density Reduce trace widths Thru-via vs µvia If pin-count high, need µvias or high layer count Today, stacked µvias is by far the best solution for very dense HDI designs. 10

11 Breakouts Fine Pitch BGAs Push perimeter fanouts If perimeter pins need fanouts, push away from BGA Can eliminate one escape layer for large BGAs Especially useful if there are power & ground pins on the outer two rows 11 Creating effective fanout patterns is puzzle solving that can increase route density.

12 Breakouts Fine Pitch BGAs Via in Pad VIP Pattern A µvia in the center of ball pad Via hole must be filled and smoothed Eliminates trapped air voids during soldering Route density may not be maximized B-C-D patterns may be better depending on pitch VIP pattern for.4mm pitch BGAs 12 Experiment with different patterns and find what is most effective.

13 Breakouts Fine Pitch BGAs Offset VIP Pattern B The µvia offset from center, still completely inside the ball pad May not need to fill & smooth µvia Likelihood of trapped air voids is much smaller than in the case of the A pattern. This Offset VIP is optimal for.5mm and.65mm pitch BGAs 13 Patterns may be applied on the whole BGA or locally as needed.

14 Breakouts Fine Pitch BGAs Partial VIP Pattern C µvia hole intersects the edge of the ball pad Location determined by route density Maximize the number of traces that can be run through the channel between µvias µvia hole may not need filling & smoothing Work with fabricator and assembler Find out if not filling the µvia is supported C pattern good for.65mm &.8mm pitch 14 Route as much as allowed on outer layers, and push outer fanouts away from BGA.

15 Breakouts Fine Pitch BGAs Partial VIP Pattern C Partial VIP Inner Layers Increase the potential number of tracks running between the vias. Useful for critical signals, power and ground, diff pairs 15 Vertical channels may be blocked depending upon via and track sizes.

16 Breakouts Fine Pitch BGAs Near VIP Pattern D µvia hole completely outside edge of ball pad Soldermask opening concern Make µvia hole completely outside the soldermask opening for the ball pad Potential maximum density May enable the best alignment of the µvias in columns and rows for the greatest route density D pattern good for.65mm and.8mm pitch 16 Experiment, but make sure you discuss solutions with fabricator.

17 Breakouts Fine Pitch BGAs Near VIP Pattern D NEAR VIP Inner Layers Maximize the potential number of tracks running between the vias. Can be 25% greater space than Partial VIP 17 Take advantage of pins that don t need fanouts and consider them in patterns.

18 Breakouts Fine Pitch BGAs 0.65 mm BGA - VIP 300 µm Ball Pad 100 µm Trace 180 µm µvia 18

19 Breakouts Fine Pitch BGAs 0.65 mm BGA - VIP 300 µm Ball Pad 100/75 µm Trace 275 µm µvia 19

20 Breakouts Fine Pitch BGAs 0.5 mm BGA - VIP 200 µm Ball Pad 100 µm Trace 200 µm µvia 20

21 Breakouts Fine Pitch BGAs 0.5 mm BGA Offset VIP 250 µm Ball Pad 75 µm Trace 200 µm µvia Better than VIP 21

22 Breakouts Fine Pitch BGAs 0.4 mm BGA VIP 180 µm Ball Pad 75 µm Trace 180 µm µvia.35 mm BGA Same approach as.4 mm But smaller feature sizes 22

23 Breakouts Fine Pitch BGAs 0.4 mm BGA Offset VIP 180 µm Ball Pad 75 µm Trace 180 µm µvia Worse than VIP Fewer total tracks VIP = 1 per channel Offset VIP =.75 23

24 Agenda 1 Routing Problems 2 3 Techniques Breakouts Fine Pitch BGAs 4 Quality 5 Rules 6 Differential Pair Routing 24

25 Route Quality Quality is about routing efficiently and meeting requirements Efficiency - Reduce meandering, vias, route segments Makes it easier to edit later Signal behavior requirements Symmetry looks nice, but avoid enabling crosstalk A design that works is the #1 priority Fabrication recommendation: Space is King Use automation that improves quality I certainly appreciate artistic work, but 25 An artistic appearance is a result, not the cause, of quality design.

26 Route Quality Quality is about routing efficiently and meeting requirements Efficiency - Reduce meandering, vias, route segments Makes it easier to edit later Signal behavior requirements Symmetry looks nice, but avoid enabling crosstalk A design that works is the #1 priority Fabrication recommendation: Space is King Use automation that improves quality I certainly appreciate artistic work, but 26 An artistic appearance is a result, not the cause, of quality design.

27 Agenda 1 Routing Problems 2 3 Techniques Breakouts Fine Pitch BGAs 4 Quality 5 Rules 6 Differential Pair Routing 27

28 Rules To ensure success, properly constrain the routing Use the rules for DRC and control Avoid wantonly ignoring rules Automation can make it easier Simplify the rule definitions Avoid over-constraining 28 Appropriately defining the rules makes routing and editing easier and faster.

29 Rules Over Constraining Conservative data sheets Skew budget (length tolerances) often in unnecessarily small Why? Desire to eliminate possibility of potential problems Finding the right balance of compromise Often not possible to over-constrain everything without sacrificing one or more of these: cost, time, size, performance or reliability Design Software If the software enables you to easily address the over constrained rules, why not use it? Allows the margin (available skew) to be reserved for other effects 29 Over constraining a design may result in more layers and higher cost.

30 Rules Over Constraining The truth Rick Hartley s presentation The Truth About Differential Pairs in High Speed PCBs illustrates that over constraining differential pairs may not be necessary Rick s view on differential pair length tolerance based on circuit speed 30

31 Rules The other side of the coin If it isn t broke, don t fix it Organizations continue conservative design practices simply because they worked in the past Reluctance to analyze constraints to determine if they are really necessary Pushing the envelope Continually strive to make process more efficient and effective Most important question At what data rate can a particular diff pair concern become significant and how is it to be managed? 31 Analyze constraints and solutions to reduce time to market and fab yield

32 Agenda 1 Routing Problems 2 3 Techniques Breakouts Fine Pitch BGAs 4 Quality 5 Rules 6 Differential Pair Routing 32

33 Differential Pair Routing Addressing concerns based on data rates 33 Know the problems & solutions Manage the primary concerns Timing, impedance, crosstalk Avoid over-constraining Reasonable tolerances Auto compensation Allows for greater timing margins Pad entry Converge ASAP with equal length

34 Differential Pair Routing Diff pair may be shorter due to faster propagation Avoid Creepy Lengths when the target length keeps growing if routed in positive tolerance In length matching, include via-used and pinpackage lengths Tuning compliments together results in no skew difference, it is always balanced Rick Hartley s Truth About Diff Pairs Diff Pair 3xH Aggressor H Reference plane 34 To prevent crosstalk on diff pair Corner and pad entry skew adjustments

35 Differential Pair Routing Corner Pad Entry Keep stitch vias equidistant to DP vias Phase match start at driver, bump at mismatch Fiberweave routing If loose weave makes one compliment is over glass and the other over resin 35 Search: Jeff Loyer fiber weave effect Best presentation on topic

36 Differential Pair Routing Impedance discontinuities can cause reflections which may add noise to signal Cannot avoid all of these discontinuities, so try to minimize the number of them 36 It is simply a matter modifying the routing to keep the same impedance, with reason

37 Differential Pair Routing 37 Remove stubs with backdrilling Eliminate stubs with µvias

38 Differential Pair Routing Using arcs When does it matter? When the data rate is >16Gb/s everything matters 38 Arcs are beautiful, but usually not necessary

39 Differential Pair Routing Pad entry Converge ASAP with equal length This will help to eliminate skew at the start and end of the routing Pad entry gloss may work well Fabrication concerns Teardrops, etch traps, soldermask Balanced pad entry Very Good Usually Within Tolerance 39 Pad entry is a good example in which automation can make routing a lot easier

40 Conclusion Routing tools and methods are improving: Tools continually enhanced for new circuit, component and fabrication technology New methods with effective automation can increase productivity and quality Using the available skew for each circuit will increase productivity Avoid over-constraining and making routing easier, yet still effective 40 Get the most out of the available automation for routing.

41 DRC Checklist Check Priorities for all rules Ensure that All-All Width and Clearance rules exist Set to lowest Priority All used via sizes fall within Via Style Min and Max values Actual Class names match those in Class-scoped rules Class name = power vs. Rule = InNetClass( pwr ) All (or appropriate) Routing Layers are enabled Check applicability of more complex rule scopes using Test Queries button Ensure that necessary rules are enabled! 41 For Interactive Routing, set Width and Via sources to Rule Preferred

42 Thanks for your Attention! Questions?

AltiumLive 2017: The Benefits of Grid Systems in Board Design

AltiumLive 2017: The Benefits of Grid Systems in Board Design AltiumLive 2017: The Benefits of Grid Systems in Board Design Susy Webb Sr PCB Designer San Diego, CA October 3-4, 2017 The information contained herein is the opinion of the presenter and not considered

More information

IMPACT ORTHOGONAL ROUTING GUIDE

IMPACT ORTHOGONAL ROUTING GUIDE Impact TM Orthogonal Midplane System Routing Guide SYSTEM ROUTING GUIDE 1 of 15 TABLE OF CONTENTS I. Overview of the Connector...3 II. Routing Strategies... Compliant Pin Via Construction... Transmission

More information

Optimizing BNC PCB Footprint Designs for Digital Video Equipment

Optimizing BNC PCB Footprint Designs for Digital Video Equipment Optimizing BNC PCB Footprint Designs for Digital Video Equipment By Tsun-kit Chin Applications Engineer, Member of Technical Staff National Semiconductor Corp. Introduction An increasing number of video

More information

Verification of HBM through Direct Probing on MicroBumps

Verification of HBM through Direct Probing on MicroBumps Verification of HBM through Direct Probing on MicroBumps FormFactor Sung Wook Moon SK hynix Outline HBM market HBM test flow Device structure overview Key test challenges addressed Signal delivery and

More information

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011

ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 ECEN689: Special Topics in High-Speed Links Circuits and Systems Spring 2011 Lecture 9: TX Multiplexer Circuits Sam Palermo Analog & Mixed-Signal Center Texas A&M University Announcements & Agenda Next

More information

NextGIn( Connec&on'to'the'Next'Level' Application note Fan-out Xilinx FLGA 2892 using VeCS. Joan Tourné & Joe Dickson NextGIn Technology BV

NextGIn( Connec&on'to'the'Next'Level' Application note Fan-out Xilinx FLGA 2892 using VeCS. Joan Tourné & Joe Dickson NextGIn Technology BV NextGIn( Connec&on'to'the'Next'Level' Application note Fan-out Xilinx FLGA 2892 using VeCS. Joan Tourné & Joe Dickson NextGIn Technology BV March 20 th 2017 The objective of this document is showing the

More information

Xpedition Layout for Package Design. Student Workbook

Xpedition Layout for Package Design. Student Workbook Student Workbook 2017 Mentor Graphics Corporation All rights reserved. This document contains information that is trade secret and proprietary to Mentor Graphics Corporation or its licensors and is subject

More information

High Speed Digital Design Seminar

High Speed Digital Design Seminar High Speed Digital Design Seminar Introduction to Black Magic, with Dr. Howard Johnson About this course Printable Index 1. Vocabulary of Signal Integrity High Speed Digital Design: Opening Lecture. HSDD

More information

How to overcome/avoid High Frequency Effects on Debug Interfaces Trace Port Design Guidelines

How to overcome/avoid High Frequency Effects on Debug Interfaces Trace Port Design Guidelines How to overcome/avoid High Frequency Effects on Debug Interfaces Trace Port Design Guidelines An On-Chip Debugger/Analyzer (OCD) like isystem s ic5000 (Figure 1) acts as a link to the target hardware by

More information

Technology Overview LTCC

Technology Overview LTCC Sheet Code RFi0604 Technology Overview LTCC Low Temperature Co-fired Ceramic (LTCC) is a multilayer ceramic substrate technology that allows the realisation of multiple embedded passive components (Rs,

More information

Spatial Light Modulators XY Series

Spatial Light Modulators XY Series Spatial Light Modulators XY Series Phase and Amplitude 512x512 and 256x256 A spatial light modulator (SLM) is an electrically programmable device that modulates light according to a fixed spatial (pixel)

More information

PCIe: EYE DIAGRAM ANALYSIS IN HYPERLYNX

PCIe: EYE DIAGRAM ANALYSIS IN HYPERLYNX PCIe: EYE DIAGRAM ANALYSIS IN HYPERLYNX w w w. m e n t o r. c o m PCIe: Eye Diagram Analysis in HyperLynx PCI Express Tutorial This PCI Express tutorial will walk you through time-domain eye diagram analysis

More information

Circuits Assembly September 1, 2003 Duck, Allen

Circuits Assembly September 1, 2003 Duck, Allen Article from: Circuits Assembly Article date: September 1, 2003 Author: Duck, Allen Depaneling is an overlooked step in surface-mount production and involves the separation of a single piece from its carrier

More information

IC Mask Design. Christopher Saint Judy Saint

IC Mask Design. Christopher Saint Judy Saint IC Mask Design Essential Layout Techniques Christopher Saint Judy Saint McGraw-Hill New York Chicago San Francisco Lisbon London Madrid Mexico City Milan New Delhi San Juan Seoul Singapore Sydney Toronto

More information

Practical De-embedding for Gigabit fixture. Ben Chia Senior Signal Integrity Consultant 5/17/2011

Practical De-embedding for Gigabit fixture. Ben Chia Senior Signal Integrity Consultant 5/17/2011 Practical De-embedding for Gigabit fixture Ben Chia Senior Signal Integrity Consultant 5/17/2011 Topics Why De-Embedding/Embedding? De-embedding in Time Domain De-embedding in Frequency Domain De-embedding

More information

7 DESIGN ASPECTS OF IoT PCB DESIGNS JOHN MCMILLAN, MENTOR GRAPHICS

7 DESIGN ASPECTS OF IoT PCB DESIGNS JOHN MCMILLAN, MENTOR GRAPHICS 7 DESIGN ASPECTS OF IoT PCB DESIGNS JOHN MCMILLAN, MENTOR GRAPHICS P C B D E S I G N W H I T E P A P E R w w w. p a d s. c o m INTRODUCTION: IoT EVERYWHERE Designing electronic products with IoT capabilities

More information

IPC-A-610F COMMON INSPECTION ERRORS TRAINING CERTIFICATION TEST (DVD-71C) v.2

IPC-A-610F COMMON INSPECTION ERRORS TRAINING CERTIFICATION TEST (DVD-71C) v.2 This test consists of twenty multiple-choice questions. All questions are from the video: IPC-A-610F Common Inspection Errors DVD-71C). Use the supplied Answer Sheet and circle the letter or word corresponding

More information

BTC and SMT Rework Challenges

BTC and SMT Rework Challenges BTC and SMT Rework Challenges Joerg Nolte Ersa GmbH Wertheim, Germany Abstract Rising customer demands in the field of PCB repair are a daily occurrence as the rapid electronic industry follows new trends

More information

Brian Holden Kandou Bus, S.A. IEEE GE Study Group September 2, 2013 York, United Kingdom

Brian Holden Kandou Bus, S.A. IEEE GE Study Group September 2, 2013 York, United Kingdom Simulation results for NRZ, ENRZ & PAM-4 on 16-wire full-sized 400GE backplanes Brian Holden Kandou Bus, S.A. brian@kandou.com IEEE 802.3 400GE Study Group September 2, 2013 York, United Kingdom IP Disclosure

More information

SMT Encoder for High Performance, High Volume Designs Small Size High Resolution Low Cost ChipEncoder Reflective Surface Mount Encoder Features

SMT Encoder for High Performance, High Volume Designs Small Size High Resolution Low Cost ChipEncoder Reflective Surface Mount Encoder Features SMT Encoder for High Performance, High Volume Designs Small Size 7.0mm (W) x 11.0mm (L) x 3.1mm (H) High Resolution Linear: 10μm or 1μm per quadrature count Rotary: 3,300 to 327,000 quadrature counts per

More information

SPATIAL LIGHT MODULATORS

SPATIAL LIGHT MODULATORS SPATIAL LIGHT MODULATORS Reflective XY Series Phase and Amplitude 512x512 A spatial light modulator (SLM) is an electrically programmable device that modulates light according to a fixed spatial (pixel)

More information

ELECTRICAL PERFORMANCE REPORT

ELECTRICAL PERFORMANCE REPORT CIRCUITS & DESIGN ELECTRICAL PERFORMANCE REPORT DENSIPAC 4 ROW Date: 06-12-2006 Circuits & Design EMEA Circuits & Design 1/21 06/12/2006 1 INTRODUCTION... 3 2 CONNECTORS, TEST BOARDS AND TEST EQUIPMENT...

More information

MODIFYING A SMALL 12V OPEN FRAME INDUSTRIAL VIDEO MONITOR TO BECOME A 525/625 & 405 LINE MULTI - STANDARD MAINS POWERED UNIT. H. Holden. (Dec.

MODIFYING A SMALL 12V OPEN FRAME INDUSTRIAL VIDEO MONITOR TO BECOME A 525/625 & 405 LINE MULTI - STANDARD MAINS POWERED UNIT. H. Holden. (Dec. MODIFYING A SMALL 12V OPEN FRAME INDUSTRIAL VIDEO MONITOR TO BECOME A 525/625 & 405 LINE MULTI - STANDARD MAINS POWERED UNIT. H. Holden. (Dec. 2017) INTRODUCTION: Small open frame video monitors were made

More information

Advancements in Acoustic Micro-Imaging Tuesday October 11th, 2016

Advancements in Acoustic Micro-Imaging Tuesday October 11th, 2016 Central Texas Electronics Association Advancements in Acoustic Micro-Imaging Tuesday October 11th, 2016 A review of the latest advancements in Acoustic Micro-Imaging for the non-destructive inspection

More information

AFM1 Imaging Operation Procedure (Tapping Mode or Contact Mode)

AFM1 Imaging Operation Procedure (Tapping Mode or Contact Mode) AFM1 Imaging Operation Procedure (Tapping Mode or Contact Mode) 1. Log into the Log Usage system on the SMIF web site 2. Open Nanoscope 6.14r1 software by double clicking on the Nanoscope 6.14r1 desktop

More information

Keysight Method of Implementation (MOI) for VESA DisplayPort (DP) Standard Version 1.3 Cable-Connector Compliance Tests Using E5071C ENA Option TDR

Keysight Method of Implementation (MOI) for VESA DisplayPort (DP) Standard Version 1.3 Cable-Connector Compliance Tests Using E5071C ENA Option TDR Revision 1.00 February 27, 2015 Keysight Method of Implementation (MOI) for VESA DisplayPort (DP) Standard Version 1.3 Cable-Connector Compliance Tests Using E5071C ENA Option TDR 1 Table of Contents 1.

More information

16B CSS LAYOUT WITH GRID

16B CSS LAYOUT WITH GRID 16B CSS LAYOUT WITH GRID OVERVIEW Grid terminology Grid display type Creating the grid template Naming grid areas Placing grid items Implicit grid behavior Grid spacing and alignment How CSS Grids Work

More information

Why Use the Cypress PSoC?

Why Use the Cypress PSoC? C H A P T E R1 Why Use the Cypress PSoC? Electronics have dramatically altered the world as we know it. One has simply to compare the conveniences and capabilities of today s world with those of the late

More information

RF V W-CDMA BAND 2 LINEAR PA MODULE

RF V W-CDMA BAND 2 LINEAR PA MODULE 3 V W-CDMA BAND 2 LINEAR PA MODULE Package Style: Module, 10-Pin, 3 mm x 3 mm x 1.0 mm Features HSDPA and HSPA+ Compliant Low Voltage Positive Bias Supply (3.0 V to 4.35 V) +28.5 dbm Linear Output Power

More information

COLOUR CHANGING USB LAMP KIT

COLOUR CHANGING USB LAMP KIT TEACHING RESOURCES SCHEMES OF WORK DEVELOPING A SPECIFICATION COMPONENT FACTSHEETS HOW TO SOLDER GUIDE SEE AMAZING LIGHTING EFFECTS WITH THIS COLOUR CHANGING USB LAMP KIT Version 2.1 Index of Sheets TEACHING

More information

Creating the Perfect Colorbar

Creating the Perfect Colorbar Creating the Perfect Colorbar What is Perfect? Each printing environment is different. Presses differ. Processes differ. Media differs. What then makes up a perfect colorbar? In simple terms, it is a pattern

More information

Scan. This is a sample of the first 15 pages of the Scan chapter.

Scan. This is a sample of the first 15 pages of the Scan chapter. Scan This is a sample of the first 15 pages of the Scan chapter. Note: The book is NOT Pinted in color. Objectives: This section provides: An overview of Scan An introduction to Test Sequences and Test

More information

Vias structural details and its effect on System performance

Vias structural details and its effect on System performance Vias structural details and its effect on System performance Roger Dame, Principal Engineer, Oracle Corporation Gustavo Blando, Principal Engineer, Oracle Corporation Istvan Novak, Senior Principal Engineer,

More information

polarinstruments.com

polarinstruments.com How to model PCB transmission lines and manage layer stackup Design system for PCB layer stackup combined with PCB transmission line field solver. SB9000 Fast stack creation Major material supplier libraries

More information

EVALUATION KIT AVAILABLE Multirate SMPTE SD/HD Cable Driver with Selectable Slew Rate TOP VIEW +3.3V. 10nF IN+ IN- MAX3812 SD/HD GND RSET +3.

EVALUATION KIT AVAILABLE Multirate SMPTE SD/HD Cable Driver with Selectable Slew Rate TOP VIEW +3.3V. 10nF IN+ IN- MAX3812 SD/HD GND RSET +3. 19-3571; Rev ; 2/5 EVALUATION KIT AVAILABLE Multirate SMPTE SD/HD Cable Driver General Description The is a multirate SMPTE cable driver designed to operate at data rates up to 1.485Gbps, driving one or

More information

The Effect of Wire Length Minimization on Yield

The Effect of Wire Length Minimization on Yield The Effect of Wire Length Minimization on Yield Venkat K. R. Chiluvuri, Israel Koren and Jeffrey L. Burns' Department of Electrical and Computer Engineering University of Massachusetts, Amherst, MA 01003

More information

RSH27 Nixie Tube Socket with LED

RSH27 Nixie Tube Socket with LED Contents: 1. Applications of the socket 2. Solder instructions of the socket 3. Drawing of the assembled socket 4. Section drawing of the socket with IN-8 tube 5. Drawing and technical data of the tube

More information

Axle Assembly Poke-Yoke

Axle Assembly Poke-Yoke Indiana University Purdue University Fort Wayne Opus: Research & Creativity at IPFW Manufacturing & Construction Engineering Technology and Interior Design Senior Design Projects School of Engineering,

More information

I. Introduction. II. Problem

I. Introduction. II. Problem Wiring Deformable Mirrors for Curvature Adaptive Optics Systems Joshua Shiode Boston University, IfA REU 2005 Sarah Cook University of Hawaii, IfA REU 2005 Mentor: Christ Ftaclas Institute for Astronomy,

More information

UV Nanoimprint Tool and Process Technology. S.V. Sreenivasan December 13 th, 2007

UV Nanoimprint Tool and Process Technology. S.V. Sreenivasan December 13 th, 2007 UV Nanoimprint Tool and Process Technology S.V. Sreenivasan December 13 th, 2007 Agenda Introduction Need tool and process technology that can address: Patterning and CD control Alignment and Overlay Defect

More information

EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043

EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043 EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP Due 16.05. İLKER KALYONCU, 10043 1. INTRODUCTION: In this project we are going to design a CMOS positive edge triggered master-slave

More information

VISSIM TUTORIALS This document includes tutorials that provide help in using VISSIM to accomplish the six tasks listed in the table below.

VISSIM TUTORIALS This document includes tutorials that provide help in using VISSIM to accomplish the six tasks listed in the table below. VISSIM TUTORIALS This document includes tutorials that provide help in using VISSIM to accomplish the six tasks listed in the table below. Number Title Page Number 1 Adding actuated signal control to an

More information

Meeting Embedded Design Challenges with Mixed Signal Oscilloscopes

Meeting Embedded Design Challenges with Mixed Signal Oscilloscopes Meeting Embedded Design Challenges with Mixed Signal Oscilloscopes Introduction Embedded design and especially design work utilizing low speed serial signaling is one of the fastest growing areas of digital

More information

Perfecting the Package Bare and Overmolded Stacked Dies. Understanding Ultrasonic Technology for Advanced Package Inspection. A Sonix White Paper

Perfecting the Package Bare and Overmolded Stacked Dies. Understanding Ultrasonic Technology for Advanced Package Inspection. A Sonix White Paper Perfecting the Package Bare and Overmolded Stacked Dies Understanding Ultrasonic Technology for Advanced Package Inspection A Sonix White Paper Perfecting the Package Bare and Overmolded Stacked Dies Understanding

More information

Advanced WLP Platform for High-Performance MEMS. Presented by Dean Spicer, Director of Engineering

Advanced WLP Platform for High-Performance MEMS. Presented by Dean Spicer, Director of Engineering Advanced WLP Platform for High-Performance MEMS Presented by Dean Spicer, Director of Engineering 1 May 11 th, 2016 1 Outline 1. Application Drivers for High Performance MEMS Sensors 2. Approaches to Achieving

More information

TKK S ASIC-PIIRIEN SUUNNITTELU

TKK S ASIC-PIIRIEN SUUNNITTELU Design TKK S-88.134 ASIC-PIIRIEN SUUNNITTELU Design Flow 3.2.2005 RTL Design 10.2.2005 Implementation 7.4.2005 Contents 1. Terminology 2. RTL to Parts flow 3. Logic synthesis 4. Static Timing Analysis

More information

Microwave Interconnect Testing For 12G-SDI Applications

Microwave Interconnect Testing For 12G-SDI Applications DesignCon 2016 Microwave Interconnect Testing For 12G-SDI Applications Jim Nadolny, Samtec jim.nadolny@samtec.com Corey Kimble, Craig Rapp Samtec OJ Danzy, Mike Resso Keysight Boris Nevelev Imagine Communications

More information

Features. = +25 C, Vs = 5V, Vpd = 5V

Features. = +25 C, Vs = 5V, Vpd = 5V v1.117 HMC326MS8G / 326MS8GE AMPLIFIER, 3. - 4. GHz Typical Applications The HMC326MS8G / HMC326MS8GE is ideal for: Microwave Radios Broadband Radio Systems Wireless Local Loop Driver Amplifier Functional

More information

Achieving Faster Time to Tapeout with In-Design, Signoff-Quality Metal Fill

Achieving Faster Time to Tapeout with In-Design, Signoff-Quality Metal Fill White Paper Achieving Faster Time to Tapeout with In-Design, Signoff-Quality Metal Fill May 2009 Author David Pemberton- Smith Implementation Group, Synopsys, Inc. Executive Summary Many semiconductor

More information

Developing Standard Cells for TSMC 0.25 µm Technology with MOSIS DEEP Rules

Developing Standard Cells for TSMC 0.25 µm Technology with MOSIS DEEP Rules Developing Standard Cells for TSMC 0.25 µm Technology with MOSIS DEEP Rules Dong S. Ha, Jos B. Sulistyo, and Jonathan Perry Virginia Tech VLSI for Telecommunication Laboratory Bradley Department of Electrical

More information

Cicoil. Not your father s flat cable

Cicoil. Not your father s flat cable Cicoil Not your father s flat cable Innovative design enhancements make flat cables strong candidates for applications where round cable was once the natural choice. Typical Round Cable Components Flat

More information

APPLICATION NOTE. Practical Tips for Using Metalic Time Domain Reflectometers (The EZ Way) What is a Time Domain Reflectometer?

APPLICATION NOTE. Practical Tips for Using Metalic Time Domain Reflectometers (The EZ Way) What is a Time Domain Reflectometer? a publication of R MEETING YOUR TESTING NEEDS TODAY AND TOMORROW Publication Number TTS3-0901 APPLICATION NOTE Practical Tips for Using Metalic Time Domain Reflectometers (The EZ Way) What is a Time Domain

More information

Boosting Performance Oscilloscope Versatility, Scalability

Boosting Performance Oscilloscope Versatility, Scalability Boosting Performance Oscilloscope Versatility, Scalability Rising data communication rates are driving the need for very high-bandwidth real-time oscilloscopes in the range of 60-70 GHz. These instruments

More information

E-TEXTILES STARTER PACK

E-TEXTILES STARTER PACK LEARN HOW TO SEW A CIRCUIT WITH THIS E-TEXTILES STARTER PACK WHITE LEDs BLUE LEDs LARGE COIN CELL MINIATURE COIN CELL SEWABLE ELECTRONICS INTRODUCTION TO ELECTRO-FASHION Electro-Fashion is Kitronik's own

More information

Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Link Work Right Out of the Box

Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Link Work Right Out of the Box Using Allegro PCB SI GXL to Make Your Multi-GHz Serial Link Work Right Out of the Box Session 8.11 - Hamid Kharrati - A2e Technologies Agenda About the Project Modeling the System Frequency Domain Analysis

More information

Wafer Thinning and Thru-Silicon Vias

Wafer Thinning and Thru-Silicon Vias Wafer Thinning and Thru-Silicon Vias The Path to Wafer Level Packaging jreche@trusi.com Summary A new dry etching technology Atmospheric Downstream Plasma (ADP) Etch Applications to Packaging Wafer Thinning

More information

Smart. Connected. Energy-Friendly.

Smart. Connected. Energy-Friendly. www.silabs.com Smart. Connected. Energy-Friendly. Miniaturizing IoT Designs Tom Nordman, Pasi Rahikkala This whitepaper explores the challenges that come with designing connected devices into increasingly

More information

Christmas LED Snowflake Project

Christmas LED Snowflake Project Christmas LED Snowflake Project Version 1.1 (01/12/2008) The snowflake is a follow-on from my Christmas star project from a few years ago. This year I decided to make a display using only white LEDs, shaped

More information

Flat Panel Displays: LCD Technologies and Trends

Flat Panel Displays: LCD Technologies and Trends Flat Panel Displays: LCD Technologies and Trends Robert Dunhouse, Sr. Engineering Manager, Display BU Class ID: 4C01B Renesas Electronics America Inc. Robert F. Dunhouse, Jr. Sr. Engineering Manager, Display

More information

AN-822 APPLICATION NOTE

AN-822 APPLICATION NOTE APPLICATION NOTE One Technology Way P.O. Box 9106 Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 www.analog.com Synchronization of Multiple AD9779 Txs by Steve Reine and Gina Colangelo

More information

PRESS FOR SUCCESS. Meeting the Document Make-Ready Challenge

PRESS FOR SUCCESS. Meeting the Document Make-Ready Challenge PRESS FOR SUCCESS Meeting the Document Make-Ready Challenge MEETING THE DOCUMENT MAKE-READY CHALLENGE PAGE DESIGN AND LAYOUT TEXT EDITS PDF FILE GENERATION COLOR CORRECTION COMBINING DOCUMENTS IMPOSITION

More information

semi-automated scanning

semi-automated scanning semi-automated scanning The X-Rite EasyTrax semi-automated scanning solution is a great tool for our short and long run book cover manufacturing process. We are excited that it quickly targets color and

More information

Graphics Video Sync Adder/Extractor

Graphics Video Sync Adder/Extractor 19-0602; Rev 2; 1/07 EVALUATION KIT AVAILABLE Graphics Video Sync Adder/Extractor General Description The chipset provides a 3-wire (RGB) interface for 5-wire (RGBHV) video by adding and extracting the

More information

Equalizing XAUI Backplanes with the MAX3980

Equalizing XAUI Backplanes with the MAX3980 Design Note: HFDN-17.0 Rev.1; 04/08 Equalizing XAUI Backplanes with the MAX3980 AVAILABLE Equalizing XAUI Backplanes with the MAX3980 1 Introduction This discussion explores the performance of the MAX3980

More information

Seamless Ultra-Fine Pitch LED Video Walls

Seamless Ultra-Fine Pitch LED Video Walls Seamless Ultra-Fine Pitch LED Video Walls Table of Contents Introduction: What Is DirectView LED Technology? 2 DirectView LED Fundamentals Comparing LED to Other Technologies What to Consider 3 9 10 Examples

More information

Component Placement Tutorial Part One

Component Placement Tutorial Part One CIRCUIT BOARD DESIGNERS WEB SITE Component Placement Tutorial Part One by Jack Olson CATERPILLAR IN SUMMARY Jack Olson is creating an introductory tutorial Web site for novice circuit board designers.

More information

Sharif University of Technology. SoC: Introduction

Sharif University of Technology. SoC: Introduction SoC Design Lecture 1: Introduction Shaahin Hessabi Department of Computer Engineering System-on-Chip System: a set of related parts that act as a whole to achieve a given goal. A system is a set of interacting

More information

INSTRUMENT CATHODE-RAY TUBE

INSTRUMENT CATHODE-RAY TUBE Instrument cathode-ray tube D14-363GY/123 INSTRUMENT CATHODE-RAY TUBE mono accelerator 14 cm diagonal rectangular flat face internal graticule low power quick heating cathode high brightness, long-life

More information

Features. = +25 C, IF = 1 GHz, LO = +13 dbm*

Features. = +25 C, IF = 1 GHz, LO = +13 dbm* v.5 HMC56LM3 SMT MIXER, 24-4 GHz Typical Applications Features The HMC56LM3 is ideal for: Test Equipment & Sensors Point-to-Point Radios Point-to-Multi-Point Radios Military & Space Functional Diagram

More information

Performance Modeling and Noise Reduction in VLSI Packaging

Performance Modeling and Noise Reduction in VLSI Packaging Performance Modeling and Noise Reduction in VLSI Packaging Ph.D. Defense Brock J. LaMeres University of Colorado October 7, 2005 October 7, 2005 Performance Modeling and Noise Reduction in VLSI Packaging

More information

HDSI Series Tensolite High-Performance Cable & Interconnect Systems

HDSI Series Tensolite High-Performance Cable & Interconnect Systems HDSI Series Tensolite High-Performance Cable & Interconnect Systems Tensolite's High Density Shielded Interconnect Products Tensolite s HDSI and HDSI-DP assemblies use ribbonized coaxial cable, matched

More information

The Omnichannel Challenge for Supply Chain Management. Ton de Kok

The Omnichannel Challenge for Supply Chain Management. Ton de Kok The Omnichannel Challenge for Supply Chain Management Ton de Kok L-Pad Case: Global Supply Chain AFM on Omnichannel 2015 2 L-Pad Case: Omnichannel AFM on Omnichannel 2015 3 Agenda E&Y survey research E&Y

More information

The Silicon Pixel Detector (SPD) for the ALICE Experiment

The Silicon Pixel Detector (SPD) for the ALICE Experiment The Silicon Pixel Detector (SPD) for the ALICE Experiment V. Manzari/INFN Bari, Italy for the SPD Project in the ALICE Experiment INFN and Università Bari, Comenius University Bratislava, INFN and Università

More information

OEM Basics. Introduction to LED types, Installation methods and computer management systems.

OEM Basics. Introduction to LED types, Installation methods and computer management systems. OEM Basics Introduction to LED types, Installation methods and computer management systems. v1.0 ONE WORLD LED 2016 The intent of the OEM Basics is to give the reader an introduction to LED technology.

More information

Innovative Fast Timing Design

Innovative Fast Timing Design Innovative Fast Timing Design Solution through Simultaneous Processing of Logic Synthesis and Placement A new design methodology is now available that offers the advantages of enhanced logical design efficiency

More information

Power Amplifier 0.5 W 2.4 GHz AM TR Features. Functional Schematic. Description. Pin Configuration 1. Ordering Information

Power Amplifier 0.5 W 2.4 GHz AM TR Features. Functional Schematic. Description. Pin Configuration 1. Ordering Information Features Ideal for 802.11b ISM Applications Single Positive Supply Output Power 27.5 dbm 57% Typical Power Added Efficiency Downset MSOP-8 Package Description M/A-COM s is a 0.5 W, GaAs MMIC, power amplifier

More information

Clocking Spring /18/05

Clocking Spring /18/05 ing L06 s 1 Why s and Storage Elements? Inputs Combinational Logic Outputs Want to reuse combinational logic from cycle to cycle L06 s 2 igital Systems Timing Conventions All digital systems need a convention

More information

Modifying the RW1127 and similar TWTs for 24GHz

Modifying the RW1127 and similar TWTs for 24GHz Modifying the RW1127 and similar TWTs for 24GHz Some notes by Brian G4NNS updated after the EME conference. Issue 1.04 During a visit from Johannes DF1OI he explained how Ulli DK3UC had modified Siemens

More information

3.22 Finalize exact specifications of 3D printed parts.

3.22 Finalize exact specifications of 3D printed parts. 3.22 Finalize exact specifications of 3D printed parts. This is the part that connect between the main tube and the phone holder, it needs to be able to - Fit into the main tube perfectly - This part need

More information

EVALUATION KIT AVAILABLE 12.5Gbps Settable Receive Equalizer +2.5V +3.3V V CC1 V CC. 30in OF FR-4 STRIPLINE OR MICROSTRIP TRANSMISSION LINE SDI+ SDI-

EVALUATION KIT AVAILABLE 12.5Gbps Settable Receive Equalizer +2.5V +3.3V V CC1 V CC. 30in OF FR-4 STRIPLINE OR MICROSTRIP TRANSMISSION LINE SDI+ SDI- 19-2713; Rev 1; 11/03 EVALUATION KIT AVAILABLE 12.5Gbps Settable Receive Equalizer General Description The driver with integrated analog equalizer compensates up to 20dB of loss at 5GHz. It is designed

More information

Comment #147, #169: Problems of high DFE coefficients

Comment #147, #169: Problems of high DFE coefficients Comment #147, #169: Problems of high DFE coefficients Yasuo Hidaka Fujitsu Laboratories of America, Inc. September 16-18, 215 IEEE P82.3by 25 Gb/s Ethernet Task Force Comment #147 1 IEEE P82.3by 25 Gb/s

More information

Draft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ)

Draft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ) Draft Baseline Proposal for CDAUI-8 Chipto-Module (C2M) Electrical Interface (NRZ) Authors: Tom Palkert: MoSys Jeff Trombley, Haoli Qian: Credo Date: Dec. 4 2014 Presented: IEEE 802.3bs electrical interface

More information

Design Project: Designing a Viterbi Decoder (PART I)

Design Project: Designing a Viterbi Decoder (PART I) Digital Integrated Circuits A Design Perspective 2/e Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolić Chapters 6 and 11 Design Project: Designing a Viterbi Decoder (PART I) 1. Designing a Viterbi

More information

3M Pak 10 Socket 1 mm Straight and Right Angle, Surface Mount PK10 Series

3M Pak 10 Socket 1 mm Straight and Right Angle, Surface Mount PK10 Series 1 mm pitch connector system Stacked, Horizontal or Vertical Mating Low profile 5 mm mated height Surface mount retention clips reduce stress on surface mount leads Keyed design helps prevent mating misalignment

More information

National Park Service Photo. Utah 400 Series 1. Digital Routing Switcher.

National Park Service Photo. Utah 400 Series 1. Digital Routing Switcher. National Park Service Photo Utah 400 Series 1 Digital Routing Switcher Utah Scientific has been involved in the design and manufacture of routing switchers for audio and video signals for over thirty years.

More information

Stud Welding Equipment

Stud Welding Equipment Stud Welding Equipment 10/16 N550c Arc Charger Breakthrough Charger design provides powerful 550A Arc Welder from 120V wall outlet! The N550c Arc Charger is the first of a revolutionary new class of stud

More information

Performing Signal Integrity Analyses. Signal Integrity Overview. Modified by Phil Loughhead on 16-Nov-2015

Performing Signal Integrity Analyses. Signal Integrity Overview. Modified by Phil Loughhead on 16-Nov-2015 Performing Signal Integrity Analyses Old Content - visit altium.com/documentation Modified by Phil Loughhead on 16-Nov-2015 This tutorial looks at performing Signal Integrity (SI) analyses. It covers setting

More information

Transforming Electronic Interconnect Breaking through historical boundaries Tim Olson Founder & CTO

Transforming Electronic Interconnect Breaking through historical boundaries Tim Olson Founder & CTO Transforming Electronic Interconnect Breaking through historical boundaries Tim Olson Founder & CTO Remember when? There were three distinct industries Wafer Foundries SATS EMS Semiconductor Devices Nanometers

More information

Homework 6: Printed Circuit Board Layout Design Narrative

Homework 6: Printed Circuit Board Layout Design Narrative Homework 6: Printed Circuit Board Layout Design Narrative Team Code Name: The Hex Me Baby Team Group No. 3 Team Member Completing This Homework: Robert Harris E-mail Address of Team Member: harris89 @

More information

An Example of Eliminating a Technical Problem with Only One Single Part

An Example of Eliminating a Technical Problem with Only One Single Part An Example of Eliminating a Technical Problem with Only One Single Part Dr.-Ing. Bernd Mittmann Delphi Energy & Chassis Systems Technical Centre Luxembourg bernd.mittmann@delphi.com Introduction This presentation

More information

Designing High Performance Interposers with 3-port and 6-port S-parameters

Designing High Performance Interposers with 3-port and 6-port S-parameters DesignCon 2015 Designing High Performance Interposers with 3-port and 6-port S-parameters Joseph Socha, Nexus Technology joe.socha@nexustechnology.com Jonathan Dandy, Tektronix jonathan.s.dandy@tektronix.com

More information

Build A Video Switcher

Build A Video Switcher Build A Video Switcher VIDEOSISTEMAS serviciotecnico@videosistemas.com www.videosistemas.com Reprinted with permission from Electronics Now Magazine September 1997 issue Copyright Gernsback Publications,

More information

HMC958LC5 HIGH SPEED LOGIC - SMT. Typical Applications. Features. Functional Diagram. General Description

HMC958LC5 HIGH SPEED LOGIC - SMT. Typical Applications. Features. Functional Diagram. General Description Typical Applications Features The HMC958LC5 is ideal for: SONET OC-192 and 1 GbE 16G Fiber Channel 4:1 Multiplexer Built-In Test Broadband Test & Measurement Functional Diagram Supports High Data Rates:

More information

Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533

Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533 Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop Course project for ECE533 I. Objective: REPORT-I The objective of this project is to design a 4-bit counter and implement it into a chip

More information

The CAAMA Building and Fit Out

The CAAMA Building and Fit Out The CAAMA Building and Fit Out CAAMA (the Central Australian Media Association) as its name suggests is a multi media association. Over the years CAAMA had grown and spread and its different departments

More information

High Performance TFT LCD Driver ICs for Large-Size Displays

High Performance TFT LCD Driver ICs for Large-Size Displays Name: Eugenie Ip Title: Technical Marketing Engineer Company: Solomon Systech Limited www.solomon-systech.com The TFT LCD market has rapidly evolved in the last decade, enabling the occurrence of large

More information

3M High-Speed Solutions

3M High-Speed Solutions 3M High-Speed Solutions 3M 2011. All Rights Reserved. Distance 3M Electronic Solutions Division 3M Twin Axial and AOC Solutions Addressing Physical Medium Dependent in the InifiniBand Fabric 100m 10m 1m

More information

Commissioning the TAMUTRAP RFQ cooler/buncher. E. Bennett, R. Burch, B. Fenker, M. Mehlman, D. Melconian, and P.D. Shidling

Commissioning the TAMUTRAP RFQ cooler/buncher. E. Bennett, R. Burch, B. Fenker, M. Mehlman, D. Melconian, and P.D. Shidling Commissioning the TAMUTRAP RFQ cooler/buncher E. Bennett, R. Burch, B. Fenker, M. Mehlman, D. Melconian, and P.D. Shidling In order to efficiently load ions into a Penning trap, the ion beam should be

More information

LASER TROUBLESHOOTING GUIDE

LASER TROUBLESHOOTING GUIDE LASER TROUBLESHOOTING GUIDE MY SOFTWARE ISN T CONNECTING My software isn t connecting Browser Error If your software says disconnected, it is having trouble communicating with your laser. Try refreshing

More information

Copyright 2008 Society of Manufacturing Engineers. FUNDAMENTALS OF TOOL DESIGN Progressive Die Design

Copyright 2008 Society of Manufacturing Engineers. FUNDAMENTALS OF TOOL DESIGN Progressive Die Design FUNDAMENTALS OF TOOL DESIGN Progressive Die Design SCENE 1. PD06A, tape FTD29, 09:14:22:00-09:14:48:00 pan, progressive die operation PROGRESSIVE DIES PERFORM A SERIES OF FUNDAMENTAL CUTTING AND FORMING

More information