Engineering College. Electrical Engineering Department. Digital Electronics Lab

Transcription

1 Engineering College Electrical Engineering Department Digital Electronics Lab Prepared by: Dr. Samer Mayaleh Eng. Nuha Odeh 2009/

2 CONTENTS Experiment Name Page 1- Measurement of Basic Logic Gates Characteristic Schmitt Gate Circuit Open-Collector Gate Circuit Tristate Gate Circuit Comparator Circuit Half-Adder and Full-Adder Circuit Half-Subtractor and Full-Subtrator Circuit Decoder Circuit Multiplexer Circuit Encoder Circuit Demultiplexer Circuit Flip-Flop Circuits Shift Registers Counters Voltage Controlled Oscillator (VCO) Circuit Oscillator Circuits Electronic EPROM(EEPROM) Circuit Analog/Digital Converter (ADC) Circuit

3 OBJECTIVE Experiment#1 Measurements of Basic Logic Gates Characteristics Understand the symbols and characteristics of various basic logic gates. DISCUSSIONS The input and output characteristics of basic logic gates are defined below: VoH - High output voltage IOH - High output current VoL - Low output voltage IOL - Low output current VIH - High input voltage IIH - High input current VIL - Low input voltage IIL - Low input current Characteristics of TTL gates are different from those of CMOS gates. The load and current-limiting resistors they are connected to are different as well. For example, in the case of an OR gate and an AND gate: 1. OR gate: inputs of TTL are connected to a 1 KΩ resistor while inputs of CMOS gates are connected to a 10KΩ resistor. TTL with 1 KΩ resistor at the input CMOS with 10KΩ resistor at the input Resistance for the LS series TTL is approximately 5KΩ. If the X input of a TTL OR gate is grounded then the output F is equal to the input A (F=A), making expansion control impossible. If the resistor is grounded and there is no signal at X, then X is equivalent to being grounded and F=A. If necessary a signal could be added to X so that F=AxX. The output can be controlled by X. 2. AND gate: TTL AND gates are in high state when it is open or when a resistor is connected to the supply voltage. CMOS AND gates are in high state when a resistor of at least 1 0K S2 is connected to the supply voltage

4 "HIGH" CMOS AND gate The "Truth Table" is a table that shows a logic gate's corresponding inputs and outputs under ideal conditions. 1. OR gate STATE INPUT A B OUTPUT F When A=0, B=0 the output F=0 When A=0, B=1 the output F=1 When A=1, B=0 the output F=1 When A=1, B=1 the output F=1 In Boolean expression, F= A B + A B + A B= A+B 2. AND gate STATE INPUT A B INVERTER gate STATE INPUT A 0 0 OUTPUT F When A=0, B=0 the output F=0 When A=0, B=1 the output F=0 When A=1, B=0 the output F=0 When A=1, B=1 the output F=1 In Boolean expression, F=AB OUTPUT F 1 When A=0, the output F= When A=1, the output F=0-4 -

5 4. XOR gate STATE INPUT A B In Boolean expression, F= A OUTPUT F When A=B, the output F=0 When A B, the output F=1 In Boolean expression, F= A B + A B = A B 5. NAND gate The output of a NAND gate is the exact opposite of an AND gate. STATE INPUT A B In Boolean expression, F= AB OUTPUT F 0 When A=0, B=0 the output F=1 When A=0, B=1 the output F=1 When A=1, B=0 the output F=1 When A=1, B=1 the output F=0 6. NOR gate The output of a NOR gate is the exact opposite of an OR gate. STATE INPUT A B OUTPUT F When A=0, B=0 the output F=1 When A=0, B=1 the output F=0 When A=1, B=0 the output F=0 When A=1, B=1 the output F=0 In Boolean expression, F= A + B = A x B These truth tables are based on "positive" logic where positive voltage represents "1" and negative voltage represents "0". In case negative logic is used the output will be reversed. Compare the truth tables for a positive and a negative OR gate shown below: - 5 -

6 STATE INPUT OUTPUT A B F STATE INPUT OUTPUT A B F Observe the truth table for a negative logic OR gate. It to equivalent to a positive logic AND gate. EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; DLLT-EM01: Basic Logic Gates Experiment Module; and Oscilloscope PROCEDURES (a) AND Gate Characteristics Measurement (DLLT-EM01 circuit d) 1. Insert connection clips according to Fig U1a and U1b will be used in this section. 2. Connect inputs A1, A2 to Data Switch SW0, SW1 TTL level and output F3 to Logic Indicator L0. Follow the input sequences below and record the outputs. STATE INPUT A2 A OUTPUT F3 3. Connect A2 to the 10Hz TTL level output of Clock Generator. Measure and record the input and output waveforms

7 Fig. 1-1 STATE (b) OR Gate Characteristics Measurement (DLLT-EM01 circuit d) 1. U2a and U2b of DLLT-EM01 circuit d will be used in this section. 2. Connect inputs A3, A4 to SW0, SW1 TTL level and output F4 to L1. Follow the input sequences below and record output F. STATE INPUT A4 A OUTPUT F4 3. Connect A4 to the 10Hz TTL level output of Clock Generator. Measure and record the input and output waveforms

8 (c) INVERTER Gate Characteristics Measurement (Module DLLT-EM01 circuit d) 1. U3c of DLLT-EM01 circuit d will be used in this section. 2. Connect input C1 and output F6 of U3c to SW0 and L1 (LED) respectively. Follow the input sequences below and record outputs. 0 1 C1 0 1 F6 1. Connect F6 to C2 with a test lead. Connect output F7 to L2 (LED). Follow the input sequences below and record the outputs. 0 1 C2 0 1 F7 (d) NAND Gate Characteristics Measurement (DLLT-EM01 circuit d) 1. U1a of DLLT-EM01 circuit d will be used in this section. Connect inputs A1, A2 to SW0, SW1 TTL level and output F1 to L1 (LED). Follow the input sequences below and record the outputs. A2 A1 F Connect 10Hz TTL level square wave to A2, measure and record input/output waveforms at the following conditions

9 e) NOR Gate Characteristics Measurement (DLLT-EM01 circuit d) 1. U2a of DLLT-EM01 circuit d will be used in this section. Connect inputs A3, A4 to SW0, SW1 TTL level and output F2 to L1 (LED) Follow the input sequences below and record the outputs. A4 A3 F Connect TTL level 10Hz square wave to A4, observe and record input/output waveforms under the following conditions with an oscilloscope: (f) XOR Gate Characteristics Measurement (DLLT-EM01 circuit d) 1. U4a of DLLT-EM01 circuit d will be used in this section. Connect inputs C4, C5 to SW0, SW1 TTL level and output F9 to L1 (LED). Follow the input sequences below and record the outputs. C5 C4 F Connect TTL level 10Hz square wave to C4, observe and record input/ output waveforms under the following conditions with an oscilloscope

10 RESULTS 1. Phase relationship between input and output waveforms should be compared when square waves are added. EXERCISE 1. Refer to Fig. (1) and (2) below. Are they identical? Determine truth tables for both circuits. MULTIPLE CHOICE QUESTIONS 1. The corresponding input/output values of a logic gate are called: 1. Trigger table 2. Truth table 3. Specification table 2. In fig. (b), if B is to represent 0 when the circuit is open, a resistor should be connected from B to: 1. Ground 2. Supply voltage 3. A 3. If A=0 for the circuit of Fig. (a) then the output F is:

11 Experiment#2 1-Schmitt Gate Circuit 2-Open-Collector Gate Circuit OBJECTIVES 1-Understand the structure and characteristics of Schmitt gates. 2-Understanding the characteristics of open-collector gates and functions of wire- AND gates. Part#1: Schmitt Gate Circuit DISCUSSION Schmitt gate is a unique logic gate with the following characteristics: 1. It will take in random input waveforms and transform them into uniform output waveforms The Schmitt gate is triggered only after the input voltage exceeds its positive threshold voltage VTH. It will change state again when the input voltage drops below the negative threshold voltage VTL. 2. VTH must be greater than VTL. The area between VTH and VTL is called "Hysteresis". 3. Since the Schmitt gate has VTH and VTL, it's less susceptible to noise interference which affects most logic gates. The output pulses of Schmitt gate have higher speed too. Fig. 2-1 (a) is a comparison of Schmitt gate input/output waveforms. Fig. 2-1 (b) demonstrates how a Schmitt gate can be constructer using basic logic gates. R2 When Vo=0, Vs x if Vs is large enough Vi will exceed VTH. ' R1 + R2 When Vs exceeds VTH, Vo= Vcc and Vi= Vs x enough Vi will drop below VTL. R2 + R1 + R2 Vcc R1 R1 + R2, If Vs is small

12 (b) Fig. 2-1 Schmitt gate EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; DLLT-EM02: Assembled Logic Circuits (1) Experiment Module. PROCEDURES 1. Insert connection clips according to Fig. 2-2 (a). Fig. 2-2 (b) is the equivalent circuit. Fig. 2-2 (a)

13 Fig. 2-2 (b) 2. Connect input Y to the sine wave output of Signal Generator(F=1Khz). Adjust R3 to set the output F to square wave. Sketch the waveforms at point F (VF) and point A (VA) in Table 2-1. RESULTS Table The output of this circuit is high-speed pulses. 2. The input sine wave of Schmitt gates has two critical points: the Upper and Lower Trigger Point. Part#2: Open-Collector Gate Circuit DISCUSSIONS An Open-Collector gate, or O.C., is shown in Fig. 2-3 (a). The collector pole of Q3 must be open. If Y is to function, a load or resistor must be connected. The advantage of having the collector pole open are: High voltage loads can be driven directly

14 (1) Directly Driven High Voltage Loads Fig. 2-3 Refer to Fig. 2-3 (b), the gate voltage is +5V and the load RL is connected to +30V. If larger loads, such as light bulbs or relays are to be driven, simply connect an additional transistor as shown in Fig. 2-3 (c). EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; Module DLLT-EM02: Assembled Logic Circuits (1) Experiment Module; 3.Multimeter PROCEDURES (a) High Voltage/Current Circuit

15 1. Connect C to +Vcc; input A to Data Switch SW1; output F1 to Logic Indicator L1. Measure the output voltage and observe L1 at A="0" and A="1 ". Fig. 2-8 (1) When A=O, F1= V. What is the state of L1? (2) When A=1, F1= V. What is the state of L1? 2. Insert one connection clip between F1 and R1. Connect input C to the Adjustable Power Supply and set the output to its maximum value. A and F1 are still connected to SW1 and L1 respectively. Measure F1 and observe L1 at A=0 and A=1. (1) When A=O, F1= V. What is the state of L1? (2) When A=1, F1= V. What is the state of L1? 3. Remove the connection clip between F1 and R1. Insert it between F1 and R2 to use the light bulb as a load. Other connections remain the same. Observe the state of L1. (1) When A=O, What is the state of L1? (2) When A=1, what is the state of L1? (b) Constructing a Logic Gate with Open Collector Gate 1. Insert connection clips according to Fig. 2-9 (a). The equivalent circuit is shown in Fig. 2-9 (b). Connect inputs A, B to SW0, SW1; output F3 to L1. Measure F3 and observe L

16 Fig. 2-9-(b) 2. When SW0 (A) = SW1 (B) =0, F3 = V. L1 =. When SW0 (A) = SW1 (B) = 1, F3 = V.L1=. When SW0 (A) SW1 (B), F3 = V.L1 =. 3. This circuit acts as gate. RESULTS 1. The open-collector gate will be in "open" state and have no logic functions without any external resistor or load. 2. The external resistor connected to an open-collector gate can be connected to any voltage as long as it is within the limitation of the circuit. 3. If outputs of an open-collector gate are connected in parallel it will serve act as an OR gate. MULTIPLE CHOICE QUESTIONS 1. ICs marked with O.C. are: 1. Can limit high voltage

17 2. Can limit current overload 3. Open-collector gates 2. An open-collector gate without external load is in what state? 1. Floating 2. High 3. Low 3. Open-collector gates can be used to construct: 1. Wire-OR gate 2. Wire-AND gate 3. Wire-NOR gate 4. Output F of the circuit shown below is equal to: 1. A B 2. A+B 3. A x B 5. If the rated voltage for an IC and an open-collector gate are 5V and 30V respectively, what is the external load voltage? 1. At least 5V 2. At least 10V 3. Maximum 30V

18 Experiment#3 1-Tristate Gate Circuit 2- Comparator Circuit OBJECTIVE 1-Understand the characteristics and applications of tristate gates. 2-Understand the construction and operational principles of digital comparators. Part#1: Tristate Gate Circuit DISCUSSIONS Schematic and symbol of a tristate gate are shown in Fig. 3-1 (a) and (b) respectively. The structure of the tristate gate is basically the same as other logic gates, with the addition of a transistor Q5 and diodes D1, D2 for controlling the three states. The socalled "three states" are "0"; "1" and "X" for "open". When the input for Q5's control terminal C is "1", Q5 is on, Q3 is grounded through D1 and Q5 so Q3 is off. If Q3 is off, Q2 and Q1 will also be off. The output F is "floating" since there are no high or low voltages. The tristate gate will function properly when Q5 is off and C="0" because D1 and D2 can't be grounded through Q5. Q1, Q2 and Q3 will all be on and the gate will operate according to the states of inputs A and B. The output F will be either "0", or "1 ". Fig. 3-1 The additional "open" state of tristate gates makes it ideal for data transmissions. Fig. 3-2 shows a bidirectional transmission scheme with tristate gates U1 and U2. U1 triggers on "1" and U2 triggers on "0"

19 Fig. 3-2 Bidirectional data transmission When C="1", U1 transmits data from A to B and U2 is open. When C="0", U2 transmits data from B to A and U1 is open. Tristate gates also can be connected in parallel but the down side to doing this is that only one gate can be triggered at a time. Short-circuit will result if more than one gate is triggered at a time. Fig. 3-3 shows parallel-connected tristate gates acting as a multiplexer. Fig. 3-3 Multiplexer constructed with tristate gates Tristate gates are particularly useful in circuits with parallel outputs, such as memory expansion circuits and parallel control circuits. EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; DLLT-EM03: Assembled Logic Circuits (2) Experiment Module, and Digital Multimeter PROCEDURES (a) Truth Table Measurements

20 1. U5a on circuit c of Module DLLT-EM03 will be measured in this section of the experiment. Fig. 3-5 of DLLT-EM 03 s circuit c 2. Connect inputs A, E1 to Data Switches SW0, SW1.Follow input sequences in Table 3-1, measure and record the output F1 with a multimeter. Table Using a connection lead, connect F1 with T1 to construct the circuit of Fig Inputs A, E1 are still connected to SW0 and SW1. Follow the input sequences in Table 3-2, record output F1 and states of LEDs CR1, CR2. Record "1" if the LED is on and "0" if LED is off. (What happens if U6a is used instead?)

21 Fig. 3-6 (b) Table 3-2 Notes: If CR1 and CR2 both are on, output F1 is open Constructing an AND Gate with Tristate Gate 1. Construct the circuit shown in Fig. 3-7 on circuit c of Module DLLT-EM03. Fig Connect inputs A to SW0; E1 to SW1; B to SW2; E2 to SW3.Set SW1 and SW3 (E1 and E2) to "1". Follow the input sequences in Table 3-3, measure and record voltages between F1 and TP

22 Table Measure the voltage across R1 when E1 > E2 and A /B. Is there any voltage drop across R1? 2. Connect inputs E1~E4 and insert connection clips according to Fig Change the inputs randomly, observe output at F. Which input determines the output? Fig. 3-8 shown the module of DLLT-EM3 When E1="1" and E2=E3=E4="0", F=. When E2="1" and El =E3=E4="0", F=. When E3="1" and E1=E2=E4="0", F=. When E4="1" and El =E2=E3="0", F=. (c) Bidirectional Transmission Circuit 1. Insert connection clips according to Fig. 3-9 to construct the bidirectional transmission circuit shown in Fig

23 Fig. 3-9 Fig Connect F4 and F6 to Logic Indicators L1 and L2. Connect E4 (E4=E5) to SW0. Use SW1 to control the inputs. Observe L1 (F4) when SW0="1" and SW1 is connected to D. What is the response of F4 if D goes from "1 to"0" to "1 "? Observe L2 (F6) when SW0="0" and SW1 is connected to B. What is the response of F6 if B goes from "1 to "0" to "1 "? RESULTS 1. Tristate gates are very similar to open-collector gates but only one gate can be activated at a time if tristate gates are connected in parallel. 2. Tristate gates can be triggered by either "0" or "1 ". 3. Unlike the open-collector gate, the tristate gate does not need external resistor or load to operate

24 4. Tristate gates are used in complicated circuits such as memory circuits; shift register circuits; multiplexer and demultiplexer circuits. Usually they are connected in parallel and only one gate is triggered at a time. MULTIPLE CHOICE QUESTIONS 1. When tristate gates are connected in parallel, which of the following statements is true? 1. Several gates are triggered at the same time 2. Only one gate is triggered at a time 3. The number of gates triggered at the same time is not limited 3. Which of the following gates are often used with memory circuits: 1. Tristate gate 2. Open-collector gate 4. The symbol of a tristate gate is: 5. Which statement applies to the circuit shown below when C="1 "? Part#2: Comparator Circuit DISCUSSION 1. A transmit data to B 2. B transmit data to A 3. Outputs are in high impedance state At least two numbers are required to perform any comparison. The simplest form of comparator has two inputs. If the two inputs are called A and B there are three possible outputs: A>B; A=B; A<B. Fig shows the schematic and symbol of a simple comparator

25 Fig Comparators A 1-bit comparator is shown in Fig In actual applications 4-bit comparators are used most often. 4-bit comparator ICs that determine greater or less inputs include TTL 7485 and CMOS TTL is an IC that only compares whether the inputs are equal. In a 4-bit comparators, each bit represents 2 0, 2 1, 2 2, 2 3. Comparisons will start from the highest bit (23), if input A is higher than input B at the 23 bit, the "A>B" output will be in high state. If A and B are equal at the 2 3 bit, comparison will be carried out at the next highest bit 2 2. If there is still no result at this bit the process is repeated again at the next bit. At the lowest bit 2 0, if the inputs are still equal then the "A=B" output will be in high state

26 Fig EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; Module DLLT-EM02: Assembled Logic Circuits (1) Experiment PROCEDURES (a) Comparator Constructed with Basic Logic Gates 1. Insert connection clips according to Fig (a). U3a, U3b, U3c, U4a, U4b, U4c and U5 will be used to construct the 1-bit comparator shown in Fig (b). Fig bit comparator

27 2. The inputs are triggered by high state voltage. Connect inputs A and B to Data Switch SW1 and SW2. The outputs are triggered by low state voltage. Connect outputs F1, F2, F5 to Logic Indicators L1, L2. L3 respectively. 3. Follow the input sequences in Table 3-4. Measure and record the outputs. (b) Comparator Constructed with TTL IC 1. Circuit d of module DLLT-EM02 will be used in this section. U6 is a bit Comparator IC. Its pin assignment and truth table are given below. 2. Connect input A>B to SW1 and F1; A=B to SW2 and F2; A<B to SW3 and F3. Connect inputs A1~b A4 and B1~ B4 of the 7458 to the output of Thumbwheel Switches on DLLT Assuming inputs A1 ~ A4=As and B1 ~ B4=Bs and As=Bs, follow input sequences in Table 3-5 and record the outputs

28 RESULTS 4. Set SW3 to "0"; SW2 to "'I"; SW1 to "0". Observe and record the outputs under the following conditions: (1) As>Bs (2) As=Bs (3) As<Bs 5. Remove A1~ A4 and B1~ B4 from the Thumbwheel Switches and connect them to DIP Switches DIP1.0 ~ DIP1.3 and DIP2.0 ~ DIP 2.3 respectively. Repeat step 4. Are the results any different from step 4? 1. 1-bit comparator has three outputs: A>B; A=B; A<B is a 4-bit comparator. Serial inputs A>B; A=B; A<B are the results of low bit comparisons. Serial inputs have no effect unless the high bits are equal. MULTIPLE CHOICE QUESTIONS 1. How many inputs does a 1-bit comparator have? The maximum number of output states a 1-bit comparator could have is: The maximum number of output states a 4-bit comparator could have is: The 7485 is a: bit comparator bit comparator bit comparator 5. If the result of comparison at the highest bit of a 4-bit comparator has one input greater than all other inputs, which output will be in high state? 1. > 2. < 3. Depends on comparisons at lower bits 6. Under which condition will a comparator have a = output? 1. The largest bit is equal 2. The smallest bit is equal 3. All bits

29 Experiment#4 1-Half-Adder and Full-Adder Circuit 2-Half-Subtractor and Full-Subtractor Circuit OBJECTIVES 1-Understand the characteristics of half-adder and full-adder in the arithmetic unit. 2-Understand the theory of complements and construction of subtractor circuits. Part#1: Half-Adder and Full-Adder Circuit DISCUSSIONS Adders can be divided into "Half-Adder" (HA) and "Full-Adder" (FA). Half-adders follow the rules of binary addition and consider only the addition of 1 bit. The result of addition is a "carry" and a "sum". In binary additions, a "carry" is generated when the sum of two numbers are greater than 1. Refer to the half-adder addition below: When "1" and "1" are added the sum is 0 and the carry is 1. The half-adder is limited to the addition of 1-bit numbers. The full-adder can perform additions of numbers greater than 2-bits in length. Refer to 4-1 (a) and (b) shows half-adder and full-adder circuits and symbols respectively

30 To perform additions of numbers greater than 2-bits in length, the connection shown in Fig. 4-2, or "Parallel Input" should be used to generate sums simultaneously. However, the sum of the next adder will be stable only after the previous adder's carry has stabilized. For example, in Fig. 4-2, the sum of FA2 will not be stable unless the carry of FA1 is stable. Fig. 4-2 When FA1 adds A1 and B1, a sum S1 and a carry C1 is generated. C1 will be added to A2 and B2 by FA2, generating another sum S2 and another carry C2. In the case of Fig. 4-2, sum of the four adders do not stabilize at the same time, delaying the adding process. This delay can be eliminated by using the "Look-Ahead" adder. Binary adders can be converted into BCD adders. Since BCD has 4 bits with the largest number being 9; and the largest 4 bit binary number is equivalent to 15, there is a difference of 6 between the binary and the BCD adder. Under the following conditions 6 must be added when binary adders are used to add BCD codes: 1. When there is any carry 2. When the sum is larger than 9 If the order of priority is S8, S4, S2, S1 and the sum is larger than 9 then S8 x S4+S8u x S2. If any carry is involved, assuming the carry is CY, under this term, 6 must be added: CY+S8xS4+S8xS2 Fig. 4-4 is the circuit of a BCD adder

31 Fig. 4-4 EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer, Module of DLLT-EM03: Assembled Logic Circuits (2) Experiment / Module of DLLT-EM04: Assembled Logic Circuits (3) Experiment PROCEDURES (a) Constructing HA with Basic Logic Gates 1. Insert connection clips according to Fig. 4-5, using U2a and U3a to assemble the half-adder circuit of Fig Connect Vcc to +5V. Fig

32 2. Connect inputs A and B to Data Switches SW0 and SW1.Connect outputs F1 and F2 to Logic Indicator L1 and L2. Follow the input sequences for A and B in Table 4-1 and record the output states. Determine which output is the sum and which is the carry Fig. 4-6 Table Reassemble the circuit according to Fig. 4-7 (a) to construct the full-adder circuit shown in Fig. 4-7 (b). Connect A, B, C to SW1, SW2 and SW3. A and B are augends while C is the previous carry. Connect F3 to L1, F5 to L2. Follow the input sequences in Table 4-2 and record output states. Determine which output is the sum and which is the carry. Table

33 (b) Full-Adder Circuit with IC 1. U5 on circuit b of module DLLT-EM04 is used as a 4-bit adder. Connect input Y5 to "0", so the XOR gates U6a-U6d, which are connected to Y0 ~Y3, will act as buffers. Connect inputs X0 ~ X3 (addends), Y0 ~ Y3 (augends) to DIP Switches DIP2.0 ~ 2.3 and DIP1.0 ~ 1.3 respectively. Connect F1, Σ0, Σ 1, Σ 2, Σ 3 to L1 ~ L5. Follow input sequences in Table 4-3, record F1 and Σ in hexadecimal numbers.(note: connect cin to ground) (X and Y can also be connected to the Thumbwheel Switches) X=X3X2X1 X0 Y=Y3Y2Y1 Y0 Σ= Σ 3 Σ2 Σ1 Σ0-33 -

34 (d) BCD Code Adder Circuit 1. The circuit shown in Fig will act as a BCD code adder

35 2. Connect input X0~ X3 to DIP1.0 ~ 1.3; Y0~ Y3 to DIP2.0 ~ 2.3: Y5 to 0. Fig is the equivalent circuit. Fig 4-11 U5 and U9 are 7483 look-ahead 4-bit BCD adders, connect outputs F8 ~ F11 of U5 the inputs of one of the 7-Segment Digital Display. F8 ~ F11 should also be connected to L1 ~ L4. Connect F1, F2 to Logic Indicators L5, L

36 Connect outputs F4 ~ F7 of U9 to another 7-segment display. Also connect F4 ~ F7 to L7 ~ L10 and F3 to L F11-F8 are the sum of X0 ~ X3 added to Y0 ~ Y3 while F1 is the carry. Follow the input sequences for X0 ~ X3 and Y0 ~ Y3 in Table 4-5 and record the output states. Table Connect inputs X0 ~ X3, Y0 ~ Y3 to the Thumbwheel Switches and outputs F7 ~ F4 to the 7-segment digital display. Adjust the inputs randomly and observe the outputs. RESULTS 1. Adders can be further classified into "half-adder" and "full-adder". 2. Binary adders can be converted into BCD code adder. MULTIPLE CHOICE QUESTIONS 1. What can be constructed with one XOR and one AND gate? 1. Full-subtractor 2. Half-adder 3. Full-adder

37 2. What is the correct compensation when binary adding is converted to BCD code adding? 1. Add6 2. Subtract 6 3. Subtract 9 3. What are the final sum (S) and carry (C) for a F.A. if both inputs A and B are equal to 1 and the previous carry is "1"? 1. C=1, S=1 2. C=0, S=1 3. C=1, S=0 4. Which of the following statements is true for BCD adding? 1. It can't be done using binary adding operation 2. It can be done using binary adding operation but has to be compensated 3. A new decimal adder circuit has to be designed Part#2: Half-Subtractor and Full-Subtractor Circuit DISCUSSION Half-subtractor and full-subtractor circuits can be built by referring to the truth tables and the Boolean expressions, or Karnaugh's map of logic gates. In this experiment we will use the theory of complement to assemble full and half subtractor circuits. Binary subtractions are usually performed by 2's complement. Two steps are required to obtain 2's complement. First, the subtrahend is inverted to its 1's complement, i.e. an "1" to a "0" and a "0" to an "1". Secondly, an "1" is added to the least significant digit of the subtrahend in 1's complement. In general subtraction the subtrahend is directly subtracted from the minuend but in 2's complement, the two numbers are added. Hence an adder also can be used as a subtractor. EXAMPLE: What is the equivalent in 2's complement for the decimal subtraction of 11-10?

38 A carry of 1 is generated in the 2 s complement subtraction. A half-subtractor execute its task of subtraction 1-bit at a time regardless of whether the minuend is greater or less than the subtrahend. The true table and logic diagram of a half-sub tractor is shown in Fig "Borrow" from previous subtraction are not taken into consideration. Fig. 4-12Half- subtractor Compare the logic diagrams of half-subtractor with half-adder and we can see that the only difference is the inverter at the input of the half-subtractor. This inverter gate represent the borrow. The full-subtractor has to consider borrow(s) from previous stages. Its truth table and logic diagram are shown in Figure When C = "0" it is equivalent to a halfsubtractor. Previous borrow Minuend Subtrahend Difference Borrow

39 Fig.4-13 Full-subtractor From a 4-bit adder circuit we can assemble subtractor circuits of 4-bit or longer. Fig. 5-3shows a dual-purpose adder/ subtractor circuit. When Bn-1="0" additions are performed and all XOR gates act as buffers. When Bn-1="1" subtractions will be performed and all XOR gates act as NOT gates. Y inputs uses 1's complement and adds an "1" from Cin. The outputs are Cn (carry) and Bn (borrow), Cn and Bn are dependent on Bn-1. EQUIPMENTS REQUIRED Fig DLLT-1300 Digital Logic Lab Trainer, DLLT-EM04: Assembled Logic Circuits (3) Experiment Module PROCEDURES (a) Subtractor Circuit Constructed with Basic Logic Gates 1. Insert connection clips according to Fig Connect inputs A ~ C to Data Switches SW0 ~ SW2; outputs F2 to Logic Indicator L1; F1 to L2; F3 to L3; F5 to L4. When C=0 the circuit is a halfsubtractor. F1 is the borrow output; F2 is the difference and F5=F2; F4=0; F3=F

40 When C=1 the circuit is a full-subtractor. F3 is the borrow output and F5 is the difference output. Fig Half-adder/Full-adder 3. Follow the input sequences in Table 4-6and record output states. Table 4-6 (b) Full-Adder and Inverter Circuit 1. The circuit of Module DLLT-EM04 circuit b (Fig. 4-16) is equivalent to the adder/ subtractor circuit of Fig

41 Fig Adder/subtractor 2. Connect inputs X3 ~ X0 to DIP Switch 1.3 ~ 1.0; Y3 ~ Y0 to DIP 2.3 ~ DIP2.0; Y5 to SW0. Connect outputs F1 to L1; F11 ~ F8 to L5 ~ L2. To execute the subtract operation, connect Y5 to "1" (or Cin of U5=1). Follow the input sequences below and record the output states in Table 4-7. Table

42 RESULTS 1. A half-subtractor is a half-adder with reversed minuend input. 2. A full-subtractor is a full-adder with reversed minuend input. 3. IC adder uses the "2's complement" method. MULTIPLE CHOICE QUESTIONS 1. Half-subtractor is simply a half-adder with: 1. INVERTER gate 2. AND gate 3. XOR gate 2. What is binary 1101 in 1's complement? Which method of complement should be used so that the result of "A-B" = "A+B" 1. 1's complement 2. 2's complement 3. 3's complement 4. What is binary 1110 in 2's complement? If a half-adder circuit is to be used as a half-subtractor circuit, A is the minuend and B is the subtrahend, which of the following statements is true? 6. The inputs of a full-subtractor include: 1. A must be reversed 2. B must be reversed 3. No modification required 1. borrow, minuend 2. subtrahend, borrow 3. Minuend, subtrahend, borrow 7. To convert a full-adder into a full-subtractor, which of these logic gates is required? 1. AND gate 2. OR gate 3. XOR gate

43 Experiment#5 1-Decoder Circuit 2-Multiplexer Circuit OBJECTIVES a-understand the operating principles of decoder circuits. b-understand the operating principles and construction of multiplexers. Part#1: Decoder Circuit DISCUSSION A decoder is a logic circuit that will detect the presence of a specific binary number or word. The input to the decoder is a parallel binary number and the output is a binary signal that indicates the presence or absence of that specific number. The AND gate can be used as a basic decoder circuit, since the AND gates s output will be a binary 1 only when all inputs are binary 1. Proper connections of AND gate's inputs to the data will ensure detection of any binary number. Binary-to-Octal Decoder A binary-to-octal decoder is shown in Fig There are 3 binary inputs A, B, C and 8 octal outputs Q0~Q7. If CBA= 010 output Q2= 1. When CBA= 111 output Q7= 1. EQUIPMENTS REQUIRED Fig

44 DLLT-1300 Digital Logic Lab Trainer; Module DLLT-EM04: Assembled Logic Circuits (3) Experiment / DLLT-EM05: Assembled Logic Circuits (4) Experiment Module; Multimeter PROCEDURES (a) Constructing a 2-to-4 Decoder with Basic Gates 1. Circuit c of module DLLT-EM05 will be used in this section of the experiment. Connect Vcc to +5V. Fig Connect inputs A, B to Data Switches SW0 and SW1. Connect outputs F1-F4 to Logic Indicators L0 ~ L3 respectively. 3. Follow the input sequences for A and B in Table 5-1 and record output states. Table 5-1 (b) Constructing a 4 to 10 Decoder with TTL IC 1 U10 (7442) on block c of module DLLT-EM04 will be used in this section of the experiment is a BCD-to-Decimal decoder IC

45 Fig Connect inputs A1, B1, C1, D1 to the BCD outputs "1", "2", "4", "8" of one of the Thumbwheel Switches respectively. Connect outputs 0-9 to Logic Indicator L0 ~ L9. The thumbwheel switch is a mechanical device that converts numbers to BCD codes. 3. Adjust the Thumbwheel Switches according to Table 5-2, measure voltages at A, B, C, D with a multimeter. Presence of voltage at the inputs indicates high logic state or "'I", absence of voltage indicates low logic state or "0". Observe the output states at L0 ~ L9. Record input and output logic states in Table 5-2. Table 5-2 (c) BCD-to-7-Segment Decoder

46 Fig Connect inputs A, B, C, D of U5 (7448) on circuit b of module DLLT-EM05 to Data Switches SW3, SW2, SW1, SW0 respectively. The 7448 is a BCD-to-7- segment decoder. Connect "LT" to DIP1.0. Set DIP 1.0 to "HIGH". 2. Follow the input sequences for D, C, B, A in Table 5-3 and record outputs of the 7-segment display. 3. Set DIP1.0 to "LOW" while DIP1.0. Repeat step 2. Are the outputs any different from step 2? 4. What is function of LT pin???. Table

47 RESULTS 1. Decoder has the exact opposite functions of the encoder. 2. Two of the most direct applications of decoders are with numbers and words. 3. The 7442 is a 3 line-to-8 line decoder if D=0. MULTIPLE CHOICE QUESTIONS 1. What has 4 input lines and 16 output lines? 1. Decoder 2. Encoder segment display 2. What is the equivalent in 5421 code for binary 8421 code "1010"? 1. "1101" 2. "1010" 3. "1110" 3. What purpose does the series of resistors in front of a display serve? 1. Matching 2. To limit the current 3. To increase the brightness 4. Which of the following statements is true? 1. There are only Common Cathode displays 2. There are only Common Anode displays 3. There are Common Cathode and Common Anode displays 5. What is the output when decimal numbers are converted into BCD switch and 6 is pressed? Part#2: Multiplexer Circuit DISCUSSION Multiplexer, or MUX, is a logic circuit that select and route any number of inputs to a single output. One of the multiple inputs are selected by the selector gate and routed to the single output. The number of selector gates determines the capacity of a multiplexer. For example, if a certain MUX has only one selector gate, it is referred to as a "2 line-to-1 line MUX" because one selector can only select from two inputs. A MUX with 3 selector gates is called "8 line-to-1 line MUX", since 3 selectors are capable of selecting an output from 8 inputs (2³=8). MUX is also referred to as "Data Selector" because it selects one output from among many inputs. Function expression, such as F (CBA) =Σ (0, 1, 2, 6, 7), can be easily executed on MUX. The function "F" generates the sum of products (CB+CB) from states 0, 1, 2, 6, 7. Refer to the 4 line-to-1 line MUX below, the output is determined by states of selectors A, Band C. When CBA=000, 001, 010, 110, 111 the output F is 1. In all other states F=

48 EQUIPMENTS REQUIRED DLTT-1300 Digital Logic Lab Trainer, Module DLLT-EM06: Assembled Logic Circuits (5) Experiment PROCEDURES a) Constructing a 2-to-1 Multiplexer 1. Circuit e of module DLLT-EM06 will be used as a 2-to-1 MUX. Fig Connect inputs A, B to Data Switches SW0, SW1; selector C to SW2. Connect output F3 to Logic Indicator L0. 3. Follow the input sequences in Table 5-4and record states of F3. Which input (A or B) determines the output? Table 5-4 (b) Constructing a 8 to 1 Multiplexer Circuit with TTL IC 1. U6 (74151) on circuit f of module DLLT-EM06 will be used in section of the experiment

49 Fig Refer to the data book for specifications of the When CBA = "000", data at D0 is send to output F. When CBA = "010", data at D2 is send to output F. When CBA = "111 ", data at D7 is send to output F. The IC will function properly only when STROBE = "0". Y will remain "0" when STROBE ="'I". 3. Connect inputs D0 ~ D7 to DIP Switch 1.0 ~ 1.7; inputs C, B, A to DATA Switches SW2, SW1, SW0. Follow the input sequences in Table 5-5, adjust D0 ~ D7 and record output states. Determine on which input among D0 ~ D7 does F depend on. Table 5-5 (c) Using Multiplexers to Create Functions 1. Circuit f of module DLLT-EM06 will be used in this section of the experiment to create functions

50 Fig. 5-6 shown circuit f of DLLT-EM06 2. Use U6 (74151) to create this function: F (D, C, B, A) = ( 0,2,4,5,7,8,10,11,15) Place connection leads according to Fig. 5-6 to complete the function shown above. Since D, C, B, A has 16 possible variations and the has only 8 variations, D will be used as the data input. 3. Connect inputs D, C, B, A to Data Switches SW3, SW2, SW1, SW0 respectively. Connect output Y to Logic Indicator L0. Follow the input sequences below and record output states. RESULTS 1. MUX circuits has multiple inputs but only one input is selected at a time

51 2. The execution of Boolean functions will be much simpler if standard MSI multiplexer devices are used. The need for SSI gates connection is also eliminated, reducing the number of ICs required as well as power consumption. 3. TTL multiplexer ICs includes: 7497, 74167, 74164, 74153, 74157, 74151, 74152, EXERCISES 1. Use the to create this function shown below: F (D, C, B, A) = Σ (1, 2, 4, 8, 13, 14) MULTIPLE CHOICE QUESTIONS 1. How many inputs does a 4-line to 1-line MUX have? How many selectors does a 4-line to 1-line MUX have? Which MUX is created when five 4-line to 1-line MUXs are connected? line to 1-line line to 1-line line to 1-line 4. Which one of the following devices is also referred to as "Data Selector"? 1. Demultiplexer 2. Multiplexer 3. Encoder

52 Experiment#6 1- Encoder Circuit 2- Demultiplexer Circuit OBJECTIVES a-understand the operating principles of encoder circuits. b-understand the operating principles and construction of demultiplexer circuits. Part#1:Encoder Circuit DISCUSSION An encoder is a combinational logic gates that accept one or multiple inputs and generates a specific output code. Only one input is triggered at a time. An encoder with n-bit inputs and n-bit outputs is shown in Fig When one of the inputs is triggered there will be a n-bit output code at the outputs. Octal to Binary Encoder Fig. 6-1 An octal to binary encoder is shown in Fig There are 8 octal inputs A1~A7 (0~7); and three binary outputs Q0, Q1, Q2 (000 ~ 111). If input A0="0" the corresponding output Q2Q1Q0 is equal to "000". Fig. 6-2 Octal -Binary encoder

53 Actually, A0 is not connected to the gate input. If A1="1" then Q2Q1Q0=001. When A2="1" the output Q2Q1Q0=010. There can't be more than one "1" among the inputs. For example, if A2="1" and A3="1" simultaneously, Q2Q1Q0=011. If A3, A4 both are "1" at the same time, Q2Q1Q0=111. Both outputs are incorrect. Matrix Encoder If no commercially available encoders fits the require specification, one could be built by using diodes. Fig. 6-3 shows a simple matrix encoder build with diodes. Fig. 6-3 Matrix encoder Only one of X0~X4 will be triggered at a time. When X0="1", Y3Y2Y1Y0="1011" When X1="1 ", Y3Y2Y1 Y0="0110". In digital circuits sometimes it is critical to process various input signals in order of priority. One particular type of encoder called "Priority Encoder", which process inputs in order of priority should be used in such circuits. When an input gate with higher priority is triggered, the output will correspond to this high priority input regardless of the states of lower priority inputs are in. The is a 9-1 priority BCD output encoder, the input priority runs in ascending order, gate 1 has the lowest and gate 9 has the highest priority. The outputs are in BCD codes. Table 6-1 is the truth table for the to-4 priority encoder

54 The is triggered by the low logic state. When inputs 1 ~ 9 are all in high state, output DCBA="HHHH". When input 2 and 5 are triggered simultaneously the output is determined by input 5, which has higher priority than input 2. When inputs 2, 5 and 7 are triggered together, input 7 will determine the output. EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; Modules DLLT-EM05: Assembled Logic Circuits (4) Experiment, Module DLLT-EM06: Assembled Logic Circuits (5) Experiment PROCEDURES (a) Constructing a 4-to-2 Encoder with Basic Gates 1. Insert connection clips according to Fig Connect Vcc to +5V. Fig Connect inputs A-D to Data Switches SW0 ~ SW3 respectively; outputs F8 and F9 to Logic Indicator L0 and L1. 4. Follow the input sequences for D, C, B, A in Table 6-2 and record the output states

55 Table Remove the connection clip between A and A1; insert it between A1 and F1 as shown in Fig All other connections remain the same. Follow the input sequences in Table 6-3 and record output states. Fig

56 Table Compare the outputs states in Table 6-2 and 6-3. What is the difference between them? (b) Constructing a 10-to-4 Encoder with TTL IC (c) 1. The (U7) on circuit a of module DLLT-EM06 is used in this section of the experiment. Connect Vcc to +5V. Fig Connect inputs A0 ~ A8 to DIP Switches 1.0 ~ 1.7, A9 to 2.0. Connect outputs F1 ~ F4 to Logic indicators L1 ~ L4. Follow the input sequences given in Table 6-4 and record output states

57 Table 6-4 RESULTS 1. Encoders have more input gates than output gates. 2. Output codes of encoders can only be read by professionals. 3. The output of encoders should be decoded by decoders. MULTIPLE CHOICE QUESTIONS 1. The correct number of outputs for a 16-to-2 encoder is: The correct number of outputs for a decimal-to-binary decoder is: How many X states does a decimal-to-binary encoder have on its Karnaugh's map? (X=don't care) Which statement is true for a priority encoder that has two inputs triggered at the same time?

58 priority 1. The output will be incorrect 2. The output is determined by the input with higher 3. The output will remain correct Part#2: Demultiplexer Circuit DISCUSSION A demultiplexer, or DMUX, is basically a logic circuit that is exact opposite of a multiplexer. DMUX has a single input and multiple outputs. The input can be connected to any one of the many outputs through the selector terminal. The DMUX is also referred to as "Data Distributor" or "Data Router". Its pin assignment diagram is shown in Fig. 6-7 (a). Input Fig. 6-7 When all three selector terminals A, B and C are in low logic state (CBA=000), data at input D is send to output number 0. When CBA=010, the input is send to output number 2. Collective state of selectors determines the location of output data. When CBA=111, data is send to the last output (output number 7). By combining MUX and DMUX, long distance transmission systems can be set up, increasing the efficiency of transmission lines. Fig. 6-7(b) shows a MUV-DMUX combinational circuit with 16 inputs, 16 outputs and 4 selectors. EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer, Module DLLT-EM06: Assembled Logic Circuits (5) Experiment PROCEDURES (a) Constructing a 2-output Demultiplexer with Basic Logic Gates 1. Insert connection clip according to Fig Connect A to Data Switch SW0; C to

59 SW3; F1 and F2 to Logic Indicators L0 and L1 respectively. Fig Set C to "0" and change data at input A. Observe how F1 and F2 changes. Set C to "1 ", change A and observe how F1 and F2 react to changes of A. (b) Constructing a 8-output Demultiplexer with CMOS IC 1. U2 (4051) on circuit e of module DLLT-EM06 is used in this section of the experiment. Fig Connect E to DIP1.0; D to DIP1.1; A to SW0; B to SW1; C to SW2; outputs Y0 ~ Y7 to Logic Indicators L0 ~ L7 respectively. 3. At D=0, apply the input sequence to the Common Input E and observe outputs Y0 ~ Y7. Did the outputs change as the input sequence is applied?

60 At D=1, apply the input sequence to the Common Input E and observe outputs Y0 ~ Y7. Did the outputs change as the input sequence is applied? Which state of D changes the outputs? Using the same sequence for E ( ), follow the sequence for A, B and C given in Table 6-5(a). Record output states. Table 6-5 (a) 4. Reconstruct the circuit by removing the connections done in step 2. Connect Y0 ~ Y7 to DIP1.0 ~ 1.7; E to L0; D to SW3; C to SW2; B to SW1; A to SW0. Change the state of Y0 ~ Y7 from 1 to 0 to 1 (1-0-1) and observe E. Did E follow changes to Y0 ~ Y7? Follow the input sequence for C, B, A in Table 6-5 (b) and observe the relationship between E and Y0 ~ Y7. Is Table 6-5 (b) correct? RESULTS Table 6-5 (b) Does the relationship between E and Y0-Y7 in Table 6-5(b) still apply when D changes state? 1. Depending on the selector terminals (decoders), MUX and DMUX will either select or distribute input data and are two TTL demultiplexer ICs

61 Experiment #7 Flip-Flops Circuits OBJECTIVE Study the differences between combinational and sequential logic circuits; and the applications of various memory units. DISCUSSIONS Two NOT, or INVERTER gate ICs are shown in Fig. 7-1, output of IC2 is connected to IC1's input. Assuming IC1's output is "1", IC2's output will be "0". Because IC2's output is connected to IC1's input, IC1's input will be inverted to "1" again. If an external pulse is connected to IC1's input, output of IC1 will be "0" while IC2's output is "1" (output of IC1 goes back to "0"). Fig. 7-1 If the external pulse is designated as A, and IC2's output as B, when either A or B is "1", output of IC1 is "0". If the NOT gates of Fig. 7-1 are replaced by two NOR gates and the two inputs are designated as R and S, a R-S flip-flop Fig. 7-2 is created. See Fig R = Reset, output Q is reset to binary 0 S = Set, output Q is set to binary 1 Fig. 7-2 Output of IC1 is called Q (normal output) while IC2's output is called Q (complement output). A flip-flop will change its logic state when an appropriate logic input is applied. It will remain in the stable state as long as power is supplied or until the input changes

62 In most cases, flip-flops are constructed with NOR or NAND gates. Fig. 7-3 shows a neither positive logic NOR R-S flip-flop. Fig. 7-3 is a negative logic NAND R-S flipflop. The R-S flip-flop is the simplest form of flip-flop and can be used to construct other flip-flops, hence a R- S flip-flop is also called "basic flip-flop". Table 7-1 is the truth table of a R-S flip-flop. On is the current output state while Qn+1 is the next output state. Table 7-1 R-S flip-flop truth table The following characteristics of R-S flip-flop can be observed from the truth table: (1) when R=0 and S=0, Qn+1=Qn so Qn+1 is equal to the previous Qn, which could be either "0" or"1". (2) when R=0 and S=1, the flip-flop is set to binary "1" so Qn+1="1". (3) when R=1 and S=0, the flip-flop is reset to binary "0" so Qn+1="0". (4) when R=1 and S=1, Qn+1 could be either "0" or "1" simultaneously. Since the output can t possibly exist in two states at the same time, Qn+1 is "undefined" or in "limbo" state when R=S=1. Fig. 7-5 shows the complete symbol of a R-S flip-flop. CK is the clock signal, the flip-flop will change state after the presence of CK is detected. PR = Preset; regardless of CK, PR will set output Q to "1" CL = Clear; regardless of CK, CL will set output Q to "0". Fig. 7-5 R-S flip-flop

63 A D flip-flop can be constructed using a R-S flip-flop. Refer to the symbol of D flipflop and the schematics of D flip-flop constructed with R-S flip-flop in Fig. 7-6 (a) and (b) respectively. (a) (b) Fig. 7-6 D flip-flop D flip-flop are used mostly for data transmission. Table 7-2 is its truth table. Table 7-2 D flip-flop truth table A T flip-flop can be constructed using a D flip-flop. Refer to the symbol of D flipflop, and the schematic of a T flip-flop constructed with D flip-flop in Fig. 7-7 (a) and (b) respectively. Table 7-3 is the truth table for T flip-flop. (a) (b) Table 7-3 Fig. 7-7 T flip-flop From Table 7-3, we can see that T flip-flop change its output state only when T=1 and CK=1. Assuming Qn="0" initially, at T=1 and CK=1, output of the T flip-flop will become binary "1 ". Output of the flip-flop will remain binary "1" until T=1, CK=1 again, at that point the output will return to binary "0". Output of T flip-flop output alternates between binary "0" and "1" when T=1, CK=1. This unique characteristic of the T flip-flop means that "divide-by-2" circuits can be constructed with T flip-flop. Refer to the waveforms in Fig. 7-8, there are two input waveforms but only one output waveform. T flip-flops are usually used in the delay circuits of counters

64 Fig. 7-8 The J-K flip-flop can eliminate the "undefined" state of R-S flip-flop. Symbol of a J- K flip-flop is shown in Fig Fig. 7-9 Fig Fig shows an equivalent J-K flip-flop constructed with R-S flip-flop. Refer to the truth table (Table 7-4). The J-K flip-flop is the same as the R-S flip-flop except at J=1, K=1 and CK=1 when the J-K flip-flop is similar to a T flip-flop. Table 7-4 J-K flip-flop truth table Since the J-K flip-flop has no undefined state and can be used to construct just about any flip-flop, it is also referred to as an "universal flip-flop". EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; Module DLLT-EM08: Sequential Logic Circuits (1) Experiment PROCEDURES 7-1-a: Constructing a R-S Flip-Flop with Basic Logic Gates

65 1. Connect inputs A3, A4 to Pulser Switches SWA A (TTL), SWB B (TTL) output. Connect outputs F6 and F7 to Logic Indicators L1, L2. What are the states of F6 and F7? Turn the power off for a few seconds and turn it back on. What are the states of F6 and F7 now? Fig Follow the input sequences in Table 7-5. Observe and record F6, F

66 Table Determine the Q and Q output, the R and S input. (Set Pulser Switch to "1" first, then "0" and "1" again) 4. Insert connection clips according to Fig to construct the circuit of Fig Connect inputs A1, A2 to Pulser Switches SWA A, SWB B output. Fig Follow the input sequences in Table 7-6. Observe and record F6, F7. Table b: Constructing a D Flip-Flop with R-S Flip-Flop 1. Insert connection clips according to Fig to construct the D flip-flop circuit Fig

67 2. Connect A1 to SW1; CK2 to SWA A output and F6 to L1. 3. Follow the input sequences in Table 7-7. Observe and record the output states. CK A1 F6 Table c: Constructing a T Flip-Flop with D Flip-Flop

68 1. Insert connection clips according to Fig to construct the T flip-flop circuit of Fig Connect CK2 to SWB B output; A1 to SW0; A5 to SW1; F6 to L1. Fig Follow the input sequences in Table 7-8. Observe and record output states. Table d: Constructing a J-K Flip-Flop with R-S Flip-Flop

69 1. Insert connection clips according to Fig to construct the J-K flip-flop circuit of Fig Connect CK1 to SWA A output; J to SW0; K to SW1; F1, F2, F6, F7 to L0, L1, L2, L3 respectively. Fig Follow the input sequences in Table 7-9. Observe and record the output states. Table

70 MULTIPLE CHOOICE QUESTIONS 1. If a logic circuit does not contain any feedback loops, and the output is wholly dependent on the input, it is called a: 1. Combinational logic circuit 2. Sequential logic circuit 3. Delay logic circuit 2. How many bits of data can a single flip-flop store? Which of these logic circuits has "memory" function? 1. Flip-flop 2. OR gate 3. NOR gate 4. Which flip-flop has "divide-by-2" function? 1. R-S flip-flop 2. D flip-flop 3. T flip-flop 5. Identify the flip-flop symbol shown in Fig. H-1. It is a: 1. D flip-flop 2. R-S flip-flop 3. T flip-flop Fig. H-1 6. If R=1, S=1 for a R-S flip-flop constructed with NOR gates, what are the outputs? 1. Q=1, Q =0 2. Q=O, Q =1 3. Q=O, Q =0-70 -

71 7. If inputs J, K of a J-K flip-flop are connected together, it is equivalent to a: 1. R-S flip-flop 2. D flip-flop 3. T flip-flop 8. If T="0" for a T flip-flop, what is the output Q CK= "1? 1. Same as the previous Q 2. Complement of previous Q Determine the flip-flop circuit shown in Fig. H-3. It is an equivalent of: 1. T flip-flop 2. J-K flip-flop 3. R-Ss flip-flop Fig. H If CK=2 KHz for the circuit of Fig. H-3, what is F0? 1. 4 KHz 2. 1 KHz 3. 2 KHz

72 Experiment #8 1-Shift Register 2-Counters. OBJECTIVES 1-Study the principles of shift registers. 2-Study the principles of counters and how to construct counters with J-K flip-flops. Part#1:Shift Register a-constructing a Shift Register with D Flip-Flop PROCEDURES: 1. Circuit c of module DLLT-EM08 will be used for this section of this experiment. Fig Connect B (clear) to SW0; A (I/P) to SW1; CK to SWA Q output; F1, F2, F3, F4 to L1, L2, L3, L4 respectively. 3. Set SW0 to "0" to clear B, then set SW0 to "1 ". 4. Follow the input sequence for A (I/P) below: (1) at A="1", send in a CK signal from SWA (2) at A="0", send in a CK signal from SWA (3) at A="0", send in a CK signal from SWA (4) at A="1 ", send in a CK signal from SWA Observe the output displays after four CK are added

73 Does it correspond with the input sequence? This is the Serial-In Parallel- Out connection. Observe output display of F1. Does it correspond with the first I/P input? Send in another CK and observe F1 again. Does it correspond with the second I/P input? This is the Serial-In Serial-Out connection. b- Preset Left/Right Shift Register PROCEDURES: 1. Circuit b of module DLLT-EM08 will be used for this section of the experiment. Fig Complete the following connections: Inputs A, B, C, D to SW0, SW1, SW2, SW3 Outputs F1, F2, F3, F4 to L0, L1, L2, L3 D1 (LOAD) to SWA A output C1 (CK) to SWB B output B1 (I/P) to DIP2.0 A1 (MODE) to DIP2.1 Table

74 3. Follow the input sequences for A1 in Table 8-2. Observe and record the outputs. Table Set A1 to "1" and follow the input sequences for D, C, B, A in Table 8-3. Observe and record the outputs. Table 8-3 Part#2:Counters. DISCUSSION Counters are constructed with flip-flops and basic logic gates. From the previous experiment, we found that the T flip-flop alternates its output state between binary "0" and "1" when its inputs T=1 and CK=1. Fig

75 Refer to Fig. 8-3 where three T flip-flops are connected in series. The Q outputs of the flip-flop in front are used as the CK input for each succeeding flip-flop. Assuming the number of flip-flops connected in series is "n" and there are "n" inputs, the output of the last flip-flop will be n/2 n. The output waveforms are shown in Fig Fig. 8-4 We can see from Fig. 8-4 that the normal outputs A, B, C are counting "up" while the complement outputs A, B, and C are counting "down" so CK is triggered at the negative edge. A has twice the cycle and half the frequency of CK. B has twice the cycle and half the frequency of A. C has twice the cycle and half the frequency of B. If CK is triggered at the positive edge, the output waveforms are as shown in Fig Clearly A, B and C are counting up. The circuit of Fig. 8-3 will count "up" when CK is connected to Q. When CK is connected to Q, the circuit will count "down"

76 Fig. 8-5 The J-K flip-flop is an universal flip-flop that will be used in this experiment to construct basic counters. The circuit of Fig. 8-6 is an up/down counter constructed with J-K flip-flops connected in series. Fig. 8-6 When M=0, CK connects to Q and the circuit will count "UP". When M=1, CK connects to Q and the circuit will count "DOWN"

77 Serial connections, such as Fig. 8-6, are referred to as "Asynchronous Counting". a: Asynchronous Binary Up-Counter 1. Insert connection clips according to Fig. 8-7 to construct the circuit of Fig.8-8. Fig. 8-7 Fig

78 2. Connect A2 (Clear) to SW0; A1 to +SV; outputs F1, F3, F5, F7 to L1-L4 respectively and B1 (CK) to the Clock Generator, adjust the output frequency to 1 KHz. 3. Set SW0 to "1" initially to clear the output; then set SW0 to "0" to begin counting. Measure CK and the outputs with the oscilloscope, record the outputs in Fig b:asynchronous Binary Down-Counter Fig Insert connection clips according to Fig to construct the circuit of Fig

79 Fig Connect A2 (Clear) to SW0=5V; A1 to +5V; B1 (CK) to 1 KHz output of the Clock Generator. Connect F2, F4, F6, F8 to L5-L8. Measure the outputs with an oscilloscope. Sketch the output waveforms in Fig Fig c: Synchronous Binary Up/Down Counter 1. Insert connection clips according to Fig to construct the circuit of Fig

80 Fig Connect A2 (Clear) to SW1; A1 to SW2; B1 to 1 KHz output of the Clock Generator. (A) At A1="1", measure waveforms at CK, F1, F3, F5, F7 with an oscilloscope. Sketch the output waveforms in Fig Fig

81 (B) At A1="0", measure waveforms at CK, F1, F3, F5, F7 with an oscilloscope. Sketch the output waveforms in Fig d: Presetable Binary Up/Down Counter Fig U1 (74193) on module DLLT-EM10 circuit a will be used in this section of the experiment. Table 8-4 is the truth table for the Table truth table 2. Connect C6 (Load) to SW0; C5 (Clear) to SW1; D3 ~ D6 to DIP1.0 ~ DIP1.3; F1 ~ F4 (QA-QD) to L1 ~ L4; F5 (CY) to L5; F6 (BW) to L6. Also connect F1 ~ F4 to one of the 7-segment digital display

82 3. (A) "UP" mode: connect B3 (DN) to Ill";C5 (Clear) to "0" and set SW1(C6) to I. Adjust the output of Clock Gen. to 1Hz and connect to A3 (UP).Observe and record outputs of digital display in Table8-5. II. Table 8-5 Connect A3 (UP) to 1 KHz, measure and sketch the output waveforms in Fig Fig III. Does the outputs F1 ~ F4 change when the state of D3 and D4 is changed? (B) Set SW0 to "1" and C5 (Clear) to "0" I. Connect A3 (UP) to 1 Hz, observe and record outputs of the digital display in Table 8-6. Table

83 II. Connect A3 (UP) to 1 KHz, measure and sketch the output waveforms in Fig Fig III. Does the outputs Fl-F4 change when the state of D3 and D4 is changed? (C) Connect C5 and C6 to "0" and "1" respectively. Repeat steps I, II, III and record the outputs in Table 8-7 and Fig Table

84 (D) Connect C5, C6 to "0" and follow input sequences for D3, D4, D5, D6 in Table 8-8. Observe and record the outputs. Table 8-8 (E) Connect A3 to "1"; F1-F4 to L1-L4 and a 7-segment digital display; C5 (Clear) to "0" and C6 (Load) to 1" I. Connect B3 (DN) to 1 Hz and record outputs in Table 8-9. Table 8-9 II. Connect B3 (DN) to 1 KHz, measure and sketch output waveforms in Fig Fig

85 OBJECTIVES Experiment#9 1-Voltage Controlled Oscillator (VCO) Circuit IC Oscillator Circuit a- Study how to control frequency with voltage and applications of VCO circuits. b- Understand the structure and applications of 555 oscillator circuit. Part#1: Voltage Controlled Oscillator (VCO) Circuit DISCUSSION From the equation "Q=CV=1t" we can find the time (t=cv/i) and the frequency f (f=1/t). Therefore the frequency can be varied by changing the current, which in turn could be controlled by the voltage. Oscillator circuits in which the output frequency are controlled by the voltage are called "Voltage Controlled Oscillator" or VCO. A typical VCO circuit is shown in Fig. 9-1 Fig. 9-1 Typical VCO circuit Q1Q2 are two identical transistors wrapped together that come under the same environmental influences and have the same amount of current leakage. Since the B and C pole of Q1 and Q2 are connected, their bias, as well as IB and Ic are equal. But Ic= IE= l1, current at Q3 (l3) is equal to the current at Q1 (l1), l1=vr/re, VE=V1, l2=l1 and l2 will charge C. If Vc is less than the high threshold voltage, Vo will be in high state which means Q5 and D2 will be off until VL reaches the threshold voltage and Vo goes into low state. When Vo is in the low state, Q5 and D2 will be on, VE=0 and l2=0, C will discharge towards R2 and Q5. When VL drops below the low threshold voltage, the output will go into high state again, again turning off Q5 and

86 D2, l1 will be generated and l2 will charge C. This loop will be repeated again and again as the output alternates between high and low state. Higher voltage will increase the ratio of VE/VR and larger 12 will increase the charging speed of C. The output frequency is directly proportional to the voltage. EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; DLLT-EM07: Clock Generator Circuit Experiment Module; Oscilloscope PROCEDURES 1. Connect A4 and A5 on circuit c of module DLLT-EM07 to +12V and Vadj respectively. Fig Adjust Vadj, measure the input voltage and the output frequency with the oscilloscope. Record the waveforms in Fig Fig What are the output frequencies when R7 is in position a and b?

87 RESULTS 1. The magnitude of input voltages will determine the output frequencies. 2. Smaller voltage will result in higher output frequency. Part#2: 555 IC Oscillator Circuit DISCUSSION The 555 IC is a widely used element in digital circuits and industrial control circuits. It is used to assemble mono-stable, astable circuits as well as VCO circuits. The 555 IC consist of the following parts: 1. Down comparator 2. Up comparator 3. Discharge transistor 4. Flip-flop 5. Output driver The schematic diagram of a 555 IC is shown in Fig. 9-5.Since it contain comparators the 555 IC is also considered a "linear" IC. Fig C The down-comparator's output will be "0" if the input is less than 1/3Vcc. When the output of down-comparator is "0", the flip-flop can be cleared. If the flip-flop is set, the discharge transistor will be triggered and the output goes to "1 ". On the other

88 hand, if the flip-flop is cleared, the discharge transistor will be cut off and the output is "0". Pin assignment of the 555 IC follows: 1. Pin 2 (TRIGGER): activates on "0" Trigger the flip-flop so the output Q will be in high state. If the input voltage at pin 2 is higher than 1/3 Vcc or open the output is "1"; lower than 1/3 Vcc the output will be "0". 2. Pin 4 (RESET): activates on low voltage When RESET=0 output Q=0. If RESET is connected to ground or the input voltage is lower than 0.4V the output is "0". If the input is higher than 1 V or open the output will be "1". 3. Pin 6 (THRESHOLD): activates on "1" When THRESHOLD is activated the output of flip-flop will go back to low state. The output is "1" when input voltage is higher than 2/3 Vcc and "0" if input voltage is lower than 2/3 Vcc or open. In case these three pins come in conflicts the order of priority is: RESET-TRIGGER-THRESHOLD 4. Pin 7 (DISCHARGE) When Pin 3 (OUTPUT) is in high state Pin 7 will be open to ground. If the output is in low state the transistor Q become conductive and Pin 7 is short to ground. 5. Pin 5 (CONTROL VOLTAGE) The input terminal for external voltage which controls THRESHOLD and TRIGGER's required voltage level. 6. Pin 8 (Vcc): Range: 4.5V-16V 7. Pin 3 (OUTPUT) Output high, low state current up to 200mA. Fig. 9-6shows a monostable oscillation circuit constructed with 555 IC

89 Fig oscillator circuit Assuming there are no capacitive voltages at the beginning, there is no discharge loop at Pin 7 because the transistor is not conductive. Vcc will charge C through (RA+RB). When the voltage reaches 2/3Vcc, Pin 7 will start to discharge. Discharge stops when the voltage drops below 1/3 Vcc and starts again until 2/3 Vcc is reached again, repeating this discharge-charge cycle again and again. In Fig we can see the waveform fluctuate between 1/3 and 2/3 Vcc. The charge loop is: (RA+RB) x C; the discharge loop is RBxC. If the charging time from 1/3 Vcc to 2/3 Vcc is called T1; the charging time from 0 to 1/3 Vcc is called t1; and from 0 to 2/3 Vcc called t2 then T1=t2-t1 or T=0.7(RA+RB) x C. Assuming the discharge time from 2/3 Vcc to 1/3 Vcc is called T2, T2=0.7RBxC. The cycle is T1 +T2, as RA and RB varies, pulses of different work cycle will be generated. To get a 50% symmetrical work cycle the circuit of Fig. 9-7 should be used. The charge circuit consists of R1, D1 and C while the discharge circuit consists of R2, D2 and C. As R1 =R2 and D1 =D2, T1 will be equal to T2 and the work cycle is 50%

90 Fig. 9-7 EQUIPMENTS REQUIRED: DLLT-1300 Digital Logic Lab Trainer, Module DLLT-EM07: Clock Generator Circuit Experiment, Oscilloscope PROCEDURES: (a) 555 Oscillator Circuit Fig Insert connection clips according to Fig. 9-8 and connect Pin 4 to Vcc. Measure and record Pin 3 (F1) under these conditions:

91 2. What is the output if Pin 4 is grounded? 3. Insert connection clips according to Fig. 9-9 to construct the circuit of Fig

92 4. Measure and record waveforms of TP3 and F1 under these conditions: 5. Connect Vcc to the Adjustable Power Supply on DLLT What is the allowable voltage range?

93 Experiment#10 Electronic EPROM (EEPROM) Circuit OBJECTIVE Understand the characteristics and applications of EEPROM. DISCUSSION The only difference between EEPROM and EPORM is how they are erased. While EPROM is erased by exposure to ultraviolet light, EEPROM is erased by voltage so it has no quartz window. Writing of EEPROM is accomplished by connecting a pin to a voltage higher than its supply voltage and erasure is done by setting all data to "1" (Hi state). This characteristic enables EEPROMs to be erased address by address, whereas all addresses in EPROM will be erased when exposed to ultraviolet light. Therefore, EEPROM is more convenient to use than EPROM, but EEPROM can only be accessed for approximately 2x10" times, which is not enough for computer applications. However, EEPROM is very useful for storing tables or charts that are not accessed often and does not change too frequently. The 2864 EEPROM is used in this experiment; its pin assignment and truth table are shown in Fig and 10-2 respectively. Fig EEPROM

94 Fig Input address Data Control pins for 2864 includes CE, OE & Vpp CE is Chip Enable. In order to trigger the IC, CE must be "0". OE is Output Enable, For READ operations, OE and CE must both be "0". For WRITE operation, OE must be 1", CE must be"0" and Vpp=21 V. EQUIPMENTS REQUIRED DLLT-1300 Digital Logic Lab Trainer; DLLT-EM11: Memory Circuits (2) Experiment Module PROCEDURES 1. Complete the circuit shown in Fig Connect Vcc to +5V Table