Pre-Emphasis and Equalization Parameter Optimization with Fast, Worst-Case/Multibillion-Bit Verification

Transcription

1 Pre-Emphasis and Equalization Parameter Optimization with Fast, Worst-Case/Multibillion-Bit Verification Andy Turudic, Altera Corporation Steven McKinney, Mentor Graphics Vladimir Dmitriev-Zdorov, Mentor Graphics Vince Duperron, Molex Karen Stoke, Altera Corporation 2005 Altera Corporation

2 Agenda System issues when designing high-speed serial interfaces Typical high-speed system interconnect components FPGA with transceiver Backplanes Connectors Optimizing signal integrity settings for high-speed channels Estimation and simulation tools and techniques Advanced vs. conventional simulation techniques Results 2

3 Designing a Robust, High-Speed Serial Interface Will it Work? Will it Meet Specifications? Primary concerns for system designers and architects: Signal integrity many channels Reducing system power dissipation Aggregate bandwidth and line bitrate Increasing capacity of legacy systems Bit-error rate (BER) Design and prototype cycles are expensive and difficult to troubleshoot Ideally simulate in EDA Well correlated models and techniques BER specification of 10E-18 Can take years to verify sequentially, requiring extrapolation of bathtub curves The Right Choice of FPGAs, EDA Tools, and Interconnects Is Critical to Design Success! 3

4 Typical System with Serial Interface Lossy Transmission Lines Switch Backplane OC48 Line Card Will It Work? Will It Meet Specs? Will I Get Fired? 4

5 Stratix II GX FPGA - Transceiver Blocks Transceiver functionality 8b/10b encoder/decoder Rate matcher Phase compensation FIFO 8,10,16, 20, 32, 40 bit interface to core 600 Mbps Gbps with analog clock data recovery (CDR) OC48/STM16 optical jitter compliant Pre-emphasis and equalization With over 5000 settings, can drive 1.25m FR4 5

6 Transceiver-Based Applications PCIe state machine Power state sequencing Electrical idle, receive detect, and others Physical interface to PCIe (PIPE) to core Gigabit Ethernet state machine Comma character insertion/deletion GMII-like interface to core XAUI state machine Channel deskew, alignment, and bonding XGMII-like interface to core 6

7 Stratix II GX SI Board Diagram 6 Full Duplex Transceiver Channels Routed to SMAs 1 Microstrip Channel (Tx) (Rx is stripline) User I/Os LEDs, Pushbuttons, DIP Switch, 7-Segment Displays Power Supply AC Adapter or Banana Jacks 4 Stripline Tx and Rx Channels USB Port PC Interface 1 Channel 40 Tx, 5 Rx Rx Tx Input Clocks Trigger Clocks Output Clocks (FPGA) Input Clocks (FPGA) 7

8 Backplane Overview The GbX Reference Backplane and the I-Trac Reference Backplane served as interconnect channels for this study GbX I-Trac Three 1m channels were measured; 1m GbX Backplane 7/7/7 mil construction channel 1m I-Trac Backplane 6/7/6 mil construction channel 1m VHP I-Trac Backplane 7/9/7 mil construction channel GbX is a registered trademark of Amphenol Corporation 8

9 Connectors Overview The GbX Connector and I-Trac Connector GbX, Edge Coupled I-Trac, Broadside Coupled GbX is a registered trademark of Amphenol Corporation 9

10 SMA Launch Optimization GbX daughtercards use blind launches I-Trac daughtercards use backdrilled launches SMA, PCB Interface, and Stripline Insertion and Return Loss GbX is a registered trademark of Amphenol Corporation 10

11 Connector Launch Optimization GbX Backplane uses a six backdrill depth schedule I-Trac Backplane uses a three backdrill depth schedule Do nothing, unacceptable in a 6.375Gbps backplane Note blue curve. This is the insertion loss that results from a top to signal 1 transition if that pin via is backdrilled as deeply as possible. Leave just the barrel required to accommodate the compliant pin. Three depths are sufficient to equal or better the performance of compliant pin stub. GbX is a registered trademark of Amphenol Corporation 11

12 Connector Launch Design GbX PCB interface I-Trac PCB interface 1m channel I-Trac PCB interface 1m VHP channel All connectors to PCB Interfaces Use Polygon Antipads and flag Escapes GbX is a registered trademark of Amphenol Corporation 12

13 Tdd11 and Sdd11 Curves GbX 1m Channel, Tdd11 I-Trac 1m Channel, Tdd11 GbX and I-Trac 1m Channels, Sdd11 GbX 1m I-Trac 1m I-Trac 1m VHP GbX is a registered trademark of Amphenol Corporation 13

14 Sdd12 GbX 1m channel (Green) I-Trac 1m channel (Blue) I-Trac 1m VHP channel (Red) BER and Eye-Opening Track Insertion Loss. GbX is a registered trademark of Amphenol Corporation 14

15 Pre-Emphasis and Channel Pulse Response Far-end 1m I-Trac pulse responses No pre-emphasis produces tail Pre-emphasis minimizes pulse distortion Near end pre-emphasized pulse Far End Composite 1m I-Trac Pulse Responses with Stratix II GX FPGA Sweeping Pre-Emphasis 15

16 Another Pre-Emphasis Technique Produce a clock pattern of five ones and five zeros Search settings until qualitatively square waveform 16

17 Too Much Pre-Emphasis? 0mA 3mA 6mA Far-End Eyes for a 15-inch GbX Backplane Channel Opening Curve Shape Is Channel and Bit-Rate Dependent Pre-Emphasis GbX is a registered trademark of Amphenol Corporation 17

18 Altera s Pre-emphasis & Equalization Link Estimator (PELE) - EDA tool for FAEs to estimate customers pre-emphasis and equalization coefficients Tx Model Customer Provided S-Parameters PELE Rx Model Coefficients Backplane 18

19 S-Parameters Not Scary Can be obtained from a number of sources Simulated/extracted (yellow), VNA (magenta), iconnect TDR/TDT (red) Example shows S21 which is insertion loss for I-Trac VHP 1m backplane channel 19

20 PELE Estimations vs. Bench at 6.25 Gbps PELE Estimated Eye from VNA S-Parameter Data Measured 1m I-Trac Eye PELE takes ~3 minutes to run PELE inputs from bench or EDA PELE outputs then control SPICE model PELE Estimated Eye from SPICE S-Parameter Data 20

21 Altera Stratix II GX Design Kit Design kit for use in Mentor Graphics HyperLynx signal integrity software Includes example topologies using Eldo SPICE models from Altera Customized model configurator for easy model setup Includes integration with Altera s PELE tool 21

22 Mentor Graphics Fast-Eye Diagram Simulation Tool (FEST) Data Flow Interconnect Channel Driver/Receiver Devices Model of Interconnect Channel Driver- and Receiver-IC Models Measurement Subsystem Circuit Simulator Channel S-Parameter Model Pulse/Step Response or Eye-Diagram Contour Fast-Eye-Diagram Subsystem or Eye Stimulus BER Bathtub Curve Worst-Case Stimulus Built-in Jitter Generator Built-in Stimulus Generator or 22

23 Worst-Case Bit Sequence and the Eye Worst-case bit sequence always generates the maximally closed eye Even beyond what is seen with billions of bits of data Can be 8b/10b protocol constrained Unit Interval Unit Interval ,000 2,000 3,000 4,000 5,000 6,000 Bit Rate Bit Rate 23

24 Different Methods of FEST There are several different approaches to fast-eye analysis Statistical analysis Step and impulse responses are collected and analyzed using 1 of 2 different techniques Convolution approach to build the eye Internal State Variable (ISV) approach to build the eye 24

25 Different Methods of FEST Results using the different impulse methods Unit Interval Internal State Variable 8b/10b 100 billion bits Unconstrained psuedorandom binary sequence (PRBS) 100,000 bits Convolution 8b/10b 10 million bits unconstrained PRBS 10 million bits Bit Rate 25

26 Different Methods of FEST Statistical analysis provides a bathtub curve of results Includes both Gaussian and Sinusoidal jitter Time offset in UI 26

27 Correlation of Results Statistical results versus impulse response with ISV Eye widths and heights are approximately equal in both cases Width = ~0.3 UI Height = ~ 25 mv 0.06 Statistical ISV

28 Correlation of Results Results of FEST analysis using ISV with measured vs. simulated step/pulse response 1 billion bits observed Measured Simulated 28

29 Correlation of Results Overall good correlation between both responses Differences are a result of: Extracted s-parameter data vs. using actual board data from measurement Bandwidth limitations of the scope-limited sample size of pulse and step responses 29

30 Correlation Results Simulated eye vs. lab measurement 30,000 samples in scope 1 billion bits in simulation Using constrained 8b/10b pattern

31 Correlation Results Overall good correlation between lab and simulated eye In the simulated results, the eyes are more closed, but this is expected based on difference in samples used Artifacts seen in measurement correlate very closely to artifacts in simulation 31

32 Conclusion (1/2) Eliminates guesswork for optimal signal integrity settings for high-speed channels PELE tool estimates pre-emphasis and equalization settings based upon S-parameters S-parameters extracted from EDA flow or bench EDA models are well correlated to bench measurements Integrating PELE allows direct configuration of ELDO/SPICE Models are well correlated to actual devices Reduces errors Ensures interworking of files, models, and tools Increases productivity by reducing simulation iterations 32

33 Conclusion (2/2) Now possible to validate design reliability at billions of bits using EDA tools like the Fast Eye Simulation Tool (FEST) Faster than traditional time-domain simulations Nearly identical results with SPICE runs Worst-case bit sequences can be generated with FEST Produces condensed test pattern resulting in maximally closed eye Designers can have confidence in meeting system design BER targets Integration of High-density Digital Functions With High Aggregate Capacity Serial Interconnects Is Possible By Using These Advanced Tools, Interconnects, and FPGAs 33

34 For More Information. Andy Turudic, Altera Corporation Steven McKinney, Mentor Graphics Vladimir Dmitriev-Zdorov, Mentor Graphics Vince Duperron, Molex Karen Stoke, Altera Corporation

35 Acknowledgements The authors would like to thank Gourgen Oganessyan and David Dunham at Molex; Leonard Dieguez, Tina Tran, Mark Flanigan, Naresh Raman, Venkat Yadavalli, Samson Tam, Sergey Shumarayev, Sarah Adams, James Adams, Kelly St. Denis, Zhi Wong, Jan-Sian Tai, Jeff Holmbeck, James Smith, Michael Woo, Toan Nguyen, Amy Lee, Christine Young and Dave Greenfield at Altera; Gary Pratt at Mentor; and Steve Bright and Eugene Mendeleyev at Tektronix. References Wilson Wong, Tin Lai, Sergey Shumarayev, Simardeep Maangat, Tim Hoang, Tina Tran, Digitally Assisted Adaptive Equalizer in 90 nm With Wide Range Support From 2.5 Gbps 6.5 Gbps. DesignCon 2007 Eric Bogatin, From Bit-banger to Gigabit Guru. High Speed Seminar Proceedings CD, Altera Corp, March Leonard Dieguez, High Speed Channel Design. High Speed Seminar Proceedings CD, Altera Corp, March Eric Bogatin, ibid. Andy Turudic, Abracadabra: Making system interconnect disappear with FPGAs. EDN Magazine, Sept. 14, 2006, Tina Tran, Gary Pratt, Kazi Asaduzzaman, Mei Luo, Simar Maangat, Toan Nguyen, Sergey Shumarayev, Kwong-Wen Wei, Equalization Challenges for 6-Gbps Transceivers Addressed by PELE A Software-Focused Solution! DesignCon Min Wang, Henri Maramis, Donald Talian, and Kevin Chung, New techniques for designing and analyzing multi- GigaHertz serial links. DesignCon Bryan K. Casper, Matthew Haycock, Randy Mooney. - Circuit Research, Intel Labs, Hillsboro Oregon, An accurate and efficient analysis method for multi-gbs chip-to-chip signaling schemes. VLSI Circuits Digest of Technical Papers, June 13, 2002, pages Anthony Sanders, Mike Resso, John D Ambrosia, Channel compliance testing utilizing novel statistical eye methodology. DesignCon

36 Thank You! Visit Altera s booth #503 to see demonstrations of FPGAs driving backplanes and cables Visit Mentor s booth #604 to see HyperLynx tools with PELE demonstration Visit Molex booth #301 for multi-gigabit backplane and cable demonstrations 36