Backside Circuit Edit on Full-Thickness Silicon Devices

Transcription

1 Backside Circuit Edit on Full-Thickness Silicon Devices Presentation Title Line 1 Title Line Two Can I really skip the global thinning step?! Date Presenter Name Chad Rue FEI Company, Hillsboro, OR, USA Steve Herschbein, Carmelo Scrudato IBM Corporation, East Fishkill, NY, USA

2 Introduction and Motivation Why Full-Thickness Backside CE? 1. Die distortion 2. Thin silicon = mechanically and thermally fragile 3. Thinning can sometime change a sample 2

3 Backside Edit Sequence Task 1. Sample preparation Yes No 2. Global navigation a. IR imaging Yes Yes b. Expose corner fiducials Sometimes No 3. Coarse trench Yes Yes 4. Local navigation Traditional Backside CE This Work a. Expose local fiducial(s) Usually Usually EFUG 2008 b. Adjust CAD overlay 1-point 3-points 5. Local trench Yes Yes 6. Edit Yes Yes 3

4 Backside Edit Sequence 1. Sample preparation 2. Global navigation a. IR imaging b. Expose corner fiducials 3. Coarse trench 4. Local navigation a. Expose local fiducial(s) b. Adjust CAD overlay 5. Local trench 6. Edit (Blue = Today s topics) 4

5 IR Imaging Through Thick Silicon Optical view of surface View through ~550 µm silicon 5

6 IR Imaging Through Thick Silicon IR view of circuitry With CAD overlay 6

7 IR Imaging Improves with Trenching 775 µm Silicon ~10µm Silicon 7

8 Backside Edit Sequence 1. Sample preparation 2. Global navigation a. IR imaging b. Expose corner fiducials 3. Coarse trench 4. Local navigation a. Expose local fiducial(s) b. Adjust CAD overlay 5. Local trench 6. Edit (Blue = next topic) 8

9 Maximize Milling Speed How can we achieve suitable milling speeds for full-thickness backside CE? 1. Increase beam current 2. Increase XeF 2 Pressure 3. Lower gas nozzle 4. Reduce loop time (retrace time 9

10 Trenching Speed and Nozzle Height Silicon Removal Rate (10 6 µm 3 /min) High-flux coaxial nozzle Nozzle Height Above Sample (µm) 10

11 Trenching Speed and Gas Depletion n Silicon Removal Rate (10 6 µm 3 /min) T= i= 1 t i T = Total pattern loop time t i = Individual pixel dwell time t n-1 t n Pattern Loop Time (msec) t 1 t 2 t 3 11

12 Sample Trench Top Down View (550 µm silicon, 44 minutes milling) Tilted View 12

13 Another Example IR View (770 µm silicon, 70 minutes milling) IR FIB View 13

14 Trench with Endpointing Top Down View Tilted View 14

15 Special Considerations Potential problems: Poor visibility Limited IR objective travel range Gas depletion effects Non-planar trench floor Solutions: Reduce aspect ratio Use alternate endpointing techniques (stage current) Set initial Si surface higher than eucentric Use smaller beam currents and/or longer refresh times Optimize milling parameters (may slow down the removal rate) SOI substrates 15

16 Conclusions Full-thickness backside CE is indeed possible Trenching times ~ hour (or better) are possible Successful IR imaging through most samples Accurate navigation using local registration points Particularly well-suited to SOI devices Some challenges exist Reduced visibility Gas depletion effects Economic aspects need further investigation 16

17 Backside Edit Sequence 1. Sample preparation 2. Global navigation a. IR imaging b. Expose corner fiducials 3. Coarse trench 4. Local navigation a. Expose local fiducial(s) b. Adjust CAD overlay 5. Local trench 6. Edit (Blue = next topic) 17

18 Identify Local Registration Features Coarse Trench with CAD Overlay IR View 18

19 Expose Registration Features Error vectors may vary within a field-of-view! 19

20 Register CAD Overlay 20

21 Registered CAD Overlay 21

22 Customized CAD Overlay Digital magnification is used to position milling patterns onto the customized CAD overlay 22

23 Advantages of the Navigational Technique Very accurate Typical errors of ~30 nm over a 150 µm travel range Non-invasive Uses a single high-resolution image No need for live imaging to visit lock points Does not require laser interferometer stage 23

24 Backside Edit Sequence 1. Sample preparation 2. Global navigation a. IR imaging b. Expose corner fiducials 3. Coarse trench 4. Local navigation a. Expose local fiducial(s) b. Adjust CAD overlay 5. Local trench 6. Edit (Blue = next topic) 24

25 Special Considerations Potential problems: Poor visibility Limited IR objective travel range Gas depletion effects Non-planar trench floor Solutions: Reduce aspect ratio Use alternate endpointing techniques (stage current) Set initial Si surface higher than eucentric Use smaller beam currents and/or longer refresh times Optimize milling parameters (may slow down the removal rate) SOI substrates 25

26 Conclusions Full-thickness backside CE is indeed possible Trenching times ~ hour (or better) are possible Successful IR imaging through most samples Accurate navigation using local registration points Particularly well-suited to SOI devices Some challenges exist Reduced visibility Gas depletion effects Economic aspects need further investigation 26

27 Backup Material 27

28 Speed and Trench Planarity Silicon Removal Rate (10 6 µm 3 /min) Pattern Loop Time (msec) Center deeper 28

29 Speed and Trench Planarity Silicon Removal Rate (10 6 µm 3 /min) Pattern Loop Time (msec) Flat bottom 29

30 Speed and Trench Planarity Silicon Removal Rate (10 6 µm 3 /min) Pattern Loop Time (msec) Edges deeper 30

31 Trench with Endpointing Contrast enhanced Top Down View Tilted View 31