Assembling Scan Structures 5

Transcription

1 5 Assembling Scan Structures 5 Before assembling the scan structures, you must specify the scan architecture and preview the resulting scan structures. This chapter includes the following sections: Specifying the Scan Architecture Previewing Scan Structures Assembling Scan Structures Figure 5-1 shows the role of these steps in generating scan chains. HOME CONTENTS INEX / 5-1

2 Figure 5-1 Specify-Preview-Assemble Flow Pre-Scan esign Specify Preview Assemble User-Generated dc_shell Script TC-Generated dc_shell Script "What Shall Be" Report Scan esign Use the following command sequence for the basic scan assembly flow: dc_shell> current_design top /* specify the scan architecture */ dc_shell> set_scan_configuration -chain_count 4 /* preview the scan structures */ dc_shell> preview_scan /* assemble the scan structures */ dc_shell> insert_scan /* verify */ dc_shell> check_test dc_shell> report_test -scan_path dc_shell> report_constraints -all_violators Perform the specify, preview, and assemble steps from the same current design. The following sections provide details about these steps. HOME CONTENTS INEX / 5-2

3 Specifying the Scan Architecture Scan configuration is the specification of global scan properties for the current design. Use the set_scan_configuration command to specify global scan properties, such as Scan methodology Scan style Number of scan chains Handling of multiple clocks Using the global properties you define, C Expert Plus automatically generates a complete scan architecture. See the esign Compiler Reference Manual: Optimization and Timing Analysis for details about the set_scan_configuration command, including default behavior. C Expert Plus also supports detailed specification of individual scan paths. Use the following commands for detailed specification of the scan architecture (scan specification): set_scan_element Use this command to specify sequential elements to be excluded (or included) in the scan chains. C Expert Plus supports the following types of sequential elements: leaf cells, hierarchical cells, references, library cells, and designs. Use the set_scan_element command sparingly. For best results, use the command only on instances. HOME CONTENTS INEX / 5-3

4 set_scan_link Use this command to specify connections between scan elements. C Expert Plus supports the use of nets or lock-up latches as connection elements. set_scan_path Use this command to specify properties specific to a scan chain, such as name, membership, and ordering. set_scan_segment Use this command to identify an existing structure, such as a shift register, that can be used as part of a scan chain. set_scan_signal Use this command to specify desired port connections for test signals. You might be unfamiliar with some of the scan path components used in the scan specification commands. Figure 5-2 illustrates the scan path components. HOME CONTENTS INEX / 5-4

5 Figure 5-2 Scan Path Components test_si Scan Element top insta instb instc clk1 ~ clk2 ~ clk2 ~ clk2 ~ clk1 ~ clk2 ~ Scan Segment latch1 clk1 Scan Link test_so Figure 5-2 shows a single scan path that starts at port test_si (which receives the test_scan_in scan signal) and ends at port test_so (which drives the test_scan_out scan signal). Cells insta/, insta/, instb/, and instb/ are examples of scan elements. The shift register in instc is a defined scan segment. In the bottom-up flow, the scan chains in insta and instb are considered subchains or inferred scan segments. The thick lines represent scan links. The latch (instance latch1) is also a scan link. The Using Existing Structures in Your Scan Chain section later in this chapter discusses defined scan segments and subchains. See the esign Compiler Reference Manual: Optimization and Timing Analysis for information about the detailed specification commands. HOME CONTENTS INEX / 5-5

6 The following sections discuss some of the situations you might encounter during scan specification. See the Selecting a Scan Style section in Chapter 2 for scan style selection considerations. Selecting a Scan Methodology C Expert Plus supports the full-scan methodology. This methodology achieves the highest fault coverage results in the shortest period of time. Fault coverage results for full-scan designs are typically higher than those for partial-scan designs due to the increased controllability and observability of the design and the greater efficiency of the combinational automatic test-pattern generation (ATPG) algorithm. In addition, vector counts and tester memory requirements are generally lower for full-scan designs despite the increased width of each pattern. C Expert Plus reduces the performance impact of implementing full scan by considering the scan effects when optimizing your design. uring the initial compile, C Expert Plus scans all sequential cells. In a timing-critical design, you can choose not to scan sequential cells on the critical path by using the set_scan_element false command. This approach gives you manual control of the tradeoff between timing and fault coverage goals. See the esign Compiler Reference Manual: Optimization and Timing Analysis for information about the set_scan_element command. The full-scan methodology requires you to make fewer design decisions and uses the simpler, more predictable combinational ATPG algorithm. For these reasons, you can typically achieve the fault coverage results you want in less time with full-scan designs than with partial-scan designs. HOME CONTENTS INEX / 5-6

7 Use the set_scan_configuration -methodology command to specify your scan methodology. dc_shell> set_scan_configuration -methodology full_scan If you do not specify a scan methodology, C Expert Plus assumes full scan. When you select the full-scan methodology, your design is a full-scan design regardless of the actual percentage of sequential cells scanned. Test Compiler ATPG uses combinational algorithms to generate patterns for your full-scan design. etermining Scan Chain Count Use these questions to decide how many scan chains to request: How many scan chains does your semiconductor vendor allow? Many semiconductor vendors restrict the maximum number of scan chains due to software or tester limitations. Before performing scan specification, check with your semiconductor vendor for the maximum number of scan chains supported. How many clock domains exist in your design? To prevent timing problems on the scan path in multiplexed flipflop designs, allocate a scan chain for each clock domain (C Expert Plus default behavior). C Expert Plus considers each edge of a clock a unique clock domain. Multiple clock domains do not affect the number of scan chains in scan styles other than multiplexed flip-flop. HOME CONTENTS INEX / 5-7

8 How much time will it take to test your design? Because the test time is proportional to the length of the longest scan chain, increasing the number of scan chains reduces the test time for a design. Use the set_scan_configuration -chain_count command to specify the number of scan chains. dc_shell> set_scan_configuration \ -chain_count number_of_chains By default, C Expert Plus generates One scan chain per clock domain, if you selected the multiplexed flip-flop scan style One scan chain, if you selected any other scan style Selecting Test Ports Sharing ports betweem test and normal operation minimizes the number of dedicated test ports required for internal scan. By default, C Expert Plus minimizes the number of dedicated test ports by sharing scan outputs with functional ports when the design contains scannable cells that directly drive functional ports. If your semiconductor vendor does not support this configuration, you can request dedicated scan output ports. Always use dedicated ports for scan-enable and test clock signals. To enable simulation using the same testbench for the RTL and gatelevel implementations of your design, you can define unconnected ports in your RTL description for use as scan ports. These HOME CONTENTS INEX / 5-8

9 unconnected ports are called dummy scan ports. If you defined dummy scan ports for your design, use the set_scan_signal command to instruct C Expert Plus to use these ports. dc_shell> set_scan_signal test_scan_in \ -port dummy_scan_in dc_shell> set_scan_signal test_scan_enable \ -port dummy_scan_en dc_shell> set_scan_signal test_scan_out \ -port dummy_scan_out Sharing a Scan Input With a Functional Port By default, C Expert Plus always generates a dedicated scan input port. To share a scan input port with an existing functional port, use the set_scan_signal command. dc_shell> set_scan_signal test_scan_in -port fnc_in If you select a bidirectional port as the scan input port, C Expert Plus automatically inserts the necessary bidirectional control logic. Sharing a Scan Output With a Functional Port If a scan chain contains a scannable sequential cell whose output directly drives a port in the current design, C Expert Plus automatically uses this cell as the last cell in the scan chain. If there are multiple scannable sequential cells that directly drive output ports, C Expert Plus uses the cell that is last in alphanumeric order. C Expert Plus disrupts alphanumeric ordering to share the scan output port only on the current design. If you use the top-down design flow on a hierarchical design, C Expert Plus places each subdesign scan HOME CONTENTS INEX / 5-9

10 chain in alphanumeric order. Use the preview_scan command to see if a cell has been moved to the end of the scan chain to prevent a dedicated scan output port. To select the functional port to be used as a scan output port, use the set_scan_signal command. dc_shell> set_scan_signal test_scan_out \ -port fnc_out If you select a bidirectional or three-state port as the scan output port, C Expert Plus automatically inserts the necessary control logic. If a scannable sequential cell drives the specified output port, C Expert Plus places that cell last in the scan chain. Otherwise, C Expert Plus automatically adds the control or multiplexing logic required to share the scan output port with the functional output port. Using edicated Scan Output Ports If your semiconductor vendor requires dedicated scan output ports (or you prefer them), use the set_scan_configuration command to specify dedicated scan outputs. dc_shell> set_scan_configuration -dedicated_scan_ports true This command specifies dedicated top-level scan outputs for all scan chains in the design. If you want dedicated top-level scan outputs on specific scan chains, use the set_scan_path command. dc_shell> set_scan_path scan_chain_name \ -dedicated_scan_out true HOME CONTENTS INEX / 5-10

11 The test_dedicated_subdesign_scan_outs variable controls the creation of dedicated scan output ports on subdesigns during hierarchical scan assembly. Leaving this variable at its default setting (true) enables the scan signals to be buffered separately from the functional signals at the module level, thereby reducing the impact of scan loading on the functional signal path. It also enables better placement of scan-out lockup latches by insert_scan during bottomup scan insertion. However, the addition of scan-out buffers between hierarchical levels can cause an increase in the gate count, and the creation of dedicated scan-out ports on subdesigns can cause more uniquification of subdesigns. When these effects outweigh the benefits of having dedicated scan-out ports, set the test_dedicated_subdesign_scan_outs variable to false: dc_shell> test_dedicated_subdesign_scan_outs = false You cannot specify both dedicated subdesign scan-out ports and hierarchical scan chain isolation. If you specify both, C Expert Plus generates the following message during scan assembly: Warning: Ignoring the request for dedicated subdesign scan-out ports. Hierarchical isolation was also requested. (UIT-47) See the Minimizing Noise and Power issipation section later in this chapter for information about hierarchical isolation. HOME CONTENTS INEX / 5-11

12 Balancing Scan Chains By default, the insert_scan command balances the number of cells in each scan chain. In the following cases, C Expert Plus can generate unbalanced scan chains: Your multiplexed flip-flop design has multiple clock domains. You are using the bottom-up design flow. You have specified scan segments using the set_scan_segment command. You have specified complete scan chains using the set_scan_path command. In the first two cases (multiple clock domains or bottom-up design flow), you can override C Expert Plus default behavior to force balanced scan chains. When overriding the default behavior, always use preview_scan to verify that the result meets your requirements. Multiple Clock omains For multiplexed flip-flop designs, C Expert Plus allocates cells to scan chains based on clock domain. You can override this default behavior using the set_scan_configuration -clock_mixing command. For example, assume you have a design with three clock domains and your desired scan architecture contains two balanced scan chains. dc_shell> create_test_clock {clk1, clk2} -waveform {45, 55} dc_shell> set_scan_configuration -chain_count 2 HOME CONTENTS INEX / 5-12

13 In the default case shown in Figure 5-3, C Expert Plus overrides your request for two chains and generates three scan chains one for each clock domain (clk1, positive-edge clk2, negative-edge clk2). Because the clock domains contain unequal numbers of cells, C Expert Plus generates unbalanced scan chains. Figure 5-3 Unbalanced Scan Chains ue to Multiple Clock omains test_si1 test_si3 test_si2 insta instb instc top clk1 ~ clk1 ~ clk2 ~ clk1 ~ clk1 ~ clk2 ~ test_so1 test_so3 test_so2 You can reduce the number of scan chains (and achieve slightly better balancing) by mixing clock edges within a single chain. dc_shell> create_test_clock {clk1, clk2} -waveform {45, 55} dc_shell> set_scan_configuration -chain_count 2 dc_shell> set_scan_configuration -clock_mixing mix_edges Mixing clock edges in a single scan chain produces a small timing risk. C Expert Plus automatically orders the cells within the scan chain so the cells clocked later in the cycle appear earlier in the scan chain, resulting in a functional scan chain. Figure 5-4 shows the scan architecture when you allow edge mixing. HOME CONTENTS INEX / 5-13

14 Figure 5-4 Better Balancing Using Mixed Clock Edges test_si1 test_si2 insta instb instc top clk1 ~ clk1 ~ clk2 ~ clk1 ~ clk1 ~ clk2 ~ test_so1 test_so2 You can balance the scan chains by mixing clocks. dc_shell> create_test_clock {clk1, clk2} -waveform {45, 55} dc_shell> set_scan_configuration -chain_count 2 dc_shell> set_scan_configuration -clock_mixing mix_clocks Mixing clocks in a single scan chain can produce a large timing risk. To reduce the risk, C Expert Plus adds lock-up latches to the scan path wherever clock changes occur. C Expert Plus guarantees a functional scan chain under ideal clock timing (no clock skew). Figure 5-5 shows the resulting scan architecture. HOME CONTENTS INEX / 5-14

15 Figure 5-5 Balanced Scan Chains Using Mixed Clocks test_si1 test_si2 instb instc insta top latch1 clk1 ~ clk2 ~ clk2 clk1 ~ clk1 ~ clk2 ~ clk1 ~ latch1 clk1 test_so1 test_so2 See the Handling Multiple Clock esigns section later in this chapter for clock-mixing considerations. See the Using Scan Lock-up Latches section later in this chapter for details about scan lock-up latches. Bottom-Up esign Flow By default, C Expert Plus does not modify subdesign scan chains. If C Expert Plus generated the subdesign scan chain, you can override this behavior using the set_scan_configuration -rebalance command. If the subdesign scan chain is an existing scan chain created by another method (or created by C Expert Plus in another session and stored in an ASCII format), C Expert Plus never modifies the subdesign scan chain. HOME CONTENTS INEX / 5-15

16 For example, assume that you have a design with two subdesigns, one that has a four-cell scan chain and one that has a two-cell scan chain. Your desired scan architecture contains two balanced scan chains. dc_shell> set_scan_configuration -chain_count 2 In the default case shown in Figure 5-6, C Expert Plus generates unbalanced scan chains because it does not modify the subdesign scan chains. Figure 5-6 Unbalanced Scan Chains ue to Existing Subdesign Scan Chains test_si1 insta test_si2 instb top dff3 clk1 ~ clk1 ~ clk1 ~ dff4 clk1 ~ clk1 ~ clk1 ~ test_so1 test_so2 To force balanced scan chains, use the set_scan_configuration -rebalance command. dc_shell> set_scan_configuration -chain_count 2 dc_shell> set_scan_configuration -rebalance true HOME CONTENTS INEX / 5-16

17 Figure 5-7 shows the resulting design if C Expert Plus generated the subdesign scan chains. Figure 5-8 shows the resulting design if C Expert Plus did not generate the subdesign scan chains. The two results differ because C Expert Plus never modifies scan connections it has not made. This prevents accidental modification of functional logic but might result in redundant logic as shown in Figure 5-8. Figure 5-7 Balanced Scan Chains Subdesign Chains Created by C Expert Plus test_si1 test_si2 insta instb top dff3 clk1 ~ clk1 ~ clk1 ~ dff4 clk1 ~ clk1 ~ clk1 ~ test_so1 test_so2 HOME CONTENTS INEX / 5-17

18 Figure 5-8 Balanced Scan Chains Subdesign Chains Not Created by C Expert Plus test_si1 test_si2 insta instb top dff3 clk1 ~ clk1 ~ clk1 ~ clk1 ~ clk1 dff4 ~ clk1 ~ test_so1 test_so2 Handling Multiple Clock esigns Multiple system clocks necessitate giving special attention to the scan architecture in multiplexed flip-flop designs. Because multiplexed flipflop designs use the system clock for scan shift, the ordering of cells within a scan chain can affect the scan shift operation. The easiest way to prevent clock skew problems during scan shift is to allocate cells to scan chains by clock domain. By default, C Expert Plus creates a scan chain for each clock domain in the design. You can mix different clock edges or different clocks (or both) within a scan chain by using the set_scan_configuration - clock_mixing command. This command applies only to the HOME CONTENTS INEX / 5-18

19 multiplexed flip-flop scan style. If you execute this command after specifying a scan style other than multiplexed flip-flop, C Expert Plus generates the following message: Warning: Scan style %s does not need scan clock domain constraints. Ignoring the set_scan_configuration -clock_mixing command. (UIT-229) Requirements for Valid Scan Chain Ordering C Expert Plus generates valid mixed-clock scan chains based on the specified (or inferred) test clock timing. The scan cells in a valid scan chain are ordered so the cells clocked later in the cycle appear earlier in the scan chain. This guarantees that all cells in the scan chain get the expected data during scan shift. C Expert Plus uses ideal clock timing to determine valid scan-chain ordering. Because C Expert Plus does not consider clock skew when ordering scan chains, mixed-clock scan chains might not shift properly. However, if you set the fix_hold attribute on the clock nets, C Expert Plus fixes hold-time violations during scan assembly. Always perform full-timing logic simulation on mixed-clock scan chains. Although C Expert Plus guarantees correct shift function (under ideal clock timing), it cannot guarantee that capture problems will not occur. Capture problems are caused by your functional logic; modify your design to correct capture problems. For more information, see the Untestable Functional Path section in Chapter 6. HOME CONTENTS INEX / 5-19

20 Figure 5-9 shows a design with a mixed-clock scan chain. C Expert Plus created this scan chain with default timing (rising edge at 45 ns, falling edge at 55 ns) for both clk1 and clk2. The validity of the scan chain depends on the clock timing. You can make the scan chain invalid if you change the clock timing. For example, the scan chain in Figure 5-9 is A valid scan chain (the insta cells are clocked after the instb cells) if you define the test clock timing as dc_shell> create_test_clock clk1 -waveform {55, 65} dc_shell> create_test_clock clk2 -waveform {45, 55} An invalid scan chain (the insta cells are clocked before the instb cells) if you define the test clock timing as dc_shell> create_test_clock clk1 -waveform {45, 55} dc_shell> create_test_clock clk2 -waveform {55, 65} To maintain the validity of your scan chains, do not change the test clock timing after assembling the scan structures. HOME CONTENTS INEX / 5-20

21 Figure 5-9 Mixed-Clock Scan Chain test_si1 insta instb top clk1 ~ clk2 ~ clk1 ~ clk2 ~ test_so1 By default, when you request mixing of clocks within a multiplexed flip-flop scan chain, C Expert Plus inserts lock-up latches to prevent timing problems. The Using Scan Lock-Up Latches section later in this chapter provides information about the use of lock-up latches in the scan chain. Using Multiple Master Clocks in LSS esigns In level-sensitive scan designs (LSS), you need not allocate scan chains by clock for timing purposes; however, you might want to do so. Assume you have a latch-based design with two system enables, en1 and en2, and you want a scan chain allocated for each enable. The following command sequence accomplishes this: dc_shell> set_scan_configuration -style lssd dc_shell> check_test /* create test A clock ports and assign to scan chains */ dc_shell> create_port -direction in {A_CLK1, A_CLK2} HOME CONTENTS INEX / 5-21

22 dc_shell> set_scan_path 1 dc_shell> set_scan_path 2 dc_shell> set_scan_signal test_scan_clock_a \ -port A_CLK1 -chain 1 dc_shell> set_scan_signal test_scan_clock_a \ -port A_CLK2 -chain 2 /* explicitly allocate cells to scan chains by system enable */ dc_shell> create_clock en1 -name cclk1 -period 100 dc_shell> cclk1_cells = all_registers( -clock cclk1 ) dc_shell> set_scan_path 1 cclk1_cells dc_shell> create_clock en2 -name cclk2 -period 100 dc_shell> cclk2_cells = all_registers( -clock cclk2 ) dc_shell> set_scan_path 2 cclk2_cells /* preview scan configuration and implement */ dc_shell> preview_scan -show all dc_shell> insert_scan edicated Test Clocks for Each Clock omain C Expert Plus creates clocks that are used only for test purposes when it routes scan chains using the following scan styles: Clocked-scan Level-sensitive scan design (LSS) Clocked LSS Auxiliary clocked LSS The test clocks are dedicated test clocks for each system clock domain. This makes clock trees and clock signal routing easier. C Expert Plus uses the following guidelines to determine how test clocks are added: For sequential cells with one clock, C Expert Plus adds different test clocks to cells that are clocked by different system clocks. This applies only to designs that use clocked-scan scan style. HOME CONTENTS INEX / 5-22

23 For sequential cells with multiple test clocks, C Expert Plus adds a test clock for each unique set of system clocks. For details, see the Test Compiler Reference Manual. Controlling LSS Slave Clock Routing For designs using LSS scan style, clocked LSS scan style, and auxiliary-clocked LSS scan style, all single latch and flip-flop elements have an unconnected slave clock pin after scan replacement. If possible, C Expert Plus uses the slave clocks distributed to doublelatch elements and does either of the following: Creates, at most, one new port per design when you only want to use the slave clocks distributed to the double-latch elements Creates one or more ports when you want test clocks created according to different system clocks C Expert Plus uses the following guidelines when connecting slave clock pins of single-latch and flip-flop elements after scan replacement: Connect the unconnected slave clock pin of LSS scan style single-latch or flip-flop elements to the slave clock pin of the double-latch that is clocked by the same system clock. Connect to a new slave clock, creating a new one if necessary, if a system clock drives multiple cells with different slave clocks. Connect the slave clock pin into a global port, creating one if necessary, if double-latches are driven by different clocks. Connect the slave clock pin into a global port, creating one if necessary, if there are no double-latches. HOME CONTENTS INEX / 5-23

24 You can control how C Expert Plus connects slave clock ports using the -create_test_clocks_by_system_clock_domain option to the set_scan_configuration command. If you set the -create_test_clocks_by_system_clock_domain option to true, C Expert Plus associates dedicated test clocks with distinct clock domains; therefore, you might create more than one slave clock port because cells are clocked by different system clocks. Another means of controlling how C Expert Plus connects slave clock ports is to use the test_use_dual_latch_slave_clock variable. If you set the test_use_dual_latch_slave_clock variable to true and you do not specify the -create_test_clocks_by_system_clock_domain option in the set_scan_configuration command (or if you set the option to false), you create no more than one slave clock port. For more details, see the Test Compiler Reference Manual. Using Scan Lock-Up Latches A scan lock-up latch is a retiming latch on a scan path that is clocked by the inversion of the previous scan cell s clock. Figure 5-10 shows a scan lock-up latch. HOME CONTENTS INEX / 5-24

25 Figure 5-10 Scan Lock-Up Latch test_si Scan Lock-up Latch clk1 clk1 ~ latch 1 clk1 clk2 clk2 ~ test_so Use scan lock-up latches in multiplexed flip-flop designs whenever adjacent scan cells have different clocks (or different branches of a gated clock). For successful synchronization, the falling edge of the current scan cell must occur after or concurrent with the rising edge of the next scan cell. By default, C Expert Plus adds scan lock-up latches to your multiplexed flip-flop scan chain whenever adjacent scan cells are clocked by different clocks. You can disable insertion of scan lock-up latches in multiplexed flip-flop designs by using the set_scan_configuration -add_lockup false command. If you execute this command after specifying a scan style other than multiplexed flipflop, C Expert Plus generates the following message: Warning: Scan style %s does not add lockup latches to the scan chain. Ignoring the set_scan_configuration -add_lockup command. (UIT-227) C Expert Plus does not add scan lock-up latches for clock-edge changes or for scan styles other than multiplexed flip-flop. When adding scan lock-up latches, C Expert Plus adds the scan lock-up latch to the module containing the last scan cell before the clock change. HOME CONTENTS INEX / 5-25

26 Regardless of your selected scan style, you can explicitly add scan lock-up latches to your scan chain using the set_scan_link and set_scan_path commands. Use the preview_scan -show cells command to see where insert_scan plans to insert scan lock-up latches in your scan chain. Using Existing Structures in Your Scan Chain C Expert Plus supports two types of existing scan structures: Subdesign scan chains A subdesign scan chain uses subdesign ports for all test signals. C Expert Plus can infer subdesign scan chains during test design rule checking. Scan segment A scan segment uses internal pins for one or more test signals. You must explicitly specify a scan segment. In order for C Expert Plus to use an existing scan structure, it must be compatible with the selected scan style. Using Subdesign Scan Chains To reuse existing subdesign scan chains, follow these steps: 1. Set the current design to the subdesign containing the existing scan chain. 2. Use the set_signal_type command to identify the existing scan ports. 3. Run the check_test command to infer the scan chain. HOME CONTENTS INEX / 5-26

27 4. Set the current design to the design where you are assembling the scan structures. 5. Use the set_scan_path command to control the scan chain connections, if desired. For example, subdesign sr in Figure 5-11 contains a shift register. The shift register performs a serial shift function, so C Expert Plus can use this existing structure in a scan chain. The scan input signal connects to subdesign port sr_. The scan output signal connects to subdesign port sr_. The shift register always performs the serial shift function, so the shift register does not need a scan enable signal. Figure 5-11 Subdesign Scan Chain Example Before Scan Insertion top dff4 (F1) sr_ sr_ dff3 (F1) (F1) (F1) sr Use the following command sequence to infer the subdesign scan chain in module sr: dc_shell> current_design sr dc_shell> set_scan_configuration -existing_scan true dc_shell> set_signal_type test_scan_in sr_ dc_shell> set_signal_type test_scan_out sr_ dc_shell> check_test HOME CONTENTS INEX / 5-27

28 Use the following command sequence to include this scan chain in a top-level scan chain: dc_shell> current_design top dc_shell> check_test dc_shell> insert_scan dc_shell> check_test Figure 5-12 shows the top-level scan chain, which includes the subdesign scan chain. C Expert Plus added a multiplexer (controlled by the scan enable signal) to select between the functional data input and the scan input. The hierarchical cell name determines the location of the subdesign scan chain in the top-level scan chain. Figure 5-12 Subdesign Scan Chain Example After Scan Insertion IP1 IP2 test_so OP1 test_si test_se clk Using Scan Segments Figure 5-13 shows a design that contains a shift register. The shift register performs a serial shift function, so C Expert Plus can use this existing structure in a scan chain. The scan input signal connects to pin /. The scan output signal connects to pin dff3/. The shift register always performs the serial shift function, so the shift register HOME CONTENTS INEX / 5-28

29 does not need a scan-enable signal. If the scan segment requires a scan-enable pin, each scan enable must be defined in the set_scan_segment -access statement. Figure 5-13 Scan Segment Example Before Scan Insertion top dff4 (F1) clk OP1 IP1 IP2 (F1) (F1) dff3 (F1) Use the following command sequence to define the scan segment: dc_shell> current_design top dc_shell> set_scan_segment sr1 \ -access {test_scan_in /, \ test_scan_out dff3/} \ -contains {,, dff3} dc_shell> preview_scan -show segments Use the following command sequence to include this scan segment in a top-level scan chain: dc_shell> check_test dc_shell> insert_scan dc_shell> check_test HOME CONTENTS INEX / 5-29

30 Figure 5-14 shows the top-level scan chain, which includes the scan segment. C Expert Plus added a multiplexer (controlled by the scanenable signal) to select between the functional data input and the scan input. The scan segment name determines the location of the scan segment in the scan chain. C Expert Plus never modifies a user-defined scan segment. Figure 5-14 Scan Segment Example After Scan Insertion IP1 IP2 test_so clk test_si dff4 (F1) (F1) (F1) dff3 (F1) OP1 test_se uring scan assembly, C Expert Plus does not validate the information you provide in the set_scan_segment command. However, C Expert Plus validates the resulting scan chains during test design rule checking. Figure 5-15 shows the resulting scan chain if you use the following commands to incorrectly specify and then use the scan segment: dc_shell> current_design top dc_shell> set_scan_segment sr1 \ -access {test_scan_in /, \ test_scan_out dff3/} \ -contains {} dc_shell> insert_scan HOME CONTENTS INEX / 5-30

31 Figure 5-15 Incorrectly efined Scan Segment After Scan Insertion IP1 IP2 OP1 clk test_se test_so test_si The resulting scan design has a bad scan chain (C Expert Plus uses output pin dff3/ as the scan segment scan output pin) and redundant logic (C Expert Plus performs scan replacement on cells and dff3). Completely specify user-defined scan segments to avoid this type of problem. Minimizing Noise and Power issipation C Expert Plus can insert gating logic that disables the scan path at hierarchical boundaries when the scan logic is inactive. This capability is called hierarchical isolation. Hierarchical isolation minimizes power dissipation and noise associated with long scan nets during normal operation of the design. Use the set_scan_configuration -hierarchical_isolation command to select hierarchical isolation. HOME CONTENTS INEX / 5-31

32 Use the following command sequence to include hierarchical isolation logic during scan assembly: dc_shell> current_design top dc_shell> set_scan_configuration \ -hierarchical_isolation true dc_shell> insert_scan Figure 5-16 shows a small subdesign before and after scan insertion. Notice the hierarchical isolation logic added to the scan output signal. Figure 5-16 Hierarchical Isolation Logic Nonscan Subdesign insta Scanned Subdesign insta test_so Hierarchical Isolation Logic test_si test_se C Expert Plus only inserts hierarchical isolation logic when the last cell in a subdesign scan chain does not directly drive an output port. To insert hierarchical isolation logic, C Expert Plus must create a dedicated scan output port. HOME CONTENTS INEX / 5-32

33 Modifying Your Scan Architecture Unless conflicts occur, the set_scan_configuration commands are additive. You can enter multiple set_scan_configuration commands to define your scan configuration. If a conflict occurs, the latest set_scan_configuration command overrides the previous configuration. To modify your scan configuration, you can rely on the override capability or you can remove the complete scan configuration and start over. Use the remove_scan_specification -configuration command to remove the complete scan configuration. o not use the reset_design command to remove the scan configuration. Configuring the scan chain does not place attributes on the design, so reset_design has no effect on the scan configuration and removes all other attributes from your design, including constraints necessary for optimization. You can also use the remove_scan_specification command to remove scan path specifications, scan link and scan segment definitions, and scan signal allocations. Use the remove_scan_specification -all command to remove the complete scan specification. See the esign Compiler Reference Manual: Optimization and Timing Analysis for details about the remove_scan_specification command. To make minor adjustments to the scan architecture, modify the scan specification script generated by the preview_scan -script command. dc_shell> preview_scan -script > scan_arch.scr /* manually modify scan_arch.scr to reflect desired architecture */ dc_shell> include scan_arch.scr dc_shell> preview_scan dc_shell> insert_scan HOME CONTENTS INEX / 5-33

34 Controlling Routing Order Use the set_scan_path command to explicitly control the routing order. You can specify the routing order of both nonscan and scanned sequential cells. Each set_scan_path command generates a scan chain; C Expert Plus uses the first command argument as the scan chain name. If you enter multiple set_scan_path commands with the same scan chain name, C Expert Plus uses only the last command entered. You can provide partial or complete scan ordering specifications. Use the -complete option to indicate that you have completely specified a scan chain. C Expert Plus does not add cells to a completely specified scan chain. If you provide a partial scan-ordering specification, C Expert Plus might add cells to the scan chain. C Expert Plus places the cells specified in a partial ordering at the end of the scan chain. C Expert Plus validates the specified scan ordering. The checks performed by C Expert Plus include Cell assignment C Expert Plus verifies that you have not assigned a cell to more than one scan chain. A violation triggers the following message during execution of the set_scan_path command: Error: Scan chains %s and %s have common elements. (TESTB-256) Common elements are: %s C Expert Plus discards the second scan path specification (it keeps the first scan path specification containing the common element). HOME CONTENTS INEX / 5-34

35 Clock ordering C Expert Plus verifies that the active clock edge of the next scan cell occurs concurrently or before the active clock edge of the current scan cell (or can be synchronized with a scan lock-up latch). If your multiplexed flip-flop design violates this requirement, C Expert Plus reorders the invalid mixed-clock scan chains and triggers the following message during execution of the preview_scan command: Warning: User specification of chain %s has been reordered. (TEST-342) Clock mixing C Expert Plus verifies that all cells on a scan path have the same clock (unless you have specifically requested clock mixing). A violation triggers the following message during execution of the preview_scan command: Warning: Chain %s has elements clocked by different clocks. (TEST-353) C Expert Plus creates the requested scan chain. Unless you have disabled scan lock-up latch insertion, C Expert Plus inserts a scan lock-up latch between clock domains. HOME CONTENTS INEX / 5-35

36 Black box cells C Expert Plus verifies that the specified cells are valid scan cells. If a sequential cell has a test design rule violation or has a scan_element false attribute, C Expert Plus considers it a black box cell. A violation triggers the following message during execution of the preview_scan command: Warning: Cannot add %s to chain %s. The element is not being scanned. (TEST-376) C Expert Plus creates the requested scan chain without the violating cells. Previewing Scan Structures Always run the preview_scan command to validate the scan architecture resulting from your scan specifications. The preview_scan command performs the following functions: Runs test design rule checking, if necessary C Expert Plus requires the check_test results to identify valid scan elements. Creates a complete scan architecture based on your specifications C Expert Plus validates your specifications and generates warning messages if it finds inconsistencies in the specification set or between the specifications and the design. If you provide a partial specification, C Expert Plus completes the scan specification using default behavior. HOME CONTENTS INEX / 5-36

37 Generates a report or script file detailing the resulting scan architecture If the scan architecture reported by the preview_scan command does not meet your requirements, modify your scan specification as discussed in the Modifying Your Scan Architecture section earlier in this chapter. Assembling Scan Structures The insert_scan command implements the scan architecture defined by your scan configuration (and default behavior) as detailed in the preview_scan report. Because the specify-preview loop runs much faster than scan assembly, verify that the scan architecture meets your requirements before executing the insert_scan command. When you are satisfied with the scan architecture, implement it using the insert_scan command. See the esign Compiler Reference Manual: Optimization and Timing Analysis for details about the insert_scan command. The insert_scan command implements the defined scan architecture by performing the following tasks: Inserting three-state disabling logic Inserting bidirectional control logic Routing scan chains and global signals Optimizing the testable design to minimize compile design rule violations and constraint violations HOME CONTENTS INEX / 5-37

38 If your design contains nonscan sequential cells, the insert_scan command also replaces these nonscan cells with scan cells. For information about scan replacement, see the Using Constraint- Optimized Scan Insertion section in Chapter 2. Whenever you modify your design, C Expert Plus invalidates the check_test results. For this reason, always rerun the check_test command after scan assembly. In addition, the completeness of the scan path report depends on updated check_test information. If you run a report_test -scan_path command when there are no valid check_test results, you will get a warning that no information is available. Synthesizing Three-State isabling Logic To prevent bus contention or bus float, internal three-state nets in your design must have a single active driver during scan shift. C Expert Plus determines if the internal three-state nets in your design meet this requirement. By default, C Expert Plus adds disabling logic to internal three-state nets that do not meet this requirement. The scan-enable signal controls the disabling logic and forces a single driver to be active on the net throughout scan shift. In some cases, C Expert Plus adds redundant disabling logic because the disabling logic checks for internal three-state nets are limited and do not use the test protocol information. Figure 5-17 shows the simple internal three-state net used as an example throughout this section. HOME CONTENTS INEX / 5-38

39 Figure 5-17 Internal Three-State Net Example Figure 5-18 shows the disabling logic added by C Expert Plus during insert_scan. Figure 5-18 Three-State Output With isabling Logic rivers Inactive uring Scan Shift u3 u2 river Active uring Scan Shift u1 HOME CONTENTS INEX / 5-39

40 If the design already contains logic that prevents (or can be configured to prevent) the occurrence of bus contention and bus float during scan shift, you can elect not to have the disabling logic added by C Expert Plus using the set_scan_configuration -disable command. dc_shell> set_scan_configuration -disable false C Expert Plus does not perform checks to detect bus contention or bus float conditions during scan shift. If you elect not to add the threestate disabling logic, verify that invalid conditions do not occur during scan shift. When using the bottom-up design flow, synthesize three-state disabling logic at the top level only. Synthesis of disabling logic at the top level guarantees a consistent implementation across all subdesigns. Use the set_scan_configuration -disable command to disable synthesis of three-state disabling logic in subdesigns. /* subdesign command sequence */ dc_shell> current_design subdesign dc_shell> set_scan_configuration -disable false... dc_shell> insert_scan /* top-level command sequence */ dc_shell> current_design top... dc_shell> insert_scan HOME CONTENTS INEX / 5-40

41 Synthesizing Bidirectional Control Logic Every semiconductor vendor has specific requirements regarding the treatment of bidirectional ports during scan shift. me vendors require that bidirectional ports be held in input mode during scan shift, some require that bidirectional ports be held in output mode during scan shift, and some have no preference. Use the set_scan_configuration -bidi_mode command to specify the scan-shift direction for bidirectional data ports. C Expert Plus uses the test signal type to determine the scan-shift direction for bidirectional test ports. If you do not specify a bidirectional mode, the insert_scan command uses input mode as the default. C Expert Plus determines if the bidirectional ports in your design are in the required mode during scan shift. By default, C Expert Plus adds control logic to bidirectional nets that are not in the required mode. The scan-enable signal controls the disabling logic and forces the bidirectional port into the required mode throughout scan shift. Bidirectional ports that have enables connected to constant values and are therefore always configured in either input mode or output mode are referred to as degenerated bidirectional ports. C Expert Plus does not add control logic for degenerated bidirectional ports. Before you insert control logic for bidirectional ports, understand your vendor s requirements for these cells during scan shift. If the design already contains logic to configure the bidirectional ports during scan shift, you can elect not to have the control logic added by C Expert Plus using the set_scan_configuration -disable command. dc_shell> set_scan_configuration -disable false HOME CONTENTS INEX / 5-41

42 Routing Scan Chains and Global gnals Most scan cells have both a scan output pin (test_scan_out) and an inverted scan output pin (test_scan_out_inverted) defined in the technology library. If the functional path through a sequential cell has timing constraints, C Expert Plus automatically selects the scan output pin with the most timing slack for use as the scan output. To disable this behavior, set the test_disable_find_best_scan_out variable to true. See the Specifying the Scan Architecture section earlier in this chapter for details about specifying scan routing. See the information about completing the scan architecture in the esign Compiler Reference Manual: Optimization and Timing Analysis for details about default routing behavior. Scan chain allocation and ordering might differ between a top-down implementation and a bottom-up implementation due to the following reasons: C Expert Plus does not modify subdesign scan chains unless explicitly specified in your scan configuration. See the Using Existing Structures in Your Scan Chain section earlier in this chapter for more information. C Expert Plus overrides alphanumeric ordering to provide a shared scan output connection on the current design but not on subdesigns. See the Selecting Test Ports section earlier in this chapter for more information. HOME CONTENTS INEX / 5-42

43 Rerouting Scan Chains The scan specification process previously discussed enables both initial routing and rerouting of your design. However, the specifypreview loop runs faster than the specify-synthesize loop. Try to avoid rerouting by iterating through the specify-preview loop until the scan architecture meets your requirements. When rerouting a scan chain, use the set_scan_configuration -replace command to indicate that the design already contains scan cells. dc_shell> set_scan_configuration -replace false If you forget to enter this command, C Expert Plus correctly reroutes your scan chain but generates the following warning message: Warning: You have asked for scan replacement, but attributes show that the design already has scan circuitry. Your request is ignored. (UIT-4) Optimizing the Testable esign To optimize the design during scan assembly, C Expert Plus Performs scan-specific optimizations to reduce the timing impact of scan routing In many cases, the scan path uses the functional output as the scan output. The scan path routing increases the output load on the functional output. If you used test-ready compile for scan replacement, this additional loading is compensated for during optimization. If you used constraint-optimized scan insertion, C HOME CONTENTS INEX / 5-43

44 Expert Plus uses focused optimization techniques during scan assembly to minimize the impact of the additional load on the overall design performance. Replaces unrouted scan cells with their nonscan equivalents If you used test-ready compile for scan replacement, your design might contain unrouted scan cells. These unrouted scan cells occur because the cell has a test design rule violation. C Expert Plus replaces these unrouted scan cells with their nonscan equivalents during execution of the insert_scan command. Your design might contain sequential cells that are defined in the technology library as scan cells but implement functional logic in your design. These cells have functional connections to both the data and scan inputs, and C Expert Plus does not modify these cells during scan assembly. Fixes hold-time violations on the scan path if the clock net has the fix_hold attribute Interfacing with Physical esign Tools If you use an external physical design tool that reroutes the scan chains, you can back-annotate the new scan path information into the C Expert Plus database. C Expert Plus supports chain reordering based on physical information provided in a Physical esign Exchange Format (PEF) file. This same capability is available by using the reoptimize_design command in the Synopsys Floorplan Manager. HOME CONTENTS INEX / 5-44

45 Back-Annotation of Routed Scan Paths To back-annotate scan path information modified during place and route, use the following steps: 1. etect the new scan path using the check_test command. 2. Run the preview_scan command to verify that C Expert Plus reports the correct scan architecture. You might need to provide additional configuration information, such as test clock timing or clock mixing, to ensure that the preview_scan results match the place and route scan path. 3. Generate a scan specification script using the preview_scan command. 4. Remove the scan specification from the.db file using the remove_scan_specification -all command. 5. Reroute the scan path using the generated scan specification script. Caution! This flow only works when all scan flip-flops have only a single output or offer a dedicated scan-out pin. Figure 5-19 shows a scan path before place and route. Figure 5-20 shows the scan path after modification by place and route. HOME CONTENTS INEX / 5-45

46 Figure 5-19 Scan Path Generated by C Expert Plus test_si top insta instb clk1 ~ clk1 ~ clk1 ~ clk1 ~ test_so Figure 5-20 Scan Path Generated by Place and Route test_si top insta instb clk1 ~ clk1 ~ clk1 ~ clk1 ~ test_so HOME CONTENTS INEX / 5-46

47 The following command sequence back-annotates the place and route scan path onto the design.db file. /* derive scan architecture from place-and-route netlist */ dc_shell> read -format verilog place_and_route.v dc_shell> current_design top dc_shell> create_test_clock clk -waveform {45 55} dc_shell> set_scan_configuration -existing true dc_shell> set_scan_configuration -clock_mixing mix_edges dc_shell> set_signal_type test_scan_in test_si dc_shell> set_signal_type test_scan_enable test_se dc_shell> set_signal_type test_scan_out q2 dc_shell> check_test dc_shell> preview_scan -show cells dc_shell> preview_scan -script > p_and_r_order.scr /* back-annotate place-and-route architecture onto.db file */ dc_shell> read -format db prelayout.db dc_shell> current_design top dc_shell> report_test -scan dc_shell> remove_scan_specification -all dc_shell> set_scan_configuration -replace false dc_shell> include p_and_r_order.scr dc_shell> preview_scan -show cells dc_shell> insert_scan Scan Chain Reordering Using Physical Information C Expert Plus supports scan chain reordering based on physcial proximity information provided in the Physical esign Exchange Format (PEF), version 2.0. A data file in this format describes the location of physical clusters and cells in a design. To use these capabilities in C Expert Plus, you need either a Floorplan Manager licence or a ScanPlanner licence. HOME CONTENTS INEX / 5-47