University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science SOLUTIONS
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1 University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Science EECS 5 Fall 25 R. H. Katz SOLUTIONS Problem Set #3: Combinational and Sequential Logic Assigned 4 September 25, Due 23 September at 2 PM. Design a combinational logic subsystem with three inputs, I 3, I 2, I, and two outputs, O, O, that behaves as follows. The outputs indicate the highest index of the inputs that is driven high. For example, if I 3 is, I 2 is, I is, then O, O would be (i.e., I 2 is the highest input set to ). If none of the inputs is, then the outputs would be. a. Specify the subsystem by filling out a complete truth table for the two outputs. I3 O O b. Write a specification of this function in Verilog. (note, this is using simplified product-of-sums as listed in part c) module f(o, o, i3, i2, i); input i3, i2, i; output o, i; assign o =!i2 & i i3; assign o = i3 i2;
2 c. Find the minimized Sum of Products description using K-maps. K-map of O I3 O = I2 I + I3 K-map of O I3 O = I3 + I2 d. Implement the subsystem using 2 x 4: multiplexers. I O O I3I2 I3I2 e. If implemented using a ROM, what size ROM is required? Why? The ROM would require 6 bits total. Each O and O is a function of I3 I2 and I, which have a total of 8 combinations each. f. Compare your solutions in parts (c) and (d). Which is simpler and why (i.e., what criteria are you using to measure complexity)? The multiplexor circuit is simpler because its implementation would use less transistors than a look-up table.
3 2. Scientists have discovered that the Venusians use a base 6 number system. However, the digits are quite different than the ones to which we are accustomed. The first row below is through 7, and the second row is 8 through F. Your task is to design a combinational logic subsystem to decode a hexadecimal digit in the range of () through F () to drive a seven-segment display for the Martian version of the hexadecimal digits (-7 in the top row, 8-F in the bottom row). The LED segments are numbered counter clockwise starting at the horizontal LED at the bottom (LED ). The middle LED is LED a. Specify the function by filling out a complete truth table for each of the seven segment drivers. O O O2 O3 O4 O5 O6
4 Write each as a Verilog specification. module o(o, i, i, i2, i3, i4); input i4, i3, i2, i; output o; assign o = (!I3 & I2 & I & I) (I3 &!I2 &!I &!I) (I3 &!I2 &!I & I) (I3 &!I2 & I &!I) (I3 &!I2 & I & I) (I3 & I2 &!I &!I) (I3 & I2 &!I & I) (I3 & I2 & I &!I) (I3 & I2 & I & I); module o(o, i, i, i2, i3, i4); input i4, i3, i2, i; output o; assign o = (!I3 & I2 &!I & I) (!I3 & I2 & I &!I) (!I3 & I2 & I & I) (I3 & I2 &!I &!I) (I3 & I2 &!I & I) (I3 & I2 & I &!I) (I3 & I2 & I & I);
5 module o2(o2, i, i, i2, i3, i4); input i4, i3, i2, i; output o2; assign o2 = (!I3 & I2 &!I &!I) (!I3 & I2 &!I & I) (!I3 & I2 & I &!I) (!I3 & I2 & I & I) (I3 &!I2 &!I &!I) (I3 &!I2 &!I & I) (I3 & I2 &!I & I) (I3 & I2 & I &!I); module o3(o3, i, i, i2, i3, i4); input i4, i3, i2, i; output o3; assign o3 = (!I3 &!I2 & I & I) (!I3 & I2 &!I &!I) (!I3 & I2 &!I & I) (!I3 & I2 & I &!I) (!I3 & I2 & I & I) (I3 &!I2 &!I &!I) (I3 &!I2 &!I & I) (I3 &!I2 & I &!I);
6 module o4(o4, i, i, i2, i3, i4); input i4, i3, i2, i; output o4; assign o4 = (!I3 &!I2 & I &!I) (!I3 &!I2 & I & I) (!I3 & I2 &!I &!I) (!I3 & I2 &!I & I) (!I3 & I2 & I &!I) (!I3 & I2 & I & I) (I3 &!I2 &!I &!I) (I3 &!I2 &!I & I) (I3 &!I2 & I &!I) (I3 &!I2 & I & I); module o5(o5, i, i, i2, i3, i4); input i4, i3, i2, i; output o5; assign o5 = (!I3 &!I2 &!I & I) (!I3 &!I2 & I &!I) (!I3 &!I2 & I & I) (!I3 & I2 &!I &!I) (!I3 & I2 &!I & I) (!I3 & I2 & I &!I) (!I3 & I2 & I & I) (I3 &!I2 &!I &!I) (I3 &!I2 &!I & I) (I3 &!I2 & I &!I) (I3 &!I2 & I & I) (I3 & I2 &!I &!I) (I3 & I2 & I & I);
7 module o6(o6, i, i, i2, i3, i4); input i4, i3, i2, i; output o6; assign o6 = (!I3 & I2 & I &!I) (!I3 & I2 & I & I) (I3 &!I2 &!I &!I) (I3 & I2 & I &!I) (I3 & I2 & I & I); c. Develop the minimized gate-level implementation using the K-map method, minimizing each K-map independently. O O = I4 + I3 O O = + I3 I + I3 I2 O2 O2 = I4 I3 + I4 + I2 + I3 O3
8 O3 = I3 I2 + I4 I3 + I4 + I3 O4 O4 = + I4 I3 + I2 I4 O5 O5 = + I4 I3 + + I2 I I3 + I4 I O6 O6 = I2 I + I2 I3
9 d. Repeat (c), but this time, minimize so as to exploit shared product terms wherever possible, as though the implementation target is a PLA. (There may be several solutions) O O = + + I3 O O = + I3 I2 I + I3 + I3 O2 O2 = I4 I3 + I4 + I2 + I3 O3 O3 = I3 I2 I + I3 I2 I + I4 + I3
10 O4 O4 = + I4 I3 + I2 I4 O5 O5 = + I4 I3 + + I2 I I3 + I4 I O6 O6 = I2 I + I2 I3 e. How does the complexity of your answers to (c) and (d) compare? Which is simpler and why? What criteria are you using to measure the complexity of these two different implementations? Although D may not be the most simplified sum of products expression, it will be easier to implement than C because many of the terms may be shared between the outputs. 3. Your textbook presents the concept of a Master-Slave flip-flop, constructed from two cascaded stages of R-S flip-flops (see Figure 6.8 on page 269). a. Master-Slave flip-flops implemented in this way exhibit the phenomena of ones catching. Explain what it is and why it happens. Is it possible for a Master-Slave flip-flop to catch zeros? Justify your answer! One s catching means the output of the Master-Slave flip-flop will be a, until a is sensed at the input. Once this happens, the output will become at the next clock cycle and remain at for the remaining clock cycles or until a reset signal is received. zero-catcher can be constructed
11 by inverting the input of the one-catcher b. Suppose that you implement a Master-Slave flip-flop as two cascaded D flip-flops, the first stage a positive edge triggered D FF and the second stage a negative edge triggered D FF. Draw a timing chart with a clock waveform and a D input that oscillates from to or to each time the clock is low. Make sure you show how the two flip-flops outputs change in response to input and clock changes. D Q' D2 Q2' Q Q2 D Q Q2 4. Your textbook presents a negative edge-triggered D flip-flop using NOR gates (see Figure 6.24 on page 272). a. Implement a positive-edge triggered D flip-flop function using NAND gates only. A D Q Q' A'
12 b. Explain the timing behavior of this circuit. Label your internal circuit nodes, show their waveforms on the timing chart, and use these waveforms to briefly explain why the triggering works. D A Q A changes on the rising edge of, and Q changes on the falling edge of. 5. Design a 3-bit counter that implements the following sequence:,,,,,,,, and repeat. Design the counter with a reset input that causes the counter to enter the state. a. Write a Verilog specification for this counter. module weirdcounter(clk, rst, out); parameter s = 3 b; parameter s = 3 b; parameter s2 = 3 b; parameter s3 = 3 b; parameter s4 = 3 b; parameter s5 = 3 b; parameter s6 = 3 b; parameter s7 = 3 b; input clk, rst; output [2:] out; reg out; reg [2:] ps, ns; assign out = ps; always@(posedge clk) begin if(rst) ps <= s; else ps <= ns; end always@(ps) case(ps) s: ns = s;
13 end s: ns = s2; s2: ns = s3; s3: ns = s4; s4:ns = s5; s5: ns=s6; s6:: ns=s; default: ns = s; b. Design the next state functions and minimize for PLA-based implementation. PS PS NS2 NS NS (The PLA optimized form is the same as the minimized Sum-of Products form) NS PS PS NS = PS PS + PS + PS NS PS PS NS = PS PS + PS + PS NS2 PS PS NS2 = PS PS + PS + PS
14 c. Show how to implement this counter using 2: multiplexers and D flipflops only. You may assume that the D FFs have a reset input. NS2 D Q CONTROL HARDWARE (See details below) RESET Q' ' NS D Q PS RESET Q' PS' NS D Q PS RESET Q' PS' CONTROL HARDWARE NS NS PS PS' PS PS' PS PS' PS PS' NS2 PS PS' PS PS' d.
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