4 of 40. Multi-ASIC reset synchronization Good Multi-Flip-Flop. Synthesis issues with reset nets. 3 of 40. Synchronous Resets? Asynchronous Resets?
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1 Synchronous Resets? Asynchronous Resets? I am so confused! How will I ever know which to use? &OLIIRUG(&XPPLQJV 'RQLOOV 6XQEXUVW'HVLJQ,Q /&'(QJLQHHULQJ OLII#VXQEXUVWGHVLJQRP PLOOV#OGPHQJRP ZZZVXQEXUVWGHVLJQRP ZZZOGPHQJRP Bad Multi-lip-lop oding Style 3 of Problem: dissimilar flip-flops in the same always block module badstyle (q2, d,, ); output q2; input d,, ; reg q2, q1; d BAD PARTITIONING Style creates EXTRA LOGI q1 ld q2 ) if (!) q1 <= 1'b; else begin q1 <= d; q2 <= q1; end endmodule q2 is only loaded if is high becomes a "load-data" signal VHDL model included in the paper Agenda "Simple Little Resets Paper" 2 of lip-flop coding styles Synchronous resets Asynchronous resets Design or Test (DT) considerations Reset-buffer tree Synthesis issues with reset nets Multi-clock resets Multi-ASI reset synchronization Good Multi-lip-lop oding Style of Solution: put dissimilar flip-flops in separate always blocks module goodstyle (q2, d,, ); output q2; input d,, ; reg q2, q1; d Good partitioning - no extra logic q1 q2 ) if (!) q1 <= 1'b; else q1 <= d; ) q2 <= q1; endmodule Note: To model sequential logic use nonblocking assignments q2 is loaded on every posedge No reset on the follower flip-flop VHDL model included in the paper
2 Modeling Synchronous Resets Synchonous reset: is not in the sensitivity list module ctrsr ( q, co, d, ld,, ); output [7:] q; output co; input [7:] d; input ld,, ; reg [7:] q; reg co; ) if (!) {co,q} <= 9'b; // sync reset else if (ld) {co,q} <= d; // sync load else {co,q} <= q + 1'b1; // sync increment endmodule VHDL model included in the paper VHDL versions would have required too many slides to show the same models or a microscopic font Modeling Asynchronous Resets Asynchonous reset: is in the sensitivity list module ctrar ( q, co, d, ld,, ); output [7:] q; output co; input [7:] d; input ld,, ; reg [7:] q; reg co; or negedge ) if (!) {co,q} <= 9'b; // async reset else if (ld) {co,q} <= d; // sync load else {co,q} <= q + 1'b1; // sync increment endmodule VHDL model included in the paper 5 of 7 of Synthesizing Synchronous Resets is in the sensitivity list "1" d ld + 9 i i1 sel Only can trigger the always block Synchronous (added path delay) Only can cause the outputs to change & ld are not in the sensitivity list (synchronous to ) ) if (!) {co,q} <= 9'b; else if (ld) {co,q} <= d; else {co,q} <= q + 1'b1; Synthesizing Asynchronous Resets "1" + d ld 9 i i1 9 sel1 1 Only or can cause the outputs to change Asynchronous (no extra path delay) or can trigger the always block or negedge ) if (!) {co,q} <= 9'b; else if (ld) {co,q} <= d; else {co,q} <= q + 1'b1; asynchronous, in the sensitivity list synchronous ld not in the sensitivity list q co q co 6 of of
3 Synchronous Resets Advantages & Disadvantages Advantages Easier to work with cycle based simulators (according to the RMM) Typically recommended for DT design Glitch filtering from reset combinational logic (to make up for poor design practices) Glitch filtering if reset is in a mission-critical application Disadvantages May not be able to come out of Unknown-X during simulation Adds delay to data path Asynchronous Reset Problem Problem: Asynchronous reset removal Will reset removal meet recovery time specification? t pd t rec is asynchronous to Potential problem: flip-flop could go metastable on reset-release if reset removal violates clock set/hold time 9 of 11 of Asynchronous Resets Advantages & Disadvantages 1 of Advantages Reset is immediate No problem related to Unknown-X-propagation in design simulation Does not interfere or add extra delay to the data path Very easy to implement Disadvantages Asynchronous signal - can go metastable on release Noisy reset line could cause unwanted resets DT designs prefer synchronous designs (??)... but there is a solution!... but this can be filtered... but this can be fixed 12 of Reset Synchronizer Advantage: Asynchronous reset assertion Advantage: Synchronous reset removal When reset is de-asserted asynchronously master is removed synchronously master pad_ pad_ Asynchronous reset assertion Guideline: EVERY ASI USING AN ASYNHRONOUS RESET SHOULD INLUDE A RESET SYNHRONIZER IRUIT!! Reset distribution buffer tree
4 Synchronous Reset Removal Solution 13 of Advantage: Synchronous reset removal Predictable reset removal to meet recovery time specification! t -q t pd t rec Guideline: EVERY ASI USING AN ASYNHRONOUS RESET SHOULD INLUDE A RESET SYNHRONIZER IRUIT!! master Synopsys Reset Switches 15 of Important reset-net switches Standard switches for reset nets set_drive set_dont_touch_network To set -resistance on a reset net (ESNUG #355, Item 2 & ESNUG #356, Item ) set_resistance Apply -resistance to the reset port with a custom wireload model in which resistance= set_wire_load -port_list reset Pre-Synopsys do both Added to v21.: to create ideal nets and force no timing updates, no delay optimization, and no DR fixing - use with set_false_path & set_disable_timing (SolvNet, Synthesis-7, Physical_Synthesis-231, Synthesis-219) set_ideal_net set_false_path & set_disable_timing Synopsys set_ideal_net removes transition time propagation oming to Synopsys set ideal "network" Reset Synchronizer Verilog RTL ode 1 of master Guideline: EVERY ASI USING AN ASYNHRONOUS RESET SHOULD INLUDE A RESET SYNHRONIZER IRUIT!! module reset_synchronizer (master,, ); output master; input, ; reg, rff1; or negedge ) if (!) {master,rff1} <= 2'b; else {master,rff1} <= {rff1,1'b1}; endmodule oncatenation makes for efficient coding of the reset synchronizer Asynchronous reset assertion (on negedge ) Synchronous reset removal (on posedge ) lock & Reset Loading 16 of lock distribution tree master Reset distribution tree NOTE: # clock loads ~ # reset loads!!
5 Reset Buffer Tree Driven from a Leaf-Driver lock lock distribution tree instantiation Sometimes it is difficult to tap into the center of the clock tree Resetsynchronizer is driven from a fanned-out clock master Reset distribution tree (reset must be removed before the next rising clock edges) Asynchronous Reset Glitch iltering Glitches on the input might cause stray resets Solution: glitch-filter on the input glitch delayed reset d f master filtered d delay f Low-asserted asynchronous reset Delayed reset De Morgan equivalent "or"-gate iltered reset 17 of 19 of Reset Buffer Tree Driven from a Source-Driver lock 1 of lock distribution tree instantiation Resetsynchronizer is driven from a source clock driver master Reset distribution tree (reset must not be removed before the rising clock edges) Asynchronous Reset & DT 2 of The process of applying the ATPG vectors to create a test is based on: scanning a known state into all the flip-flops in the chip switching the flip-flops from scan shift mode, to functional data input mode applying one functional clock switching the flip-flops back to scan shift mode to scan out the result of the one functional clock while scanning in the next test vector During the above process, the designer must insure that under NO ONDITIONS, an asynchronous set/reset can occur and thus corrupt the input vectors The asynchronous reset must be held in the inactive state during the entire test What about coverage to the portion of the chip controlled by the reset?
6 Asynchronous Reset & DT an I use an asynchronous reset with Design or Test (DT) strategies? scan in all ones into the scan chain issue and release the asynchronous reset scan out the result and scan in all zeros issue and release the reset scan out the result set the reset input to the non reset state and then apply the ATPG generated vectors Multiple lock Domains Synchronized Reset Removal This technique works to force ordered reset removal 1st a b c 21 of This will test for the reset line attached to either the asynchronous set or reset of a flip-flop 23 of a 2nd Resets are removed in an ordered sequence b 3rd c Multiple lock Domains Non-Synchronized Reset Removal 22 of This technique works if small reset removal timing differences are not a problem a a All resets removed at nearly the same time b b c c What About Synchronizing Multiple ASIs? 2 of Synchronizing reset removal on the same ASI is easily handled How do we precisely synchronize reset removal on multiple ASIs? We need to consider: Board layout and trace delays Mixture of fast and slow ASIs (due to process differences)
7 25 of Actual Design Solution High speed data acquisition product our interleaved identical ASIs each ASI samples the same data stream at phased differently from the other ASIs each ASI outputs a data value and a memory address to be stored the correct sample from each ASI must be correctly ordered and stored into address address counters are free-running after reset How can the four ASIs be reliably synchronized and sequenced to a common reset removal? One solution - "digital calibration" Valid "Ramp" Signal 27 of 1 Synchronizing a "Ramp" (correct synchronization) Synchronized example: input data "ramp" Data is being sampled by four different ASIs A E ASI#1 Sample #1 ASI#2 Sample #1 ASI#3 Sample #1 ASI# Sample #1 ASI#1 Sample #2 ASI#2 Sample #2 ASI#3 Sample #2 ASI# Sample #2 ASI#1 Sample #3 ASI#2 Sample #3 ASI#3 Sample #3 ASI# Sample #3 ASI#1 Sample # ASI#2 Sample # ASI#3 Sample # ASI# Sample # RAM1 Sample #1 RAM2 Sample #1 RAM3 Sample #1 RAM Sample #1 RAM1 Sample #2 RAM2 Sample #2 RAM3 Sample #2 RAM Sample #2 RAM1 Sample #3 RAM2 Sample #3 RAM3 Sample #3 RAM Sample #3 RAM1 Sample # RAM2 Sample # RAM3 Sample # RAM Sample # Synchronizing a "Ramp" (flawed synchronization) Problem example: input data "ramp" Data sampling is not synchronized A E ASI#1 Sample #1 ASI# Sample #1 ASI#1 Sample #2 ASI#3 Sample #1 ASI# Sample #2 ASI#1 Sample #3 ASI#2 Sample #1 ASI#3 Sample #2 ASI# Sample #3 ASI#1 Sample # ASI#2 Sample #2 ASI#3 Sample #3 ASI# Sample # RAM1 Sample #1 RAM2 Sample #1 RAM3 Sample #1 RAM Sample #1 RAM1 Sample #2 RAM2 Sample #2 RAM3 Sample #2 RAM Sample #2 RAM1 Sample #3 RAM2 Sample #3 RAM3 Sample #3 RAM Sample #3 RAM1 Sample # RAM2 Sample # RAM3 Sample # RAM Sample # A E E 5 6 A 26 of 2 of ASI#1 Sample #1 ASI#2 Sample #1 ASI#3 Sample #1 ASI# Sample #1 ASI#1 Sample #2 ASI#2 Sample #2 ASI#3 Sample #2 ASI# Sample #2 ASI#1 Sample #3 ASI#2 Sample #3 ASI#3 Sample #3 ASI# Sample #3 ASI#1 Sample # ASI#2 Sample # ASI#3 Sample # ASI# Sample # ASI#1 Sample #5 ASI#2 Sample #5 ASI#3 Sample #5 ASI# Sample #5 ASI#1 Sample #6 ASI#2 Sample #6
8 Invalid "Ramp" Signal 29 of ASI#1 Sample #1 ASI#2 Sample #1 ASI#3 Sample #1 ASI# Sample #1 ASI#1 Sample #2 ASI#2 Sample #2 ASI#3 Sample #2 ASI# Sample #2 ASI#1 Sample #3 ASI#2 Sample #3 ASI#3 Sample #3 ASI# Sample #3 ASI#1 Sample # ASI#2 Sample # ASI#3 Sample # ASI# Sample # ASI#1 Sample #5 ASI#2 Sample #5 ASI#3 Sample #5 ASI# Sample #5 ASI#1 Sample #6 ASI#2 Sample #6 1 Multi-ASI Reset? How? datain 1 ASI #1 3 ASI #3 1- have slightly difference phases 2 ASI #2 ASI # Reset sync net reset_n reset_n cannot be used to synchronize the ASIs 31 of addrout1 dataout1 addrout3 dataout3 addrout dataout addrout2 dataout2 Synchronization Problem Starting the Address ounters 3 of After removing reset, all address counters start incrementing Address counters are free running until a "trigger" halts data acquisition Data values are being fanned-out to multiple memory devices Waveform reconstruction happens as the data is read back from memory The data must be correctly sequenced in memory The address counters must: startup in the correct sequence all start within a 1-cycle clock period Otherwise, data storage and retrieval will be incorrectly sequenced Digital alibration 32 of Use programmable delays in each ASI to synchronize startup of each ASI after reset removal A range of working programmable delays must be determined choose the middle of the range Board layout (sync-signal trace lengths) impacts required delays Process variations impacts delays of each ASI Repeated ramp-capture to calibrate valid ranges for each ASI
9 Synchronization Logic 33 of Implementation shown on next slide addrcnt pad_sync_in sync_in Programmable Delay sync_dly mstr pad_ pad_master master sync_out pad_sync_out Externally connect sync_out to sync_in on the master ASI Tied high for Master ASI Tied low for Slave ASIs Dangling output for ASIs Inter-ASI Synchronization sync_out / sync_in When tied high: Master ASI When tied low: Slave ASI 35 of master 1 ASI #1 3 ASI #3 sync_in sync_out sync_in 2 ASI #2 ASI # Reset sync net sync_in sync_in reset_n Programmable Delay 3 of sync_in Load the delay setting from a processor interface sdly sdly1 sdly2 sdly3 sdly sdly5 sdly6 sdly7 Delay Select Reg sdly7 sdly sdly9 sdly1 sdly11 sdly12 sdly13 sdly1 sdly15 delaysel[3:] sdly sdly1 sdly2 sdly3 sdly sdly5 sdly6 sdly7 sdly sdly9 sdly1 sdly11 sdly12 sdly13 sdly1 sdly15 i i1 i2 i3 i i5 i6 i7 i i9 i1 i11 i12 i13 i1 y muxsel sync_dly datain Multiple ASI Synchronization omplete Block Diagram When tied high: Master ASI master When tied low: Slave ASI 36 of addrout1 dataout1 addrout3 ASI #1 ASI #3 dataout3 OS or PLL lock Generator I sync_in sync_out sync_in addrout ASI #2 ASI # dataout Reset sync net sync_in sync_in reset_n addrout2 dataout2
10 alibration ASI#2 - Early Startup 37 of ASI#1 Sample #1 ASI#2 Sample #1 ASI#1 Sample #2 ASI#2 Sample #2 ASI#1 Sample #3 ASI#2 Sample #3 ASI#1 Sample # ASI#2 Sample # ASI#1 Sample #5 ASI#2 Sample #5 ASI#1 Sample #6 ASI#2 Sample #6 ASI#2 started sampling too soon ASI# ASI#2 samples were captured early ASI#2 - (Early) early correct alibration ASI#2 - Synchronized Startup 3 of ASI# ASI#2 samples were captured correctly ASI# correct ASI#1 Sample #1 ASI#2 Sample #1 ASI#1 Sample #2 ASI#2 Sample #2 ASI#1 Sample #3 ASI#2 Sample #3 ASI#1 Sample # ASI#2 Sample # ASI#1 Sample #5 ASI#2 Sample #5 ASI#1 Sample #6 ASI#2 Sample #6 alibration ASI#2 - Late Startup 39 of hoose (half way between 5 & 11) ASI#1 Sample #1 ASI#2 Sample #1 ASI#1 Sample #2 ASI#2 Sample #2 ASI#1 Sample #3 ASI#2 Sample #3 ASI#1 Sample # ASI#2 Sample # ASI#1 Sample #5 ASI#2 Sample #5 ASI#1 Sample #6 ASI#2 Sample #6 ASI#2 started sampling too late ASI# ASI#2 samples were captured late ASI# (Late) correct late onclusions of The "Reset Synchronizer": Offers the advantages of asynchronous resets Offers the advantages of synchronous reset removal Works well with DT techniques "Digital alibration" A viable technique to synchronize reset removal across multiple ASIs
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