Configuring FLASHlogic Devices
|
|
- Mercy McGee
- 5 years ago
- Views:
Transcription
1 Configuring FLASHlogic s April 995, ver. Application Note 45 Introduction The Altera FLASHlogic family of programmable logic devices (PLDs) is based on CMOS technology with SRAM configuration elements. This technology supports in-circuit reconfigurability (ICR) via the Joint Test Action Group (JTAG) interface without requiring any special programming voltages. FLASHlogic devices can be reconfigured with the FLASHlogic Download Cable or an intelligent host. Each FLASHlogic device has on-board, non-volatile FLASH or EPROM memory that stores a single configuration. An external controller, such as a microcontroller or state machine, is required for reconfiguration. When the device is powered up, the configuration information is written into the on-board SRAM and the device is ready to perform its intended function. The FLASH or EPROM memory is programmed with Altera s PENGN software, which is not discussed in this application note. For more information on programming FLASHlogic devices, refer to the PLDshell Plus/PLDasm User s Guide V5.0, available from Altera Literature at (408) JEDJTAG Operation To reconfigure a FLASHlogic device, you must first use Altera s PLDshell Plus software or third-party software to create a JEDEC (.jed) that contains the FLASHlogic device configuration information. You can then process the file with Altera s JEDJTAG software and use it to reconfigure the device. The JEDJTAG software is included with PLDshell Plus. The Altera MAX+PLUS II development system provides programming-only support for FLASHlogic devices. Full device support is planned for the second half of 995. JEDJTAG converts a JEDEC into one of three different output formats: a Bit (.bit), a Binary (.bin), or a Hexadecimal (Intel- Format) (.hex). The output format you choose depends on the type of controller used to reconfigure the device. The controller then uses the selected output format to send the configuration data to the FLASHlogic device via the JTAG interface. Table describes the JEDJTAG input files. f Go to the PLDshell Plus/PLDasm User s Guide V5.0 for additional information on the FLASHlogic Download Cable, the JEDJTAG software, and FLASHlogic device configuration. Altera Corporation A-AN-045-0
2 Table. JEDJTAG Input s String Description (.sdl) <file name>.jed jtag.dvc Description Describes the JTAG chain, which is the series of connected devices on a circuit board. JEDEC (s) generated with PLDshell Plus software can be used to configure the FLASHlogic devices. Library file, included with the PLDshell Plus software, that contains a description of several common JTAG devices. You can easily add information for other JTAG devices from device data sheets or from the appropriate Boundary Scan Description Language (BSDL). Instructions on adding devices are included in the jtag.dvc file. The JEDJTAG software produces one of the output formats shown in Table. Table. JEDJTAG Output s <file name>.bit <project name>.bin <project name>.hex Description JEDJTAG intermediate file. JEDJTAG creates one Bit for each JEDEC, then compares the time stamps. If the JEDEC is more recent, JEDJTAG recreates the Bit. Bin containing the JEDJTAG stream of JTAG signals. This file is used to create a Hex or is sent to the computer s parallel port. The Bin is created from Bit s. Hex used for programming standard memory devices. To start the JEDJTAG software, type the following command at the DOS prompt: jedjtag <project name> 9 Figure shows a block diagram of JEDJTAG operation. Altera Corporation
3 Figure. JEDJTAG Block Diagram String Description.sdl Hex.hex ICR via Intelligent Host JEDEC.jed JEDJTAG Software Parallel Port Reconfiguration via FLASHlogic Download Cable Library jtag.dvc Binary.bin Custom Reconfiguration Scheme (i.e., Board Tester or Other Process) The String Description lists the JTAG device chain and any associated JEDEC s, as shown in the example.sdl file in Figure. Figure. String Description (example.sdl) In this example, a pipe character ( ) indicates a comment line. FILE: example.sdl -Simple Prototype Board { Port_Num Port_Type STRING 3 BIN_FILE Port_Num - for LPT: Port_Type must be PARALLEL_PORT or BIN_FILE Loc. Ref JEDEC DEVICE 0 U3 EPX780QC3 RIGHT.JED DEVICE U4 EPX780LC84 LEFT.JED DEVICE U TI_74BCT8373 } The STRING instruction in the String Description controls which operations JEDJTAG uses for the JTAG chain. To create a Hex or a Bin, specify the following: STRING 3 <file type> where 3 specifies the configuration option that enables you to generate a file, and <file type> is either HEX_FILE or BIN_FILE. Altera Corporation 3
4 To send the configuration via the PC s parallel port, you must specify parallel port instructions in the String Description as follows: STRING <parallel port> PARALLEL_PORT where <parallel port> is to specify LPT and to specify LPT. The example.sdl file shown in Figure describes the JTAG device chain shown in Figure 3. In this example, does not have a JEDEC, and will not be reconfigured by JEDJTAG. Figure 3. JTAG Chain (example.sdl) External Connector TDI TDO TDI TDO TMS & TCK TDI TDO 0 Configuring FLASHlogic s Using ICR In-circuit reconfigurability (ICR) enables you to reconfigure devices that are already soldered onto a printed circuit board. For example, you can use the FLASHlogic Download Cable or an intelligent host to change the logic in add-on card applications that interface with different buses. In-Circuit Reconfiguration with the FLASHlogic Download Cable If a printed circuit board has a JTAG chain with a header, you can use the FLASHlogic Download Cable to reconfigure devices in-circuit. 4 Altera Corporation
5 To use the FLASHlogic Download Cable:. Connect one end of the cable to your PC s parallel port, and connect the other end of the cable to the JTAG header on your printed circuit board.. Create the JEDEC (s) for the design. 3. Create a String Description that describes the JTAG chain. Be sure to include the appropriate parallel port STRING instruction. 4. Run JEDJTAG. This software generates a Bin and downloads it to your board to reconfigure the FLASHlogic device(s). In-Circuit Reconfiguration with an Intelligent Host When you reconfigure a device using an intelligent host, your system must have the appropriate storage capability, such as ROM, external peripherals, or disk drives. To reconfigure a device with an intelligent host:. Create the JEDEC (s) for the design.. Create a String Description that describes the JTAG chain. Be sure to include the appropriate Hex STRING instruction. 3. Run JEDJTAG to create the Hex. 4. Program the storage memory with the Hex. 5. Develop software using the guidelines specified by your microcontroller manufacturer to download the configuration data from the storage device into the FLASHlogic device(s). You can use almost any combination of CPU and memory to reconfigure FLASHlogic devices in-circuit. For example, you can use an Intel 87C5 microprocessor as an intelligent host. See Figure 4. Altera Corporation 5
6 Figure 4. Implementing ICR with an Intelligent Host 87C5 Memory Hex (.hex) JTAG FLASHlogic FLASHlogic The interconnect between the CPU and the JTAG chain requires four I/O signals (TMS, TCK, TDI, and TDO), plus a RESET signal, if necessary. See Figure 5. Figure 5. Sample Schematic for Implementing ICR with an Intelligent Host MHz C Y 33 pf 4 37 V CC LED DS R3 3 C 33 pf V CC R 5 S XTAL XTAL 0.5 k V CC 35 R9 EA# C 4.7 µf XTAL XTAL EA-/V PP C5-Reset 0 Reset R.5 AL/Prog- 33 ALE P00/AD0 43 ADO0 P0-AD 4 ADO P0/AD 4 ADO P03/AD4 40 ADO3 P04/AD5 39 ADO4 P05/AD5 38 ADO5 P06/AD6 37 ADO6 P07/AD7 36 ADO7 4 A08 P0/A8 5 A09 P/A9 6 A0 P/A0 7 A P3/A 8 A P4/A 9 A3 P5/A3 30 A4 P6/A4 3 A5 P7/A5 87C5FA 3 PSEN- OC- C D 3 D 4 3D 5 4D 6 5D 7 6D 8 7D 9 8D 74HCT573 9 AO0 Q 8 AO Q 7 AO 3Q 6 AO3 4Q 5 AO4 5Q 4 AO5 6Q 3 AO6 7Q AO7 8Q FLASH Memory 56KX8 CE V 4 PP OE 3 WE A0 A I/O 3 0 A I/O 4 9 A3 I/O3 5 8 A4 I/O4 7 7 A5 I/O5 8 6 A6 I/O6 9 5 A7 I/O7 0 7 A8 6 A9 3 A0 5 A 4 A 8 A3 9 A4 3 A5 I/O8 JTAG Chain of FLASHlogic s LED_R RESET_R# TDI_Port_R TDO_Port_R TMS_R TCK_R P0/T 3 P/TEX 4 P/ECI 5 P3/CEX0 6 P4/CEX 7 P5/CEX 8 P6/CEX3 9 P7/CEX4 P30/RXD P3/TDX 3 P3/IN0-4 P33/IN - 5 P34/T0 6 P35/T 7 P36/WR - 8 P37/RD - 9 Flash-CE# A6 A7 Write# Read# 30 A6 A7 V CC C4 0. µf C5 C6 0. µf 0. µf C7 0. µf 6 Altera Corporation
7 Figure 6 shows the code used by the 87C5 microprocessor to control the JTAG chain. Figure 6. Hex Download Algorithm for the 87C5 (Part of ) ;******************************************************************** ;* JTAG STAND-ALONE LOADER CODE ;** ;* This program usually executes in an embedded controller from an ;* executable memory bank. It transmits data from a local nonvolatile ;* data memory bank to a JTAG IEEE 49. chain, typically to load the ;* SRAM control memory in the FLASHlogic devices in the chain. ;** ;* Data is stored in the non-volatile memory off-line, e.g., with a PROM ;* programmer. It is formatted as a JTAG data stream. Each byte ;* contains TDO/TMS data for 4 TCK cycles. Bit 0 of each byte is the ;* first TDO, bit is the first TMS, bit is the second TDO, etc. ;* No inversion occurs between memory and TMS/TDO. ;** ;* The first four bytes in the non-volatile memory specify the Ending ;* Address +. The least significant byte is at data address 0. The ;* JTAG data stream starts at data address 4. ;** ;* Data is automatically downloaded each time the embedded controller ;* is reset, including power-on. ;******************************************************************** ; Initialization SET LED# port bit ; turn off LED DELAY (500) ; delay 500 ms. ; Give time for host JTAG string to completely power-up before beginning. CLR TICK port bit ; init TCK to LOW CLR RESET# port bit ; init RESET# to LOW (activate host RESET) CLR CE# port bit ; enable FLASH memory CLR LED# port bit ; turn on LED ; Transmit data adrs = 0; initialize data address and last-adrs = (adrs) ; last address + (these are 3 bit values) adrs = adrs + 4; WHILE (adrs < last_adrs) ( ; loop until all data is moved from memory to JTAG chain ; output lst TMS/TDO MOVE bit 0 of (adrs) to TDO port bit MOVE bit of (adrs) to TMS port bit SET TCK port bit ; pulse TCK CLR TCK port bit Altera Corporation 7
8 Figure 6. Hex Download Algorithm for the 87C5 (Part of ) ; output nd TMS/TDO MOVE bit of (adrs ) to TDO port bit MOVE bit 3 of (adrs) to TMS port bit SET TCK port bit ; pulse TCK CLR TCK port bit ; output 3rd TMS/TDO MOVE bit 4 of (adrs) to TDO port bit MOVE bit 5 of (adrs) to TMS Port bit SET TCK port bit ; pulse TCK CLR TCK port bit ; output 4th TMS/TDO MOVE bit 6 of (adrs) to TDO port bit MOVE bit 7 of (adrs) to TMS port bit SET TCK port bit ; pulse TCK CLR TCK port bit adrs = adrs + ) ; Completion SET RESET# port bit ; release host SET LED# port bit ; turn off LED SET CE# port bit ; disable memory to save power SLEEP ; disable embedded controller to save power Conclusion Altera s FLASHlogic family of PLDs provides the features and flexibility designers need for many of today s applications. These devices can be reconfigured in-circuit, allowing quick and easy design iterations and field upgrades. 60 Orchard Parkway San Jose, CA (408) Applications Hotline: (800) 800-EPLD Customer Marketing: (408) Literature Services: (408) Altera, MAX, MAX+PLUS, and FLEX are registered trademarks of Altera Corporation. The following are trademarks of Altera Corporation: MAX+PLUS II, AHDL, and FLEX 0K. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog and Verilog-XL are registered trademarks of Cadence Design Systems, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Synopsys is a registered trademark of Synopsys, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright 996 Altera Corporation. All rights reserved. 8 Altera Corporation Printed on Recycled Paper.
SignalTap Plus System Analyzer
SignalTap Plus System Analyzer June 2000, ver. 1 Data Sheet Features Simultaneous internal programmable logic device (PLD) and external (board-level) logic analysis 32-channel external logic analyzer 166
More information12. IEEE (JTAG) Boundary-Scan Testing for the Cyclone III Device Family
December 2011 CIII51014-2.3 12. IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family CIII51014-2.3 This chapter provides guidelines on using the IEEE Std. 1149.1 boundary-scan test
More informationSignalTap Analysis in the Quartus II Software Version 2.0
SignalTap Analysis in the Quartus II Software Version 2.0 September 2002, ver. 2.1 Application Note 175 Introduction As design complexity for programmable logic devices (PLDs) increases, traditional methods
More informationIn-System Programmability Guidelines
In-System Programmability Guidelines May 1999, ver. 3 Application Note 100 Introduction As time-to-market pressures increase, design engineers require advanced system-level products to ensure problem-free
More information3. Configuration and Testing
3. Configuration and Testing C51003-1.4 IEEE Std. 1149.1 (JTAG) Boundary Scan Support All Cyclone devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan
More informationM89 FAMILY In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems for MCUs
In-System Programmable (ISP) Multiple-Memory and Logic FLASH+PSD Systems for MCUs DATA BRIEFING Single Supply Voltage: 5V±10% for M9xxFxY 3 V (+20/ 10%) for M9xxFxW 1 or 2 Mbit of Primary Flash Memory
More informationImplementing Audio IP in SDI II on Arria V Development Board
Implementing Audio IP in SDI II on Arria V Development Board AN-697 Subscribe This document describes a reference design that uses the Audio Embed, Audio Extract, Clocked Audio Input and Clocked Audio
More informationUniversity Program Design Laboratory Package
University Program Design Laboratory Package August 1997, ver. 1 User Guide Introduction The University Program Design Laboratory Package was designed to meet the needs of universities teaching digital
More informationUniversity Program Design Laboratory Package
University Program Design Laboratory Package November 1999, ver. 1.02 User Guide Introduction The University Program Design Laboratory Package was designed to meet the needs of universities teaching digital
More informationUpgrading a FIR Compiler v3.1.x Design to v3.2.x
Upgrading a FIR Compiler v3.1.x Design to v3.2.x May 2005, ver. 1.0 Application Note 387 Introduction This application note is intended for designers who have an FPGA design that uses the Altera FIR Compiler
More informationConcurrent Programming through the JTAG Interface for MAX Devices
Concurrent through the JTAG Interface for MAX Devices February 1998, ver. 2 Product Information Bulletin 26 Introduction Concurrent vs. Sequential In a high-volume printed circuit board (PCB) manufacturing
More informationComparing JTAG, SPI, and I2C
Comparing JTAG, SPI, and I2C Application by Russell Hanabusa 1. Introduction This paper discusses three popular serial buses: JTAG, SPI, and I2C. A typical electronic product today will have one or more
More informationRemote Diagnostics and Upgrades
Remote Diagnostics and Upgrades Tim Pender -Eastman Kodak Company 10/03/03 About this Presentation Motivation for Remote Diagnostics Reduce Field Maintenance costs Product needed to support 100 JTAG chains
More informationUsing the XC9500/XL/XV JTAG Boundary Scan Interface
Application Note: XC95/XL/XV Family XAPP69 (v3.) December, 22 R Using the XC95/XL/XV JTAG Boundary Scan Interface Summary This application note explains the XC95 /XL/XV Boundary Scan interface and demonstrates
More informationSAU510-USB ISO PLUS v.2 JTAG Emulator. User s Guide 2013.
User s Guide 2013. Revision 1.00 JUL 2013 Contents Contents...2 1. Introduction to...4 1.1 Overview of...4 1.2 Key Features of...4 1.3 Key Items of...5 2. Plugging...6 2.1. Equipment required...6 2.2.
More informationEntry Level Tool II. Reference Manual. System Level Solutions, Inc. (USA) Murphy Avenue San Martin, CA (408) Version : 1.0.
Entry Level Tool II Reference Manual, Inc. (USA) 14100 Murphy Avenue San Martin, CA 95046 (408) 852-0067 http://www.slscorp.com Version : 1.0.3 Date : October 7, 2005 Copyright 2005-2006,, Inc. (SLS) All
More informationThe ASI demonstration uses the Altera ASI MegaCore function and the Cyclone video demonstration board.
April 2006, version 2.0 Application Note Introduction A digital video broadcast asynchronous serial interace (DVB-) is a serial data transmission protocol that transports MPEG-2 packets over copper-based
More informationUniversity Program Design Laboratory Package
University Program Design Laboratory Package October 2001, ver. 2.0 User Guide Introduction The University Program (UP) Design Laboratory Package was designed to meet the needs of universities teaching
More informationMemec Spartan-II LC User s Guide
Memec LC User s Guide July 21, 2003 Version 1.0 1 Table of Contents Overview... 4 LC Development Board... 4 LC Development Board Block Diagram... 6 Device... 6 Clock Generation... 7 User Interfaces...
More informationSection 24. Programming and Diagnostics
Section. and Diagnostics HIGHLIGHTS This section of the manual contains the following topics:.1 Introduction... -2.2 In-Circuit Serial... -2.3 Enhanced In-Circuit Serial... -5.4 JTAG Boundary Scan... -6.5
More informationJTAG Boundary- ScanTesting
JTAG Boundary- ScanTesting In Altera evices November 995, ver. 3 Application Note 39 Introduction As printed circuit boards (PCBs) become more complex, the need for thorough testing becomes increasingly
More information11. JTAG Boundary-Scan Testing in Stratix V Devices
ecember 2 SV52-.4. JTAG Boundary-Scan Testing in Stratix V evices SV52-.4 This chapter describes the boundary-scan test (BST) features that are supported in Stratix V devices. Stratix V devices support
More informationUniversal ByteBlaster
Universal ByteBlaster Hardware Manual June 20, 2005 Revision 1.1 Amfeltec Corp. www.amfeltec.com Copyright 2008 Amfeltec Corp. 35 Fifefield dr. Maple, L6A 1J2 Contents Contents 1 About this Document...
More informationSection 24. Programming and Diagnostics
Section. Programming and Diagnostics HIGHLIGHTS This section of the manual contains the following topics:.1 Introduction... -2.2 In-Circuit Serial Programming... -3.3 Enhanced In-Circuit Serial Programming...
More informationSaving time & money with JTAG
Saving time & money with JTAG AltiumLive 2017: ANNUAL PCB DESIGN SUMMIT Simon Payne CEO, XJTAG Ltd. Saving time and money with JTAG JTAG / IEEE 1149.X Take-away points Get JTAG right from the start Use
More informationInterfacing the TLC5510 Analog-to-Digital Converter to the
Application Brief SLAA070 - April 2000 Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP Perry Miller Mixed Signal Products ABSTRACT This application report is a summary of the
More informationTesting Sequential Logic. CPE/EE 428/528 VLSI Design II Intro to Testing (Part 2) Testing Sequential Logic (cont d) Testing Sequential Logic (cont d)
Testing Sequential Logic CPE/EE 428/528 VLSI Design II Intro to Testing (Part 2) Electrical and Computer Engineering University of Alabama in Huntsville In general, much more difficult than testing combinational
More informationJTAG Test Controller
Description JTAG Test Controller The device provides an interface between the 60x bus on the Motorola MPC8260 processor and two totally independent IEEE1149.1 interfaces, namely, the primary and secondary
More informationA Briefing on IEEE Standard Test Access Port And Boundary-Scan Architecture ( AKA JTAG )
A Briefing on IEEE 1149.1 1990 Standard Test Access Port And Boundary-Scan Architecture ( AKA JTAG ) Summary With the advent of large Ball Grid Array (BGA) and fine pitch SMD semiconductor devices the
More informationSerial Digital Interface Reference Design for Stratix IV Devices
Serial Digital Interface Reference Design for Stratix IV Devices AN-600-1.2 Application Note The Serial Digital Interface (SDI) reference design shows how you can transmit and receive video data using
More informationTools to Debug Dead Boards
Tools to Debug Dead Boards Hardware Prototype Bring-up Ryan Jones Senior Application Engineer Corelis 1 Boundary-Scan Without Boundaries click to start the show Webinar Outline What is a Dead Board? Prototype
More informationCHAPTER 3 EXPERIMENTAL SETUP
CHAPTER 3 EXPERIMENTAL SETUP In this project, the experimental setup comprised of both hardware and software. Hardware components comprised of Altera Education Kit, capacitor and speaker. While software
More informationAT18F Series Configurators. Application Note. Stand-alone or In-System Programming Applications for AT18F Series Configurators. 1.
Stand-alone or In-System Programming Applications for AT18F Series Configurators 1. Overview The AT18F Series Configurators, which include AT18F010-30XU (1M), AT18F002-30XU (2M), AT18F040-30XU (4M), and
More informationMSP430 JTAG / BSL connectors
MSP430 JTAG / BSL connectors (PD010A05 Rev-4: 23-Nov-2007) FAQ: Q: I have a board with the standard TI-JTAG pinhead. Can I use your programmer to flash my MSP430Fxx device? A: Yes. You can use any of our
More informationSMPTE-259M/DVB-ASI Scrambler/Controller
SMPTE-259M/DVB-ASI Scrambler/Controller Features Fully compatible with SMPTE-259M Fully compatible with DVB-ASI Operates from a single +5V supply 44-pin PLCC package Encodes both 8- and 10-bit parallel
More informationOverview of BDM nc. The IEEE JTAG specification is also recommended reading for those unfamiliar with JTAG. 1.2 Overview of BDM Before the intr
Application Note AN2387/D Rev. 0, 11/2002 MPC8xx Using BDM and JTAG Robert McEwan NCSD Applications East Kilbride, Scotland As the technical complexity of microprocessors has increased, so too has the
More informationthe Boundary Scan perspective
the Boundary Scan perspective Rik Doorneweert, JTAG Technologies rik@jtag.com www.jtag.com Subjects Economics of testing Test methods and strategy Boundary scan at: Component level Board level System level
More information7 Nov 2017 Testing and programming PCBA s
7 Nov 207 Testing and programming PCBA s Rob Staals JTAG Technologies Email: robstaals@jtag.com JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before
More informationCoLinkEx JTAG/SWD adapter USER MANUAL
CoLinkEx JTAG/SWD adapter USER MANUAL rev. A Website: www.bravekit.com Contents Introduction... 3 1. Features of CoLinkEX adapter:... 3 2. Elements of CoLinkEx programmer... 3 2.1. LEDs description....
More informationProduct Update. JTAG Issues and the Use of RT54SX Devices
Product Update Revision Date: September 2, 999 JTAG Issues and the Use of RT54SX Devices BACKGROUND The attached paper authored by Richard B. Katz of NASA GSFC and J. J. Wang of Actel describes anomalies
More informationVideo and Image Processing Suite
Video and Image Processing Suite August 2007, Version 7.1 Errata Sheet This document addresses known errata and documentation issues for the MegaCore functions in the Video and Image Processing Suite,
More informationUniversity of Arizona January 18, 2000 Joel Steinberg Rev. 1.6
I/O Specification for Serial Receiver Daughter Board (PCB-0140-RCV) (Revised January 18, 2000) 1.0 Introduction The Serial Receiver Daughter Board accepts an 8b/10b encoded serial data stream, operating
More informationIlmenau, 9 Dec 2016 Testing and programming PCBA s. 1 JTAG Technologies
Ilmenau, 9 Dec 206 Testing and programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge
More informationof Boundary Scan techniques.
SMT TEHNOLOGY Boundary Scan Techniques for Test Coverage Improvement When discussing the JTAG protocol, most engineers immediately think of In System Programming procedures. Indeed, there are numerous
More informationV6118 EM MICROELECTRONIC - MARIN SA. 2, 4 and 8 Mutiplex LCD Driver
EM MICROELECTRONIC - MARIN SA 2, 4 and 8 Mutiplex LCD Driver Description The is a universal low multiplex LCD driver. The version 2 drives two ways multiplex (two blackplanes) LCD, the version 4, four
More informationUsing the XSV Board Xchecker Interface
Using the XSV Board Xchecker Interface May 1, 2001 (Version 1.0) Application Note by D. Vanden Bout Summary This application note shows how to configure the XC9510 CPLD on the XSV Board to enable the programming
More informationWhite Paper Lower Costs in Broadcasting Applications With Integration Using FPGAs
Introduction White Paper Lower Costs in Broadcasting Applications With Integration Using FPGAs In broadcasting production and delivery systems, digital video data is transported using one of two serial
More informationLaboratory Exercise 4
Laboratory Exercise 4 Polling and Interrupts The purpose of this exercise is to learn how to send and receive data to/from I/O devices. There are two methods used to indicate whether or not data can be
More informationIntroduction to JTAG / boundary scan-based testing for 3D integrated systems. (C) GOEPEL Electronics -
Introduction to JTAG / boundary scan-based testing for 3D integrated systems (C) 2011 - GOEPEL Electronics - www.goepelusa.com Who is GOEPEL? World Headquarters: GÖPEL electronic GmbH Göschwitzer Straße
More informationDocument Part Number: Copyright 2010, Corelis Inc.
CORELIS Low Voltage Adapter Low Voltage Adapter Boundary-Scan Interface User s Manual Document Part Number: 70398 Copyright 2010, Corelis Inc. Corelis, Inc. 12607 Hiddencreek Way Cerritos, CA 90703-2146
More informationJTAGcable II In Circuit Emulator for Atmel AVR microcontrollers. User s Guide REV 1.0. Many ideas one solution
JTAGcable II In Circuit Emulator for Atmel AVR microcontrollers REV 1.0 User s Guide Evalu ation Board s for 51, AVR, ST, PIC microcontrollers Sta- rter Kits Embedded Web Serve rs Prototyping Boards Minimodules
More informationXJTAG DFT Assistant for
XJTAG DFT Assistant for Installation and User Guide Version 1.0 enquiries@xjtag.com Table of Contents SECTION PAGE 1. Introduction...3 2. Installation...3 3. Quick Start Guide...3 4. User Guide...4 4.1.
More informationA/D and D/A convertor 0(4) 24 ma DC, 16 bits
A/D and D/A convertor 0(4) 24 ma DC, 6 bits ZAT-DV The board contains independent isolated input A/D convertors for measurement of DC current signals 0(4) ma from technological convertors and sensors and
More informationBABAR IFR TDC Board (ITB): system design
BABAR IFR TDC Board (ITB): system design Version 1.1 12 december 1997 G. Crosetti, S. Minutoli, E. Robutti I.N.F.N. Genova 1. Introduction TDC readout of the IFR will be used during BABAR data taking to
More informationXJTAG DFT Assistant for
XJTAG DFT Assistant for Installation and User Guide Version 2 enquiries@xjtag.com Table of Contents SECTION PAGE 1. Introduction...3 2. Installation...3 3. Quick Start Guide...3 4. User Guide...4 4.1.
More information18 Nov 2015 Testing and Programming PCBA s. 1 JTAG Technologies
8 Nov 25 Testing and Programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge costs
More informationECE 372 Microcontroller Design
E.g. Port A, Port B Used to interface with many devices Switches LEDs LCD Keypads Relays Stepper Motors Interface with digital IO requires us to connect the devices correctly and write code to interface
More informationBTW03 DESIGN CONSIDERATIONS IN USING AS A BACKPLANE TEST BUS International Test Conference. Pete Collins
2003 International Test Conference DESIGN CONSIDERATIONS IN USING 1149.1 AS A BACKPLANE TEST BUS Pete Collins petec@jtag.co.uk JTAG TECHNOLOGIES BTW03 PURPOSE The purpose of this presentation is to discuss
More information2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family
December 2011 CIII51002-2.3 2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family CIII51002-2.3 This chapter contains feature definitions for logic elements (LEs) and logic array blocks
More informationuresearch GRAVITECH.US GRAVITECH GROUP Copyright 2007 MicroResearch GRAVITECH GROUP
GRAVITECH.US uresearch GRAVITECH GROUP Description The I2C-7SEG board is a 5-pin CMOS device that provides 4-digit of 7-segment display using I 2 C bus. There are no external components required. Only
More informationChapter 7 Memory and Programmable Logic
EEA091 - Digital Logic 數位邏輯 Chapter 7 Memory and Programmable Logic 吳俊興國立高雄大學資訊工程學系 2006 Chapter 7 Memory and Programmable Logic 7-1 Introduction 7-2 Random-Access Memory 7-3 Memory Decoding 7-4 Error
More informationXDS560R JTAG Emulator Technical Reference
XDS560R JTAG Emulator Technical Reference 2006 DSP Development Systems XDS560R JTAG Emulator Installation Guide 507355-0001 Rev. B August 2006 SPECTRUM DIGITAL, INC. 120502 Exchange Drive, #440 Stafford,
More information16 Dec Testing and Programming PCBA s. 1 JTAG Technologies
6 Dec 24 Testing and Programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge costs
More informationTMS320C6000: Board Design for JTAG
Application Report SPRA584C - April 2002 320C6000: Board Design for JTAG David Bell Scott Chen Digital Signal Processing Solutions ABSTRACT Designing a 320C6000 DSP board to utilize all of the functionality
More informationEEM Digital Systems II
ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EEM 334 - Digital Systems II LAB 3 FPGA HARDWARE IMPLEMENTATION Purpose In the first experiment, four bit adder design was prepared
More informationPART. Maxim Integrated Products 1
9-646; Rev 0; /00 General Description The MAX94 evaluation kit (EV kit) is assembled with a MAX94 and the basic components necessary to evaluate the -bit analog-to-digital converter (ADC). Connectors for
More informationUNIT IV CMOS TESTING. EC2354_Unit IV 1
UNIT IV CMOS TESTING EC2354_Unit IV 1 Outline Testing Logic Verification Silicon Debug Manufacturing Test Fault Models Observability and Controllability Design for Test Scan BIST Boundary Scan EC2354_Unit
More informationXJTAG. Boundary Scan Tool. diagnosys.com
XJTAG Boundary Scan Tool diagnosys.com XJLink Overview The XJLink is a small, portable, USB 2.0 to JTAG adapter that provides a high speed interface (480Mbps) to the JTAG chain. The small, lightweight
More informationOpenOCD - Beyond Simple Software Debugging
OpenOCD - Beyond Simple Software Debugging Oleksij Rempel o.rempel@pengutronix.de https://www.pengutronix.de Why I use OpenOCD? Reverse engineering and for fun This is the main motivation behind this talk
More informationLAX_x Logic Analyzer
Legacy documentation LAX_x Logic Analyzer Summary This core reference describes how to place and use a Logic Analyzer instrument in an FPGA design. Core Reference CR0103 (v2.0) March 17, 2008 The LAX_x
More informationJRC ( JTAG Route Controller ) Data Sheet
JRC ( JTAG Route Controller ) Data Sheet ATLAS TGC Electronics Group September 5, 2002 (version 1.1) Author : Takashi Takemoto Feature * JTAG signal router with two inputs and seven outputs. * Routing
More informationKramer Electronics, Ltd. USER MANUAL. Models: VS-162AV, 16x16 Audio-Video Matrix Switcher VS-162AVRCA, 16x16 Audio-Video Matrix Switcher
Kramer Electronics, Ltd. USER MANUAL Models: VS-162AV, 16x16 Audio-Video Matrix Switcher VS-162AVRCA, 16x16 Audio-Video Matrix Switcher Contents Contents 1 Introduction 1 2 Getting Started 1 3 Overview
More informationCMOS Testing-2. Design for testability (DFT) Design and Test Flow: Old View Test was merely an afterthought. Specification. Design errors.
Design and test CMOS Testing- Design for testability (DFT) Scan design Built-in self-test IDDQ testing ECE 261 Krish Chakrabarty 1 Design and Test Flow: Old View Test was merely an afterthought Specification
More informationApplication Note PG001: Using 36-Channel Logic Analyzer and 36-Channel Digital Pattern Generator for testing a 32-Bit ALU
Application Note PG001: Using 36-Channel Logic Analyzer and 36-Channel Digital Pattern Generator for testing a 32-Bit ALU Version: 1.0 Date: December 14, 2004 Designed and Developed By: System Level Solutions,
More informationontap BOUNDARY SCAN SOFTWARE PRODUCT FEATURES AND SCREEN TOUR FLYNN SYSTEMS CORP.
ontap BOUNDARY SCAN SOFTWARE PRODUCT FEATURES AND SCREEN TOUR FLYNN SYSTEMS CORP. PROVIDING BOUNDARY SCAN SOLUTIONS SINCE 2000 1 ontap Product Documentation Table of Contents Introduction... 4 Overview...
More informationUltraLogic 128-Macrocell ISR CPLD
256 PRELIMINARY Features 128 macrocells in eight logic blocks In-System Reprogrammable (ISR ) JTAG-compliant on-board programming Design changes don t cause pinout changes Design changes don t cause timing
More informationDLP Pico Chipset Interface Manual
Data Sheet TI DN 2510477 Rev A May 2009 DLP Pico Chipset Interface Manual Data Sheet TI DN 2510477 Rev A May 2009 IMPORTANT NOTICE BEFORE USING TECHNICAL INFORMATION, THE USER SHOULD CAREFULLY READ THE
More informationXJTAG DFT Assistant for
XJTAG DFT Assistant for Installation and User Guide Version 2 enquiries@xjtag.com Table of Contents SECTION PAGE 1. Introduction...3 2. Installation...3 3. Quick Start Guide...3 4. User Guide...4 4.1.
More information82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE
Y Y Y Y Y 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most Other Microprocessors High Speed Zero Wait State Operation with 8 MHz 8086 88 and 80186 188 24 Programmable I
More informationVirtex-II Pro and VxWorks for Embedded Solutions. Systems Engineering Group
Virtex-II Pro and VxWorks for Embedded Solutions Systems Engineering Group Embedded System Development Embedded Solutions Key components of Embedded systems development Integrated development environment
More informationRaspberry Pi debugging with JTAG
Arseny Kurnikov Aalto University December 13, 2013 Outline JTAG JTAG on RPi Linux kernel debugging JTAG Joint Test Action Group is a standard for a generic transport interface for integrated circuits.
More informationChapter 18. DRAM Circuitry Discussion. Block Diagram Description. DRAM Circuitry 113
DRAM Circuitry 113 Chapter 18 DRAM Circuitry 18-1. Discussion In this chapter we describe and build the actual DRAM circuits in our SK68K computer. Since we have already discussed the general principles
More informationLogic Devices for Interfacing, The 8085 MPU Lecture 4
Logic Devices for Interfacing, The 8085 MPU Lecture 4 1 Logic Devices for Interfacing Tri-State devices Buffer Bidirectional Buffer Decoder Encoder D Flip Flop :Latch and Clocked 2 Tri-state Logic Outputs
More informationSerial Digital Interface II Reference Design for Stratix V Devices
Serial Digital Interface II Reference Design for Stratix V Devices AN-673 Application Note This document describes the Altera Serial Digital Interface (SDI) II reference design that demonstrates how you
More informationCH7021A SDTV / HDTV Encoder
Chrontel SDTV / HDTV Encoder Brief Datasheet Features VGA to SDTV/EDTV/HDTV conversion supporting graphics resolutions up to 1600x1200 HDTV support for 480p, 576p, 720p, 1080i and 1080p Support for NTSC,
More informationXJTAG DFT Assistant for
XJTAG DFT Assistant for Installation and User Guide Version 2 enquiries@xjtag.com Table of Contents SECTION PAGE 1. Introduction...3 2. Installation...3 3. Quick Start Guide...4 4. User Guide...4 4.1.
More informationDP8212 DP8212M 8-Bit Input Output Port
DP8212 DP8212M 8-Bit Input Output Port General Description The DP8212 DP8212M is an 8-bit input output port contained in a standard 24-pin dual-in-line package The device which is fabricated using Schottky
More informationVtronix Incorporated. Simon Fraser University Burnaby, BC V5A 1S6 April 19, 1999
Vtronix Incorporated Simon Fraser University Burnaby, BC V5A 1S6 vtronix-inc@sfu.ca April 19, 1999 Dr. Andrew Rawicz School of Engineering Science Simon Fraser University Burnaby, BC V5A 1S6 Re: ENSC 370
More informationField Programmable Gate Arrays (FPGAs)
Field Programmable Gate Arrays (FPGAs) Introduction Simulations and prototyping have been a very important part of the electronics industry since a very long time now. Before heading in for the actual
More informationLMH0344 3Gbps HD/SD SDI Adaptive Cable Equalizer
3Gbps HD/SD SDI Adaptive Cable Equalizer General Description The 3Gbps HD/SD SDI Adaptive Cable Equalizer is designed to equalize data transmitted over cable (or any media with similar dispersive loss
More informationSERDES Eye/Backplane Demo for the LatticeECP3 Versa Evaluation Board User s Guide
SERDES Eye/Backplane Demo for the LatticeECP3 Versa Evaluation Board User s Guide May 2011 UG44_01.1 Introduction This document provides technical information and instructions on using the LatticeECP3
More informationImage generator. Hardware Specification
Image generator [SVO-03] Rev. NetVision Co., Ltd. Update History Revision Date Note 2018/07/02 New File(Equivalent to Japanese version 1.2) S.Usuba i index 1. Outline... 1 1.1. features and specification
More informationWhite Paper Versatile Digital QAM Modulator
White Paper Versatile Digital QAM Modulator Introduction With the advancement of digital entertainment and broadband technology, there are various ways to send digital information to end users such as
More informationSDI Audio IP Cores User Guide
SDI Audio IP Cores User Guide Subscribe Last updated for Quartus Prime Design Suite: 16.0 UG-SDI-AUD 101 Innovation Drive San Jose, CA 95134 www.altera.com TOC-2 Contents SDI Audio IP Cores Overview...1-1
More informationUSER'S MANUAL. Getting started with ALEXAN ATMEL AT89C2051/AT89C4051 Training Module - 1
USER'S MANUAL Getting started with ALEXAN ATMEL AT89C05/AT89C405 Training Module - Version.0 Copyright 006 Ace Electronic Technology Inc. All Rights Reserved Alexan 05/405 TM- v..0 Page of 7 About This
More informationCombo Board.
Combo Board www.matrixtsl.com EB083 Contents About This Document 2 General Information 3 Board Layout 4 Testing This Product 5 Circuit Diagram 6 Liquid Crystal Display 7 Sensors 9 Circuit Diagram 10 About
More informationPicoBlaze. for Spartan-3, Virtex-II, Virtex-IIPRO and Virtex-4 devices. JTAG Loader. Quick User Guide. Kris Chaplin and Ken Chapman
PicoBlaze for Spartan-3, Virtex-II, Virtex-IIPRO and Virtex-4 devices JTAG Loader Quick User Guide Kris Chaplin and Limited Warranty and Disclaimer. These designs are provided to you as is. Xilinx and
More informationMSP430-H2618 development board Users Manual
MSP430-H2618 development board Users Manual All boards produced by Olimex are RoHS compliant Rev. Initial, April 2009 Copyright(c) 2009, OLIMEX Ltd, All rights reserved Page 1 INTRODUCTION: MSP430-H2618
More informationMicrocontrollers and Interfacing week 7 exercises
SERIL TO PRLLEL CONVERSION Serial to parallel conversion Microcontrollers and Interfacing week exercises Using many LEs (e.g., several seven-segment displays or bar graphs) is difficult, because only a
More informationWhy FPGAs? FPGA Overview. Why FPGAs?
Transistor-level Logic Circuits Positive Level-sensitive EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 28, 2003 John Wawrzynek Transistor Level clk clk clk Positive
More information