JTAG Boundary- ScanTesting

Transcription

1 JTAG Boundary- ScanTesting In Altera evices November 995, ver. 3 Application Note 39 Introduction As printed circuit boards (PCBs) become more complex, the need for thorough testing becomes increasingly important. Advances in surfacemount packaging and PCB manufacturing have resulted in smaller boards, making traditional test methods e.g., external test probes and bed-of-nails test fixtures harder to implement. As a result, cost savings from PCB space reductions are sometimes offset by cost increases in traditional testing methods. In the 98s, the Joint Test Action Group (JTAG) developed the IEEE specification for boundary-scan testing. The boundary-scan test (BST) architecture offers the capability to efficiently test components on PCBs with tight lead spacing. You can use the BST architecture to test pin connections without using physical test probes and to capture functional data while a device is operating normally. Boundary-scan cells in a device can force signals onto pins, or capture data from pin or core logic signals. Forced test data is serially shifted into the boundary-scan cells. Captured data is serially shifted out and externally compared to expected results. Figure illustrates the concept of boundary-scan testing. Figure. JTAG Boundary-Scan Testing Serial ata In Boundary-Scan Cell IC Pin Signal Serial ata Out Core Logic Core Logic Interconnection to Be Tested JTAG evice JTAG evice 2 Table summarizes Altera devices that comply with the IEEE specification by providing BST capability for input, output, and dedicated configuration pins. Altera Corporation A-AN-39-3

2 Table. Altera evices with BST Capability evice Family FLEX K FLEX 8 MAX 9 MAX 7S () FLASHlogic evices Supporting BST All devices EPF8282, EPF8282A, EPF8282V, EPF8282AV, EPF8636A, EPF882, EPF882A, EPF85, EPF85A All devices EPM728S, EPM76S, EPM792S, EPM7256S All devices Note: () The EPM732S, EPM764S, and EPM796S contain a JTAG controller for ISP. However, these devices do not support BST. This application note describes how to use the BST circuitry provided in Altera devices, and discusses the following topics: Altera device JTAG BST architecture JTAG boundary-scan register JTAG BST operation control Enabling JTAG BST circuitry Guidelines for JTAG boundary-scan testing Boundary-Scan escription Language (BSL) support References In addition to BST, you can use the JTAG circuitry for in-system programming (ISP) in MAX 9, MAX 7S, and FLASHlogic devices and for in-circuit reconfigurability (ICR) in FLEX K, FLEX 8, and FLASHlogic devices. This application note only discusses the BST feature of the JTAG circuitry. f For more information on using JTAG circuitry for ISP and ICR, go to the following documents: Application Note 59 (Configuring FLEX K evices) Application Note 33 (Configuring FLEX 8 evices) Application Note 38 (Configuring Multiple FLEX 8 evices) Application Note 45 (Configuring FLASHlogic evices) Application Brief 4 (In-System Programmability in MAX 9 evices) Application Brief 45 (esigning for In-System Programmability in MAX 7S evices) 2 Altera Corporation

3 Altera evice JTAG BST Architecture A device operating in JTAG BST mode uses four required pins, TI, TO, TMS, and TCK, and one optional pin, ntrst. Table 2 summarizes the functions of each of the JTAG BST pins. Table 2. JTAG Pin escriptions Pin escription Function TI Test data input Serial input pin for instructions as well as test and programming data. ata is shifted in on the rising edge of TCK. TO Test data output Serial data output pin for instructions as well as test and programming data. ata is shifted out on the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. TMS Test mode select Input pin that provides the control signal to determine the transitions of the TAP Controller state machine. Transitions within the state machine occur at the rising edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS is evaluated on the rising edge of TCK. TCK Test Clock input The Clock input to the BST circuitry. Some operations occur at the rising edge, while others occur at the falling edge. ntrst Test reset input (optional) Active-low input to asynchronously reset the boundary-scan circuit. This pin is only available in FLEX devices (ntrst is optional according to IEEE Std. 49.). For FLEX K, MAX 9, FLASHlogic, EPF85, and EPF85A devices, the JTAG pins are dedicated for BST testing only. For MAX 7S, EPF882, EPF882A, EPF8636A, EPF8282, EPF8282A, EPF8282V, and EPF8282AV devices, you can use the four JTAG pins as I/O pins by turning off the JTAG option with Altera s MAX+PLUS II software (see Enabling JTAG BST Circuitry on page 25 of this application note). FLEX 8 and FLEX K JTAG devices have the optional pin, ntrst, that can asynchronously reset the JTAG BST circuitry. JTAG boundary-scan testing is controlled by a Test Access Port (TAP) Controller, which is described in JTAG BST Operation Control on page 3 of this application note. JTAG BST requires instruction, bypass, and boundary-scan registers, which are described below: Altera Corporation 3

4 The instruction register is used to determine the test to be performed, the data register to be accessed, or both. The bypass register is a -bit-long data register used to provide a minimum-length serial path between TI and TO. The boundary-scan register is a long shift register composed of all the boundary-scan cells at the pins of the device. Table 3 shows the length of the instruction register and boundary-scan register for Altera JTAG devices. Table 3. Length of JTAG evice Instruction Register Length (Bits) Boundary-Scan Register Length (Bits) EPFK 48 EPFK2 624 EPFK3 768 EPFK4 864 EPFK5 96 EPFK7,4 EPFK,248 EPF8282, EPF8282V, EPF8282A, EPF8282AV EPF8636A 3 47 EPF882, EPF882A EPF85, EPF85A EPM EPM EPM948 6 EPM EPM732S, Note () EPM764S, Note () EPM796S, Note () EPM728S 3 EPM76S 32 EPM792S 372 EPM7256S 492 EPX EPX EPX EPX , Note (2) 4 Altera Corporation

5 Notes to table: () This device supports ISP through the JTAG interface but does not support BST. (2) The boundary-scan register in the EPX86 is comprised of two, 26-bit-long register chains. Figure 2 shows the JTAG register control functions. The TMS, ntrst, and TCK pins operate the TAP Controller, and the TI and TO pins provide the serial path for the data registers. The TI pin also provides data to the instruction register, which then generates control logic for the data registers. Figure 2. JTAG Register Control Instruction Register TI UPATEIR CLOCKIR SHIFTIR TO TMS TCLK ntrst Note () TAP Controller UPATER CLOCKR SHIFTR Instruction ecode ata Bypass Register Boundary-Scan Register ICOE Register, Note (2) UESCOE Register, Note (3) ISP/ICR, Note (4) Notes: () The ntrst pin is available only in FLEX devices. (2) The ICOE register is available in FLEX K, EPM94, EPM948, MAX 7S, and FLASHlogic devices. (3) The UESCOE register is available in FLEX K, MAX 7S, and FLASHlogic devices. (4) The ISP/ICR registers are available in FLEX K, MAX 9, MAX 7S, and FLASHlogic devices. Altera Corporation 5

6 JTAG Boundary-Scan Register The boundary-scan register is a large serial-shift register that uses the TI pin as an input and the TO pin as an output. The boundary-scan register consists of 3-bit peripheral elements that are either I/O pins (all devices), dedicated inputs (all devices), or dedicated configuration pins (FLEX devices only). You can use the boundary-scan register to test external pin connections or to capture internal data. Figure 3 shows how test data is serially shifted around the periphery of the JTAG device. Figure 3. Boundary-Scan Register Internal Logic Each peripheral element is either an I/O pin, dedicated input pin, or dedicated configuration pin. TAP Controller TI TMS TCLK ntrst () TO Note: () The ntrst pin is available only in FLEX devices. I/O Pin Boundary-Scan Cells Figure 4 shows the boundary-scan cells (BSCs) associated with each I/O pin in FLEX K, FLEX 8, and MAX 9 devices. The 3-bit BSC consists of a set of capture registers and a set of update registers for each I/O pin. The capture registers connect to internal device data via the OUTJ, OEJ, and I/O pin signals, while the update registers connect to external data through the tri-state data input, tri-state control, and INJ signals. The control signals for the JTAG BST registers (e.g., SHIFT, CLOCK, and UPATE) are generated internally by the TAP Controller; the MOE signal is generated by a decode of the instruction registers. The data signal path for the boundary-scan register runs from the Serial ata In (SI) signal to the Serial ata Out (SO) signal. The scan register begins at the TI pin and ends at the TO pin of the device. 6 Altera Corporation

7 Figure 4. FLEX K, FLEX 8 & MAX 9 I/O Pins with JTAG BST Circuitry I/O Controls SO to Row or Column Interconnect 4 () OEJ 6 (2) INJ from Row or Column Interconnect 2 ENA CLRN OUTJ 2 VCC VCC Capture Update Slew- Rate Control I/O Pin 2 SI SHIFT UPATE MOE CLOCK I/O Element I/O Cell Circuitry JTAG Circuitry Figure 5 shows the BSCs that are associated with each I/O pin in MAX 7S and FLASHlogic devices. The BSCs in Figure 5 are similar to BSCs in other device families, except the input portion does not contain an update register. Altera Corporation 7

8 Figure 5. MAX 7S & FLASHlogic I/O Pins with JTAG BST Circuitry OE Control Signals SO OEJ to PIA INJ from Macrocell OUTJ I/O Pin Capture Update Slew- Rate Control SI SHIFT UPATE MOE CLOCK I/O Control Block JTAG Circuitry edicated Input Boundary-Scan Cells The boundary-scan register also includes dedicated input pins. Because these pins have special functions, some bits of the boundary-scan register are internally connected to VCC or GN, or used only for device configuration; these bits are thus forced to a static high () or low () state, or are used internally for configuration. Figure 6 shows the BSCs for the dedicated input pins in FLEX devices. The register normally associated with an output signal, OUTJ, is tied to GN, and the tri-state control, OEJ, is connected to VCC. The signal data from the dedicated input is the only register that contains test data. The data shifts out of SO in the order,, and, where is the data associated with the dedicated input. Because only the bit has valid data, a scan test pattern must either ignore or expect the and that follow the bit. 8 Altera Corporation

9 Figure 6. FLEX edicated Input Pins with JTAG BST Circuitry to Internal Logic SO edicated Input VCC Update Register GN Capture SI SHIFT CLOCK UPATE MOE Figure 7 shows the BSCs for the dedicated input pin in MAX 9 and MAX 7S devices. All of the update registers in the BSCs are disabled and the registers normally associated with the output signals OUTJ and OEJ are connected to GN and VCC, respectively. When shifting data in and out of the BSCs, OUTJ and OEJ must be ignored. Altera Corporation 9

10 Figure 7. MAX 9 & MAX 7S edicated Input Pins with JTAG BST Circuitry edicated Input to Internal Logic SO VCC GN SI SHIFT CLOCK Capture Figure 8 shows the BSCs for the dedicated input pins in FLASHlogic devices. FLASHlogic BSCs contain a single capture register that allows the data at the input pin to be captured and shifted out. Figure 8. FLASHlogic edicated Input Pins with JTAG BST Circuitry edicated Input to Internal Logic SO Capture SI SHIFT CLOCK Altera Corporation

11 edicated Configuration Boundary-Scan Cells (FLEX evices Only) The FLEX boundary-scan register includes dedicated configuration pins. Because these pins have special functions, some bits of the boundary-scan register are internally connected to VCC or GN, or used only for device configuration; these bits are thus forced to a static high () or low () state, or are used internally for configuration. Figure 9 shows the peripheral elements associated with the FLEX dedicated configuration pins (i.e., nconfig, MSEL, MSEL, nsp, CONF_ONE, nstatus, and CLK). These pins are used only during device configuration, but the capture register associated with the I/O pin can be used for external pin connectivity tests. The I/O pin can receive data but cannot force data onto external connections. The data values associated with the other two capture registers should be ignored. Figure 9. FLEX edicated Configuration Pins with JTAG BST Circuitry (Part of 2) to Internal Controls VCC SO nconfig MSEL MSEL nsp () nce (2) CLK (2) MSEL (2) GN SI Capture SHIFT CLOCK Notes: () The nsp pin is available in FLEX 8 devices only. (2) The nce, CLK, and MSEL pins are available in FLEX K devices only. Altera Corporation

12 Figure 9. FLEX edicated Configuration Pins with JTAG BST Circuitry (Part 2 of 2) to Internal Controls SO from Internal Controls CONF_ONE nstatus GN GN SI SHIFT CLOCK Capture to Internal Controls SO from Internal Controls from Internal Controls CLK () nceo (2) SI SHIFT CLOCK Capture Notes: () The CLK pin is available in FLEX 8 devices only. (2) The nceo pin is available in FLEX K devices only. 2 Altera Corporation

13 JTAG BST Operation Control Altera JTAG devices implement the following BST instructions: SAMPLE/PRELOA, EXTEST, BYPASS, UESCOE, HIZ, and ICOE. Table 4 summarizes the BST instructions, which are described in detail later in this application note. Table 4. Boundary-Scan Instructions Mode Instruction Code escription SAMPLE/ PRELOA FLEX K FLEX 8 MAX 9 MAX 7S FLASHlogic Allows a snapshot of the signals at the device pins to be captured and examined during normal device operation, and permits an initial data pattern to be output at the device pins. EXTEST Allows the external circuitry and board-level interconnections to be tested by forcing a test pattern at the output pins and capturing test results at the input pins. BYPASS Note () UESCOE Note (3) Places the -bit bypass register between the TI and TO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. Note (3) Selects the UESCOE register and places it between TI and TO, allowing the UESCOE to be serially shifted out of TO. HIZ Sets all I/O pins to a highimpedance state. ICOE Note (2) Selects the ICOE register and places it between TI and TO, allowing the ICOE to be serially shifted out of TO. Altera Corporation 3

14 Notes to table: () EPM732S, EPM764S, and EPM796S devices do not support JTAG BST. However, these devices have a BYPASS mode that allows them to pass JTAG information to other devices in the scan chain that support JTAG BST. (2) For MAX 9 devices, ICOE is available in the EPM94 and EPM948 devices only. (3) FLEX K and MAX 7S devices have a private instruction to select the UESCOE registers to be connected to TI and TO. The FLEX K UESCOE register is 7 bits long. The MAX 7S UESCOE register is 6 bits long. The TAP Controller, a 6-state state machine clocked on the rising edge of TCK, uses the TMS pin to control JTAG operation in the device. Figure shows the flow of the TAP Controller. 4 Altera Corporation

15 Figure. JTAG TAP Controller State Machine TMS = TEST_LOGIC/ RESET TMS = SELECT_R_SCAN TMS = SELECT_IR_SCAN TMS = RUN_TEST/ ILE TMS = TMS = TMS = TMS = TMS = CAPTURE_R TMS = CAPTURE_IR TMS = TMS = SHIFT_R TMS = SHIFT_IR TMS = TMS = TMS = EXIT_R TMS = TMS = EXIT_IR TMS = TMS = PAUSE_R TMS = PAUSE_IR TMS = TMS = TMS = TMS = EXIT2_R TMS = EXIT2_IR TMS = TMS = TMS = UPATE_R TMS = UPATE_IR TMS = TMS = Altera Corporation 5

16 At device power-up, the TAP Controller is in the TEST_LOGIC/RESET state, in which the BST circuit is disabled and the device is in normal operation. The TAP Controller remains in this state as long as TMS is held high when TCK is clocked (all devices except FLEX) or when ntrst is driven low (FLEX devices only). uring JTAG operation, the TEST_LOGIC/RESET state is entered if TMS is held high for at least five Clock cycles on TCK (all devices except FLEX) or if ntrst is driven low (FLEX devices only). Figure shows the timing requirements for the JTAG signals. Figure. JTAG Waveforms TMS TI t JCP t JCH t JCL tjpsu t JPH TCK t JPX t JPCO t JPXZ TO Signal to Be Captured Signal to be riven t JSZW t JSSU t JSH t JSCO t JSXZ Table 5 shows the timing values for each Altera JTAG device. 6 Altera Corporation

17 Table 5. JTAG Timing Parameters Symbol Parameter FLEX K FLEX 8 MAX 9 MAX 7S FLASHlogic Unit EPX74 & EPX78 EPX88 & EPX86 Min Max Min Max Min Max Min Max Min Max Min Max t JCP TCK clock period 5 25 ns t JCH TCK clock high time ns t JCL TCK clock low time ns t JPSU JTAG port setup ns time t JPH JTAG port hold time ns t JPCO JTAG port clock to ns output t JPZX JTAG port highimpedance to valid output ns t JPXZ t JSSU t JSH t JSCO t JSZX t JSXZ JTAG port valid output to highimpedance Capture register setup time Capture register hold time Update register clock to output Update register high-impedance to valid output Update register valid output to highimpedance ns ns ns ns ns ns To start JTAG operation, select an instruction mode by advancing the TAP Controller to the shift instruction register (SHIFT_IR) state and shift in the appropriate instruction code on the TI pin. The waveform diagram in Figure 2 represents the entry of the instruction code into the instruction register. It shows the values of TCK, TMS, TI, and TO and the states of the TAP Controller. From the RESET state, TMS is clocked with the pattern to advance the TAP Controller to SHIFT_IR. Altera Corporation 7

18 Figure 2. Selecting the Instruction Mode TCK TMS TI TO TAP_STATE SHIFT_IR RUN_TEST/ILE SELECT_IR_SCAN TEST_LOGIC/RESET SELECT_R_SCAN CAPTURE_IR EXIT_IR The TO pin is tri-stated in all states except in the SHIFT_IR and SHIFT_R states. The TO pin is activated at the first falling edge of TCK after entering either of the shift states and is tri-stated at the first falling edge of TCK after leaving either of the shift states. To ensure proper JTAG operation, the initial state of the instruction register is set to the codes summarized in Table 6. Table 6. Initial Intstruction Register Codes evice Family Code FLEX K FLEX 8 MAX 9, Note () MAX 7S FLASHlogic Note: () For the EPM932 and EPM956, the initial state of the instruction register is. When the SHIFT_IR state is activated, TO is no longer tri-stated, and the initial state of the instruction register is shifted out on the falling edge of TCK. TO continues to shift out the contents of the instruction register as long as the SHIFT_IR state is active. The TAP Controller remains in the SHIFT_IR state as long as TMS remains low. 8 Altera Corporation

19 uring the SHIFT_IR state, an instruction code is entered by shifting data on the TI pin on the rising edge of TCK. The last bit of the opcode must be clocked at the same time that the next state, EXIT_IR, is activated; EXIT_IR is entered by clocking a high logic level on TMS. Once in the EXIT_IR state, TO becomes tri-stated again. TO is always tri-stated except in the SHIFT_IR and SHIFT_R states. After an instruction code is entered correctly, the TAP Controller advances to perform the serial shifting of test data in one of three modes SAMPLE/PRELOA, EXTEST, or BYPASS that are described below. SAMPLE/PRELOA Instruction Mode The SAMPLE/PRELOA instruction mode allows you to take a snapshot of device data without interrupting normal device operation. Figure 3 shows the capture, shift, and update phases of the SAMPLE/PRELOA mode. Figure 3. JTAG BST SAMPLE/PRELOA Mode (Part of 2) Capture Phase SO In the capture phase, the signals at the pin, OEJ and OUTJ, are loaded into the capture registers. The register CLOCK signal is supplied by the TAP Controller s CLOCKR output. The data retained in these registers consists of signals from normal device operation. OEJ INJ OUTJ Capture Update SI SHIFT CLOCK UPATE MOE Altera Corporation 9

20 Figure 3. JTAG BST SAMPLE/PRELOA Mode (Part 2 of 2) Shift & Update Phases SO In the shift phase, the previously captured signals at the pin, OEJ and OUTJ, are shifted out of the boundaryscan register via the TO pin using CLOCK. As data is shifted out, the patterns for the next test can be shifted in via the TI pin. OEJ INJ In the update phase, data is transferred from the capture registers to the UPATE registers using the UPATE Clock. The data stored in the UPATE registers can be used for the EXTEST instruction. OUTJ Capture Update SI SHIFT CLOCK UPATE MOE uring the capture phase, the multiplexers that precede the capture registers select the active device data signals; this data is then clocked into the capture registers. The multiplexers at the outputs of the update registers also select active device data to prevent functional interruptions to the device. uring the shift phase, the boundary-scan shift register is formed by clocking data through capture registers around the device periphery and then out of the TO pin. New test data can simultaneously be shifted into TI and replace the contents of the capture registers. uring the update phase, data in the capture registers is transferred to the update registers. This data can then be used in the EXTEST instruction mode described below. Figure 4 shows the SAMPLE/PRELOA waveforms. The SAMPLE/PRELOA instruction code is shifted in through the TI pin. The TAP Controller advances to the CAPTURE_R state and then to the SHIFT_R state, where it remains if TMS is held low. The data shifted out of the TO pin consists of the data that was present in the capture registers after the capture phase. New test data shifted into the TI pin appears at the TO pin after being clocked through the entire boundary-scan register. Figure 4 shows that the instruction code at TI does not appear at the 2 Altera Corporation

21 TO pin until after the capture register data is shifted out. If TMS is held high on two consecutive TCK Clock cycles, the TAP Controller advances to the UPATE_R state for the update phase. Figure 4. SAMPLE/PRELOA Shift ata Register Waveforms TCK TMS TI TO SHIFT_IR TAP_STATE EXIT_IR SELECT_R_SCAN Instruction Code UPATE_IR CAPTURE_R ata stored in boundary-scan register is shifted out of TO. SHIFT_R After boundary-scan EXIT_R register data has been UPATE_R shifted out, data entered into TI will shift out of TO. EXTEST Instruction Mode The EXTEST instruction mode is used primarily to check external pin connections between devices. Unlike the SAMPLE/PRELOA mode, EXTEST allows test data to be forced onto the pin signals. By forcing known high and low logic levels on output pins, opens and shorts can be detected at pins of any device in the scan chain. Figure 5 shows the capture, shift, and update phases of the EXTEST mode. Altera Corporation 2

22 Figure 5. JTAG BST EXTEST Mode Capture Phase SO In the capture phase, the signals at the pin, OEJ and OUTJ, are loaded into the capture registers. The register CLOCK signal is supplied by the TAP Controller s CLOCKR output. Previously retained data in the update registers drives the IOC input, INJ, and allows the I/O pin to tri-state or drive a signal out. OEJ INJ A in the OEJ update register tri-states the output buffer. OUTJ Capture Update SI SHIFT CLOCK UPATE MOE Shift & Update Phases SO In the shift phase, the previously captured signals at the pin, OEJ and OUTJ, are shifted out of the boundaryscan register via the TO pin using CLOCK. As data is shifted out, the patterns for the next test can be shifted in via the TI pin. OEJ INJ In the update phase, data is transferred from the capture registers to the update registers using the UPATE Clock. The update registers then drive the IOC input, INJ, and allow the I/O pin to tristate or drive a signal out. OUTJ Capture Update SI SHIFT CLOCK UPATE MOE 22 Altera Corporation

23 EXTEST selects data differently than SAMPLE/PRELOA. EXTEST chooses data from the update registers as the source of the INJ, output, and Output Enable signals. Once the EXTEST instruction code is entered, the multiplexers select the update register data; thus, data stored in these registers from a previous EXTEST or SAMPLE/PRELOA test cycle can be forced onto the pin signals. In the capture phase, the results of this test data are stored in the capture registers and then shifted out of TO during the shift phase. New test data can then be stored in the update registers during the update phase. The waveform diagram in Figure 6 resembles the SAMPLE/PRELOA waveform diagram, except that the instruction code for EXTEST uses all zeros. The data shifted out of TO consists of the data that was present in the capture registers after the capture phase. New test data shifted into the TI pin appears at the TO pin after being clocked through the entire boundary-scan register. Figure 6. EXTEST Shift ata Register Waveforms TCK TMS TI TO SHIFT_IR TAP_STATE EXIT_IR SELECT_R Instruction Code UPATE_IR CAPTURE_R ata stored in boundary-scan register is shifted out of TO. SHIFT_R After boundary-scan register data has been shifted out, data entered into TI will shift out of TO. EXIT_R UPATE_R BYPASS Instruction Mode The BYPASS instruction mode is activated with an instruction code made up of only ones. The waveforms in Figure 7 show how scan data passes through a device once the TAP Controller is in the SHIFT_R state. In this state, data signals are clocked into the bypass register from TI on the rising edge of TCK and out of TO on the falling edge of the same Clock pulse. Altera Corporation 23

24 Figure 7. BYPASS Shift ata Register Waveforms TCK TMS TI TO Bit Bit 2 Bit 3 Bit Bit 2 Bit 4 SHIFT_IR TAP_STATE EXIT_IR SELECT_R_SCAN Instruction Code UPATE_IR CAPTURE_R SHIFT_R ata shifted into TI on the rising edge of TCK is shifted out of TO on the falling edge of the same TCK pulse. EXIT_R UPATE_R UESCOE Instruction Mode The UESCOE instruction mode is used to examine the user electronic signature (UES) within the devices along a JTAG chain. When this instruction is selected, the UES register is connected between the TI and TO ports and the user-defined UES is shifted out through the UES register. In FLEX K devices, the UES register is 7 bits long; in MAX 7S devices, it is 6 bits long; and in FLASHlogic devices, it is 6 bits long. Altera devices do not implement the optional JTAG USERCOE register, which shifts out a user-defined identification from the JTAG device. Altera devices support a UES register, which has equivalent functionality. In MAX 7S devices, this UES register is read using margin instructions in ISP mode. HIZ Instruction Mode The HIZ instruction mode (FLASHlogic devices only) forces all I/O pins into a high-impedance state. After the HIZ instruction is loaded, the I/O pins remain in a high-impedance state until another instruction is loaded into the instruction register. For example, loading TEST_LOGIC/RESET resets the instruction register to ICOE. ICOE Instruction Mode The ICOE instruction mode is used to perform a blind interrogation of the devices in a JTAG chain. When ICOE is selected, the device identification register is loaded with the 32-bit vendor-defined 24 Altera Corporation

25 identification code and connected between the TI and TO ports. The 32- bit vendor-defined identification register for Altera devices is listed in Table 7. Table 7. ICOE for Altera evices evice ICOE, Note () Version (4 bits) Part Number (6 bits) Manufacturer s Identity ( bits) ( Bit) EPFK EPFK2 EPFK3 EPFK5 EPFK7 EPFK EPM94 EPM948 EPM732S EPM764S EPM796S EPM728S EPM76S EPM792S EPM7256S EPX74 (44-pin) EPX74 (68-pin) EPX78 (84-pin) EPX78 (32-pin) EPX88 (84-pin) EPX88 (32-pin) EPX86 (dev ), Note (2) EPX86 (dev ) Notes: () The most significant bit is on the left. (2) The EPX86 contains two separate JTAG state machines. Each EPX86 TAP Controller contains a separate ICOE. Enabling JTAG BST Circuitry This section describes the procedures for enabling and disabling JTAG BST circuitry for Altera s JTAG-capable devices. Altera Corporation 25

26 FLEX K, EPF85, EPF85A, MAX 9 & FLASHlogic evices The JTAG BST circuitry for Altera devices is enabled upon device powerup. You can use JTAG BST both before and after device programming or configuration. Because these devices have dedicated JTAG pins, their JTAG circuitry is always enabled. To disable the JTAG circuitry in these devices, tie the JTAG pins to the values shown in Table 8. Table 8. isabling JTAG Circuitry evice Compiler Option JTAG Pins, Note () TMS TCK TI TO ntrst FLEX K VCC VCC VCC Leave open GN FLEX 8 JTAG isabled User I/O User I/O User I/O User I/O GN (except EPF85 JTAG Enabled VCC VCC VCC Leave open GN and EPF85A) EPF85 and VCC VCC VCC Leave open GN EPF85A MAX 9 VCC VCC VCC Leave open MAX 7S JTAG isabled User I/O User I/O User I/O User I/O JTAG Enabled VCC VCC VCC Leave open FLASHlogic VCC VCC VCC Leave open Note: () If the design has been compiled with JTAG circuitry enabled, tying the JTAG pins to the appropriate state will deactivate the JTAG circuitry. FLEX 8 (Except EPF85) & MAX 7S evices The JTAG circuitry for Altera devices is enabled upon device power-up. You can use JTAG BST both before and after device programming or configuration. In FLEX 8 devices, if the dedicated configuration pin nconfig is held low, configuration is delayed and you can perform JTAG BST. Because these devices have four pins that can be used as either JTAG pins or user I/O pins, you must enable or disable the JTAG circuitry before compilation. For a design that has been compiled with JTAG pins enabled, the four pins operate as dedicated JTAG pins only. If these devices are not using the JTAG circuitry, tying the JTAG pins to the appropriate state (shown in Table 8) disables the JTAG circuitry. 26 Altera Corporation

27 You can enable or disable JTAG support for these devices on a device-bydevice basis with the Enable JTAG Support option in the FLEX 8 Individual evice Options dialog box or the MAX 7S Individual evice Options dialog box. You can also enable JTAG support on all devices in a project in the FLEX 8 Global Project Options dialog box or the MAX 7S Global Project Options dialog box. Guidelines for JTAG Boundary-Scan Testing Use the following guidelines when performing boundary-scan testing with JTAG devices: If the... pattern does not shift out of the instruction register via the TO pin during the first Clock cycles of the SHIFT_IR state, then the proper TAP Controller state has not been reached. To solve this problem, try the following: Verify that the TAP Controller has reached the SHIFT_IR state correctly. To advance the TAP Controller to the SHIFT_IR state, return to the RESET state and clock the code on the TMS pin. Check the connections to the VCC, GN, JTAG, and dedicated configuration pins on the device. For FLEX and MAX 7S devices, if the device is in user mode, make sure that you have turned on the Enable JTAG Support option in MAX+PLUS II. Perform a SAMPLE/PRELOA test cycle prior to the first EXTEST test cycle to ensure that known data is present at the device pins when the EXTEST mode is entered. If the OEJ update register contains a, then the data in the OUTJ update register will be driven out. The state must be known and correct to avoid contention with other devices in the system. o not execute a BYPASS shift cycle before an EXTEST test cycle that requires preloaded test data. The bypass and boundary-scan registers shift simultaneously when the TAP Controller is in the SHIFT_R state. Therefore, using the BYPASS mode will shift test data out of the capture registers. If problems persist, contact Altera Applications at (8) 8-EPL. Boundary-Scan escription Language (BSL) Support The Boundary-Scan escription Language (BSL) a subset of VHL provides a syntax that allows you to describe the features of a JTAG BSTcapable device that can be tested. Test software development systems can then use the BSL files for test generation, analysis, failure diagnostics, and ISP. Altera Corporation 27

28 For a list of the BSL files for JTAG-compliant Altera devices, go to the readme.txt file in the /jtagbsdl/pc directory on the MAX+PLUS II C-ROM. BSL files are also contained in the self-extracting file, jtagbsdl.exe (for PCs) and the compressed file jtagbsdl.tar (for workstations), which are available on the Altera electronic bulletin board service (BBS) at (48) and on the Altera FTP site at ftp.altera.com. You can also access the Altera FTP site through Altera s world-wide web site at Conclusion References The JTAG BST circuitry available in Altera devices provides a costeffective and efficient way to test systems that contain devices with tight lead spacing. Circuit boards with Altera and other JTAG-compliant devices can use the EXTEST, SAMPLE/PRELOA, and BYPASS modes to create serial patterns that internally test the pin connections between devices and check device operation. Bleeker, H., P. van den Eijnden, and F. de Jong. Boundary-Scan Test: A Practical Approach. Eindhoven, The Netherlands: Kluwer Academic Publishers, 993. Institute of Electrical and Electronic Engineers, Inc. IEEE Standard Test Access Port and Boundary-Scan Architecture (IEEE Std ). New York: Institute of Electrical and Electronic Engineers, Inc., 99. Maunder, C. M., and R. E. Tulloss. The Test Access Port and Boundary- Scan Architecture. Los Alamitos: IEEE Computer Society Press, Orchard Parkway San Jose, CA (48) Applications Hotline: (8) 8-EPL Customer Marketing: (48) Literature Services: (48) Altera, MAX, MAX+PLUS, and FLEX are registered trademarks of Altera Corporation. The following are trademarks of Altera Corporation: MAX+PLUS II, AHL, and FLEX K. Altera acknowledges the trademarks of other organizations for their respective products or services mentioned in this document, specifically: Verilog and Verilog-XL are registered trademarks of Cadence esign Systems, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Synopsys is a registered trademark of Synopsys, Inc. Viewlogic is a registered trademark of Viewlogic Systems, Inc. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. Copyright 996 Altera Corporation. All rights reserved. 28 Altera Corporation Printed on Recycled Paper.