Prototype of a Gigabit Data Transmitter in 65-nm CMOS for DEPFET Pixel Detectors at Belle-II

Transcription

1 Prototype of a Gigabit Data Transmitter in 65-nm CMOS for DEPFET Pixel Detectors at Belle-II Tetsuichi Kishishita H. Krüger, T. Hemperek, M. Lemarenko, M. Koch, M. Gronewald, N. Wermes University of Bonn 12th Pisa meeting, May, 2012

2 Outline Pixel Detector (PXD) at Belle-II Data Handling Processor (DHP) Gbit Data Transmitter Measurement Results Summary -1/20-

3 Belle-II Experiment at Super-KEKB Mt. Tsukuba Silicon Vertex Detector Pixel Detector (PXD) 1.8 & 2.2 cm radii TOP Counter KEKB Belle-II e - e + ~1km in diameter E-CAL Linac About 60km northeast of Tokyo Muon Detector RICH Counter Central Drift Chamber KEKB/Belle upgrade ( ) Super-high luminosity ~ cm -2 s -1 (x40 higher) study CP violation via B 0 /B 0 -bar decays rare decay modes more statistics Radiation environment: ~1 Mrad per year Refurbishment of accelerator and detector required -2/20-

4 Pixel Detector with DEPFET sensor p-fet (MOSFET) on a fully depleted bulk (sideward depletion) signal electrons accumulated in the internal gate modulate the transistor current (gq~600pa/e-) low CD, low noise charge collection during external gate being switched off low power integrating device, discharge internal gate with positive pulse applied to the clear contact See posters by Peter Kodys & Christian Koffmane -3/20-

5 Front-end ASICs for PXD Active pixel area thinned to 50 µm Independent read-out from both sides ASICs bump bonded onto the DEPFET substrate All-silicon DEPFET module ILC mech. dummy SWITCHER high voltage (10-20V) pulses for clear and gate lines DCD (Drain Current Digitizer) receive drain current signals from DEPFET sample and subtract pedestal currents digitize signals 4:1 multiplex ADC outputs DHP (Data Handling Processor) data reduction sending data off the module to the backend -4/20-

6 Data Handling Processor (DHP) Functionality Module controller JTAG bus to DCD and SWITCHER chips Clock & timing generation & distribution Data reduction (1/20) 0-suppression triggered r/o to Switcher timing 10 MHz row frequency 100 ns ADC conversion time DAC ADC 256 inputs per DCD 8 bit ADC + 2 bit DAC per input DCD DCD4:1 output mux 81.9 Gbps 320 Mbps output data x 256 lines DCD Data processing Raw data buffer Fixed pattern noise correction Hit finder (FIFO1 + FIFO2) Framing (AURORA) Serializer + Gbit link driver JTAG PLL DAC ADC JTAG clock, sync Deserializer Pedestal substraction Common mode corr. FIFO 1 Hit finder FIFO 2 Framer Gbit Serializer driver one data out per DHP raw data memory pedestal memory trigger DAC memory DHP DHP 5 Gbps (1.25 Gbps link per DHP) tation & buffer size (FIFO 1 & 2) Synchronized clock generation (PLL) + Gbit link driver -5/20-

7 DHP Data Link Specifications 1.6 Gbps per DHP chip, four links per module (incl. 20 % overhead) Electrical link (optical data transmission not feasible due to radiation tolerance requirements) 40 cm flex-cable up to patch panel (PP) 12-15m 2-15m twisted pair (TWP) cable to to DHH (Data Handling Hybrid) Link bandwidth & signal integrity (>12m cable) are crucial. to other modules regulator power supplies PXD module module pp ~40 cm flex cable detector volume patch panel data, ctrl TWP cable m DHH FPGA opto TX/RX DHH clock, trigger, reset from other modules opto links for data 40 compute node ATCA shelf from machine Gbit eth Gbit link (x4) -6/20-

8 Test Chips raw data buffer (x16) pedestal buffer (x2) HSTL receiver DHP 0.1, IBM 90nm, submitted March 2010 C4 bumps 4x2mm 2 half size chip (32 inputs) Full data processing (1.6 GHz PLL, Gbit link driver) main PLL SER PLL CML driver dual port SRAM ADC & DACs DHP 0.2, IBM 90nm, submitted July 2011 full size chip (64 inputs) improved data processing & hit finder 4x3.2 mm 2 CML driver with programmable pre-emphasis Bias DACs & temperature sensor DHPT 0.1,TSMC 65nm, submitted Oct separate chiplets: Analog designs are challenging. 1.9x1.9 mm /20-

9 DHPT0.1 with TSMC 65-nm CMOS PLL (Phase-Locked Loop) 80 MHz reference clock 1.6 GHz, 800MHz & 320 MHz outputs Pseudo random bit sequence generator 8 bit LFSR CML link driver with programmable pre-emphasis Two differential pairs with adj. bias currents Programmable delay 80 MHz PLL 320 MHz 800 MHz 1.6 GHz LFSR pre drv. 320 MHz CML driver TXO_P TXO_N CML driver 0.95 x 0.95 mm 2-9 metal layers -Vcore=1.2 V -VIO=1.8 V -MIM option TX1_P TX1_N I 0 I 1 del SVD-PXD, Vienna 2012, H. Krüger 2 dt a b -8/20-

10 Charge-pump PLL Voltage Controlled Oscillator (VCO) provides oscillating waveform with variable frequency PLL synchronizes VCO frequency to input reference freq. through feedback Use digital counter structure to divide VCO frequency UP(t) ref(t) f REF =80MHz div(t) f FB =80MHz+δ PFD e(t) DN(t) Charge Pump N=20 I CP Divider Loop Filter v(t) Vctrl VCO out(t) 1.6 GHz N N=2 N=5 800 MHz 320 MHz -9/20-

11 more schematic details... f REF = 80MHz R Q PFD delay D Q Ref2Fast UP R CP I CP CP OUT Cpole: 3.86 pf ICP: 10 ua η: 0.98 LF R ripple VCO Q DN R C pole R notch C ripple R D Q I CP C notch V CT RL f FB =80MHz+δ f REF Ref(t) (t) f FB Div(t) (t) UP(t) Up(t) DN(t) Down(t) delay Fb2Fast VCO Phase-Frequency Detector (PFD): classical two flipflops structure, additional error detection circuit Charge-pump (CP): differential structure with dummy branch Loop-filter (LPF): MIM structures, well-tuned parameters for PLL stability f REF -10/20-

12 more schematic details... f REF = 80MHz R Q PFD delay D Q Ref2Fast UP R CP I CP CP OUT Cpole: 3.86 pf ICP: 10 ua η: 0.98 LF R ripple VCO Q DN R C pole R notch C ripple R D Q I CP C notch V CT RL f FB =80MHz+δ delay Fb2Fast Layout 140um VCO f REF f REF Ref(t) (t) f FB Div(t) (t) UP(t) Up(t) DN(t) Down(t) PFD DIV CP LPF 55um VCO 105 µm MIM cap. -10/20-

13 Voltage-Controlled Oscillator (VCO) three inverters connected as a ring oscillator differential pairs with PMOS loads with cross-coupled stages for rail-to-rail switching V CT RL In+ 1.2 V In- Out Out In- Out+ Power:1.25 mw for 1.6 GHz Out- Out+ Output frequency (GHz) Periodic Steady State Response slow (ss), 40 C typical, 27 C fast (ff), 0 C 800 MHz [800 MHz vs. Vctrl] In+ In Vctrl (V) V CT RL wide tuning range of the output frequency oscillation freq. of 1.6 GHz is secured under 3σ process variations. -11/20-

14 PLL Settling Behavior The Vctrl settles to the final value in tsettle~750 ns within accuracy of 2%. Stable behavior for all process corners. Layout parasitics are included in the simulation. 1.0 Transient Response 0.75 Vctrl (V) slow (ss), 40 C typical, 27 C fast (ff), 0 C time (μs) -12/20-

15 CML Driver with pre-emphasis Differential current mode logic (CML): driver (phase control) + differential pair post driver Two differential pairs: adj. bias currents: 105 µm Layout - tap weights (a & b), Predriver circuit - delay (dt) upto 600ps with 4 fixed steps Dummy poly layout for impedance matching Decoupl. C 75 µm PLL outputs CML driver TX1_P TX1_N poly-res. with dummy structures 1.6 GHz/ 800 MHz pre drv. del I 0 I 1 a dt -b a dt [waveform] b 2 dt a b -13/20-

16 Why pre-emphasis is necessary? Signal integrity is affected by Driver PLL jitter phase noise signal rise time Cable (12-15m long high frequency attenuation) resistive loss (skin effect) large cable diameter dielectric loss low εr Cross-talk shielding driver preemphasis cable receiver Signal spectrum Signal spectrum after preemphasis Cable transfer function (low pass filter) Received spectrum Compensate signal losses by shaping the transmitted pulse response (boosting high frequency component) necessary for Gbit driver -14/20-

17 Measurement setup 800 MHz output connected to the oscilloscope 1.6 GHz LFSR output connected with flex & twisted cables Signal Integrity Analysis DHPT 0.1 Flex cable, 38cm TWP cable, 10 (20) m -15/20-

18 Measurement setup 800 MHz output connected to the oscilloscope 1.6 GHz LFSR output connected with flex & twisted cables 800 MHz output clock 1.25 ns precise clock generation -15/20-

19 Pre-emphasis Measurements Check 800 MHz output with CML pre-emphasis on (directly connected to the oscilloscope) pre-emphasis works as expected Delay settings variations variable delay settings Tap weight (bias) settings variations variable tap weight settings -16/20-

20 Signal Integrity Analysis Measure vertical & horizontal eye opening Pseudo random bit sequence as a signal source 1.6 Gbps, 8bit LFSR sequence 10m Infiniband cable (LEONI, AWG 26) 600 mv bad eye opening Pre-emphasis: off -17/20-

21 Signal Integrity Analysis Measure vertical & horizontal eye opening Pseudo random bit sequence as a signal source 1.6 Gbps, 8bit LFSR sequence 10m Infiniband cable (LEONI, AWG 26) 600 mv 400 mv Pre-emphasis: off Pre-emphasis: on (dt=600 ps & max. tap weight) -17/20-

22 Signal Integrity Analysis 1.6 Gbps, 8bit LFSR sequence 38 cm flex (I.V.) + 10m Infiniband cable (LEONI, AWG 26) Max. pre-emphasis settings jitter: 25ps (1σ) 200 mv -18/20-

23 Signal Integrity Analysis 1.6 Gbps, 8bit LFSR sequence 38 cm flex (I.V.) + 20m Infiniband cable (LEONI, AWG 26) Max. pre-emphasis settings jitter: 42ps (1σ) 100 mv Intrinsic rad. hardness (tox~1-2 nm) is attractive for future high-energy experiments. -19/20-

24 Summary DHPT 0.1, test chip, TSMC 65nm, shipped Jan. 2012, full custom blocks good signal integrity for 1.6 Gbps with flex + 10m (20m) Infiniband cables Irradiation tests (TID for PLL & Gbit driver) under way Another 65nm test chip was submitted in Mar LVDS RX/TX for JTAG Full size chip (DHPT 1.0, TSMC 65nm) to be designed & submitted by fall 2012 Thank you for your attention. -20/20-

25 Backup slides

26 DEPFET Pixel Vertex Detector PXD 18 mm 22 mm 22 mm 18 mm 8 GeV e - (HER) 3.7 GeV e + (LER) occupancy: ~0.2 hits/µm 2 /sec (es8mated for 1x10 35 cm - 2 sec - 1.8cm radius) spa8al resolu8on : < 10 µm (r- phi) (can be less in z) pixel size: 50 µm (r- phi) x ~90 µm (z- axis) material budget < 0.15 % X 0 per layer read- out Kme: 10 µs radia8on level: ~1 Mrad per year acceptance (η = [ ]) layer 1: 10 modules at 1.8 cm radius layer 2: 12 modules at 2.2 cm radius op8onal layer 0 at 1.3 cm radius with beam pipe upgrade half- module ac8ve area: 4.9 cm x 1.2 cm (layer1) #pixels: 240 x 512 r/o channels: 960 x 128 (4- fold parallel) sample (row) rate: 12 MHz