Are Your PLDs Metastable?

Transcription

1 Thi application note provide a detailed decription of the metatable behavior in PL from both circuit and tatitical viewpoint. Additionally, the information on the metatable characteritic of Cypre PL preented here can help you achieve any deired degree of reliability. Metatable i a Greek word meaning in between. Metatability i an undeirable output condition of digital logic torage element caued by marginal triggering. Thi marginal triggering i uually caued by violating the torage element minimum et-up and hold time. In mot logic familie, metatability i een a a voltage level in the area between a logic HIGH and a logic LW. Although ytem have been deigned that did not account for metatability, it effect have taken their toll on many of thoe ytem. In mot digital ytem, marginal triggering of torage element doe not occur. Thee ytem are deigned a ynchronou ytem that meet or exceed their component wort-cae pecification. Totally ynchronou deign i not poible for ytem that impoe no fixed relationhip between input ignal and the local ytem clock. Thi include ytem with aynchronou bu arbitration, telecommunication equipment, and mot I/ interface. For thee ytem to function properly, it i neceary to ynchronize the incoming aynchronou ignal with the local ytem clock before uing them. Figure how a imple ynchronizer, whoe aynchronou input come from outide the local ytem. The ynchronizer operate with a ytem clock that i ynchronou to the local ytem operation. n each riing edge of thi ytem clock, the ynchronizer attempt to capture the tate of the aynchronou input. Figure 2 how the expected reult. Mot of the time, thi ynchronizer perform a deired. ASYNCHRNUS INPUT SYSTEM CLCK CLCK ASYNC INPUT SYNCH UTPUT SYNCHRNIZER SYNCHRNUS UTPUT Figure. Simple Synchronizer Figure 2. Expected Synchronizer utput LCALLY SYNCHRNUS SYSTEM igital ytem are uppoed to function properly all the time, however. But becaue there i no direct relationhip between the aynchronou input and the ytem clock, at ome point the two ignal will both be in tranition at very nearly the ame intant. Figure 3 how ome of the ynchronizer poible metatable output when thi input condition occur. Thee type of output would not occur if the ynchronizer made a deciion one way or the other in it pecified clock-to-output time. A flip-flop, when not properly triggered, might not make a deciion in thi time. When improperly triggered into a metatable tate, the output might later tranition to a HIGH or a LW or might ocillate. CLCK ASYNC INPUT SYNC UT METASTABLE RESLVE T 0 METASTABLE RESLVE T Figure 3. Poible Metatable State of Synchronizer When other component in the local ytem ample the ynchronizer metatable output, they might alo become metatable. A potentially wore problem can occur if two or more component ample the metatable ignal and yield different reult. Thi ituation can eaily corrupt data or caue a ytem failure. Such ytem failure are not a new problem. In 952, Lubkin (Reference ) tated that ytem deigner, including the deigner of the ENIAC, knew about metatability. The accepted olution at that time wa to concatenate an additional flip-flop after the original ynchronizer tage (Figure 4). Thi added flip-flop doe not totally remove the problem but doe improve reliability. Thi ame olution i till in wide ue today. ASYNC_IN CLCK INTERMEIATE SIGNAL SYNCHRNIZER Figure 4. Two-Stage Synchronizer METASTABLE SCILLATING UTPUT SYNC_UT LCALLY SYNCHRNUS SYSTEM Cypre Semiconductor Corporation 390 North Firt Street San Joe CA March 6, 997

2 Recovery from metatability i probabilitic. In the improved ynchronizer, the firt flip-flop output might till be in a metatable tate at the end of the ample clock period. Becaue the flip-flop are equential, the probability of propagating a metatable condition from the econd flip-flop tage i the quare of the probability of the firt flip-flop remaining metatable for it ample clock period. Thi type of ynchronizer doe have the drawback of adding one clock cycle of latency, which might be unacceptable in ome ytem. A ytem peed increae and a more ytem utilize input from aynchronou external ource, metatability-induced failure become an increaingly ignificant portion of the total poible ytem failure. So far, no known method totally eliminate the poibility of metatability. However, while you cannot eliminate metatability, you can employ deign technique that make it probability relatively mall compared with other failure mode. Explanation of Metatability In a flip-flop, a metatable output i undefined or ocillate between HIGH and LW for an indefinite time due to marginal triggering of the circuit. Thi anomalou flip-flop behavior reult when data input violate the pecified et-up and hold time with repect to the clock. In the cae of a -type flip-flop, the data mut be table at the device input before the clock edge by a time known a the et-up time, t. Thi data mut remain table after the clock edge by a time known a the hold time, t h (Figure 5). The data ignal mut atify both the et-up and hold time to enure that the torage device (regiter, flip-flop, latch) tore valid data and to enure that the output preent valid data after a maximum pecified clock-to-output delay t co_max. A ued in thi application note, t co_max refer to the interval from the clock riing edge to the time the data i valid on the output. In mot cae, t co_max refer to the maximum t co pecified by a data heet, a oppoed to the average or typical t co value. t > t h > t _max t h_max t < t _max CLCK INPUT UTPUT t co < t co_max t co > t co_max t h < t h_max Figure 5. Triggering Mode of a Simple Flip-Flop If the data violate either the et-up or hold pecification, the flip-flop output might go to an anomalou tate for a time greater than t co_max (Figure 5). The additional time it take the output to reach a valid level can range from a few hundred picoecond to ten of microecond. The amount of additional time beyond t co_max required for the output to reach a valid logic level i known a the metatable walk-out time. Thi walk-out time, while tatitically predictable, i not determinitic. Figure 6. utput Propagation v. ata Tranition Figure 6, from Reference 2, how the variation in output delay with data input time. The left portion of the graph how that when the data meet the required et-up time, the device ha valid output after a predictable delay, which equal t co. The middle portion of the graph indicate the metatable region. If the data tranition in thi region, valid output i delayed beyond t co_max. The cloer the input tranition to the center of the metatable region, violating the device triggering requirement, the longer the propagation delay. If the data tranition after the metatable region, the device doe not recognize the input at that clock edge, and no tranition occur at the output. A given in Reference, you can predict the region t w, where data tranition caue a propagation delay longer than t, from the formula: t w ( t t co ) τ t co e Eq. where t depend on device-pecific characteritic uch a tranitor dimenion and the flip-flop gain-bandwidth product. Figure 7 how another way of looking at metatability. A flip-flop, like any other bitable device, ha two minimum-potential energy level, eparated by a maximum-energy potential. A bitable ytem ha tability at either of the two minimum-energy point. The ytem can alo have temporary tability metatability at the energy maximum. If nothing puhe the ytem from the maximum-energy point, the ytem remain at thi point indefinitely. Figure 7. Triggering Mode of a Simple Flip-Flop 2

3 A hill with valley on either ide i another bitable ytem. A ball placed on top of the hill tend to roll toward one of the minimum-energy level. If left unditurbed at the top, the ball can remain there for an indeterminate amount of time. A thi figure indicate, the characteritic of the top of the hill a well a natural factor affect how long the ball tay there. The teepne of the hill i analogou to the gain-bandwidth product of the flip-flop input tage. Caue of Metatability Sytem with eparate entitie, each running at different clock rate, are called globally aynchronou ytem (Reference 4). The entitie might include keyboard, communication device, dik drive, and proceor. A ytem containing uch entitie i aynchronou becaue ignal between two or more entitie do not hare a fixed relationhip. Metatability can occur between two concurrently operating digital ytem that lack a common time reference. For example, in a multiproceing ytem, it i poible that a requet for data from one ytem can occur at nearly the exact moment that thi ignal i ampled by another part of the ytem. In thi cae, the requet might be undefined if it doe not obey the et-up and hold time of the requeted ytem. When globally aynchronou ytem communicate with each other, their ignal mut be ynchronized. Arbitration mut occur when two or more requet for a hared reource are received from aynchronou ytem. An arbiter decide which of two event hould be erviced firt. A ynchronizer, which i a type of arbiter with a clock a one of the arbited ignal, mut make it deciion within a fixed amount of time. A device can ynchronize an input ignal from an external, aynchronou device in cae uch a a keyboard input, an external interrupt, or a communication requet. Care mut be taken when two locally ynchronou ytem communicate in a globally aynchronou environment. A ynchronization failure occur when one ytem ample a flip-flop in the other ytem that ha an undefined or ocillating output. Thi event can ditribute non-binary ignal through a binary ytem (Reference 5). In ynchronizer, the circuit mut decide the tate of the data input at the clock input riing edge. If thee two ignal arrive at the ame time, the circuit can produce an output baed on either deciion, but mut decide one way or the other within a fixed amount of time. Attacking Metatability The deign of ynchronou ytem i much different than the deign of globally aynchronou ytem. The deign of a ynchronou digital ytem i baed on known maximum propagation delay of flip-flop and logical gate. Aynchronou ytem by definition have no fixed relationhip with each other, and therefore, any propagation delay from one locally ynchronou ytem to the next ha no phyical meaning. Two different method are available to produce locally ynchronou ytem from globally aynchronou ytem. The firt method involve creating elf-timed ytem. In a elf-timed ytem, the entity that perform a tak alo emit a ignal that indicate the tak completion. Thi handhaking ignal allow the ue of the reult when they are ready intead of waiting for the wort-cae delay. Such handhaking ignal allow communication between locally ynchronou ytem. The advantage of the elf-timed method i that it permit machine to run at the average peed intead of the wort-cae peed. The diadvantage are that a elf-timed ytem mut have extra circuitry to compute it own completion ignal and extra circuitry to check for the completion of any tak aigned to external entitie. Petri Net, data flow machine, and elf-timed module all ue the elf-timed method of communication among locally ynchronou ytem. Self-timed tructure do not completely eliminate metatability, however, becaue they can include arbiter that can be metatable. Mot ytem do not include elf-timed interface due to the additional circuitry and complexity. The econd method of producing locally ynchronou ytem from globally aynchronou ytem i the imple ynchronizer. Thi i the mot common way of communicating between aynchronou object. The metatability error that might arie from thee ytem mut be made to play an inignificant role when compared with other caue of ytem failure. Many metatability olution involve pecial circuit (Reference 6 and 7). Some of thee olution do not reduce metatability at all (Reference 3 and 8). ther, however, do reduce metatability error by puhing the occurrence of metatability to a place where ufficient time i available for reolving the error. Mot of thee circuit are ytem dependent and do not offer a univeral olution to metatability error. The eaiet and the mot widely ued olution i to give the ynchronizing circuit enough time to both ynchronize the ignal and reolve any poible metatable event before other part of the ytem ample the ynchronized output. Thi olution require knowledge of the metatable characteritic of the device performing the ynchronization. Many emiconductor companie have developed circuit uch a arbiter, flip-flop, and latche that are pecifically deigned to reduce the occurrence of metatability. Although thee part might have good metatability characteritic, they have very limited application. The circuit can only function a flip-flop or arbiter and do not have the flexibility of PL. Cypre Semiconductor ha deigned the flip-flop in the company PL to be metatability hardened. Thi allow you to ue Cypre PL in a wide range of ytem requiring ynchronization. Circuit Analyi of Metatability Many author have written paper detailing the analyi of metatability from a circuit tandpoint (Reference 5, 7, 8, 9, 0,, and 2). In Reference, for example, Kacprzak preent a detailed analyi of an RS flip-flop metatable operation. He tate that a flip-flop ha two tage of metatable operation (Figure 8). uring the initialization phae, the and output move imultaneouly from their exiting level to the metatable voltage V m, which i the voltage at which V q V q. The econd or reolving phae occur when the output once again drift toward table voltage. nce a flip-flop ha entered a metatable tate, the device can tay there for an indeterminate length of time. The probability that the flip-flop will tay 3

4 Figure 8. Two Phae of Metatability metatable for an unuually long period of time i zero, however, due to factor uch a noie, temperature imbalance within the chip, tranitor difference, and variance in input timing. uring the econd phae of metatability, for very mall deviation around the metatable voltage, V m, the flip-flop behave like two cro-coupled linear amplifier tage that gain V d V q V q. When the gain of the cro-coupled loop exceed unity, the differential voltage increae exponentially with time. The length of time the flip-flop take to reolve cannot be exactly determined. The probability that the flip-flop will reolve within a pecific length of time, however, can be predicted. Thi probability depend on the electrical parameter of the flip-flop acting a a linear amplifier around the metatability voltage. The olution (Reference ) to the differential voltage V d (t) driving the reolving phae i given by Figure 9. Energy/Force Function of a Bitable Sytem S R Vin Vin2 Figure 0. Firt-rder Flip-Flop V o V o ( t t 0 ) τ V d () t V d ( t 0 )e Eq. 2 where t depend directly on the amplifier gain and capacitance, and where V d (t 0 ) repreent the differential voltage at ome time t 0. You can ue thi equation to determine the length of time that the output voltage will take to drift from the metatable voltage V m to a pecified voltage difference V d. Hortmann (Reference 5) tate that a flip-flop, like any other ytem with two table tate, can be decribed by an energy function with two local energy minima where P(x) 0 (Figure 9). Any bitable ytem ha at leat one metatable tate, which i an untable energy level within the ytem and repreent the local maximum of the energy function. The ytem gradient can be repreented by a force, F(x), that i zero at table and metatable tate (inflection point of the energy function). Figure 0 how a implified firt-order model of an RS flip-flop ued to predict and viualize metatability. A flip-flop energy tranfer curve (Figure ) how the relationhip between the two output. The two table tate are local energy minima of the ytem. The metatable tate, M, i a local energy maximum and repreent an untable tate with loop gain near M that i greater than one. Figure. Energy Tranfer iagram of Simple RS Flip-Flop Figure 2 how the trigger line for the firt-order approximation of the flip-flop. The dahed line RS repreent the device normal trigger line, which doe not follow the tranfer curve becaue, during triggering, the feedback loop ha not been etablihed. If at varying point along the trigger line the feedback loop i re-etablihed, the node of the device follow the curve that lead to the line S 0 S. nce on thi line, the circuit exponentially drift toward tability at either S 0 or S, depending on which ide of the line the feedback loop 4

5 that p and n device with equal geometrie produce the optimal gain-bandwidth product for metatable event reolution. Statitical Analyi of Metatability To begin the analyi of metatability, aume that the flip-flop probability of reolving it metatable tate doe not depend on it previou metatable tate. In other word, the metatable device ha no memory of how long it ha been in a metatable region. The analyi of metatability alo aume that the flip-flop probability of reolving it metatable tate in a given time interval doe not depend on the metatable reolution in another dijoint time interval. The probability that a metatable event will reolve in a given interval (0,t) i only proportional to the length of the interval. Thee aumption yield an exponential ditribution that decribe the probability that the flip-flop reolve it metatability at a time t. The exponential ditribution ha the form fx ( ) µe µt Eq. 3 Figure 2. Energy Tranfer Curve howing Trigger Path wa re-etablihed. The curve are olution to the firt-order model circuit equation for the device hown in Figure 0. When the feedback loop i retored near the line, the ytem move toward the untable tate M and can take an indefinite amount of time to exit from thi metatable tate. You can ee thi from the graph by noticing that S 0 and S are equally likely olution for ytem tability from M. nce the feedback loop i re-etablihed, the ytem exponentially decay toward M and then exponentially grow toward S 0 or S. Figure 3 how the ytem poible trigger event uing the implied time cale of the tate-pace curve. The olution of thee implified firt-order equation indicate that the fatet metatable reolution time occur when the circuit gain-bandwidth product i maximized. where m i the expected value of metatability reolution per unit time (ettling rate). Uing thi equation and given that the flip-flop wa metatable at time t 0, the probability of a metatable event lating a time t or longer i Pmet ( t met t 0 ) µe µt d T e µt Eq. 4 t The next part of the analyi involve the probability that the flip-flop i metatable at time t 0. Thi part of the analyi aume that the probability that the data tranition in a given time interval depend only on the length of the interval. A Poion proce with rate f d decribe the probability of the data tranitioning at a time t: px ( ) e f d t ( f d t) x x! Eq. 5 where x i the number of tranition. If a data tranition within a bounded time interval, W, of the clock edge caue a metatable condition, the expected number of tranition of thi Poion proce with rate f d in time interval W i EX ( ) xe f d W ( f d W) x x! x 0 f d W Eq. 6 Becaue thi expected number of tranition i the ame a the probability that the flip-flop i metatable at t 0, the equation for the probability at t 0 i Pmet ( t 0 ) f d W Eq. 7 Figure 3. Time Scale Showing Trigger Path Flannagan (Reference 2), in an attempt to maximize the gain-bandwidth product, olve implified flip-flop equation to determine the phae trajectory near the metatable point. Hi reult, which are upported by other author, indicate Uing Equation 5 and 7, the probability that a given clock cycle reult in metatability that lat at mot a time t i Pmet ( t ) Pmet ( t met t 0 )Pmet ( t 0 ) f d We µt Eq. 8 5

6 Subtituting t w for µ allow thi variable to be expreed a a ettling time contant of the flip-flop. Further, a ynchronization failure for a given clock cycle exit whenever a metatable event lat a pecified time (t r ) or longer. Uing thee two ubtitution, the probability that the flip-flop i metatable in a given clock cycle i t r t w Pfail ( clock ) f d We Eq. 9 Becaue the data tranition are independent, the number of failure in n clock cycle ha a binomial ditribution with an expected number of failure: Efail ( n cycle ) np( fail cycle ) Eq. 0 Auming a ample clock frequency, f c, that repreent the number of clock cycle, n, per unit time, the expected number of failure per unit time i t r t w Efail ( unit time ) f c f d We Eq. Auming that all data tranition are independent and that the clock ha a fixed period, the mean time between failure (MTBF) i MTBF Efail ( unit time ) t w e f c f d W Eq. 2 where MTBF i a meaure of how often, on the average, a metatable event lat a time t r or longer. Metatability ata The trong reemblance between Equation 2 and Equation 2 i baed on the prediction of the firt-order circuit analyi of an RS flip-flop. In fact, the metatability reolving time contant, t w, i directly related to the variable t, which i baed on the flip-flop gain-bandwidth product. The device-dependent variable W depend motly on the window of time within which the combination of the input and clock generate a metatable condition. Thi parameter alo depend on proce, temperature, and voltage level. The MTBF equation i uually plotted with t r (the reolving time allowed for metatable event) on the X axi and the natural log of the MTBF plotted on the Y axi (ee the appendix in thi note). Becaue the metatability equation i plotted on a emi-log cale, the graph of t r v ln(mtbf) i a line decribed by the equation t r To determine how often, on the average, a given ynchronizer in a ytem will go metatable (MTBF), you mut know the two device-pecific parameter W and t w, which hould be available from the manufacturer. Table, dicued later in thi note, lit thee value for Cypre PL. Additional value you need are the average frequency of both the ytem data and the ynchronizer clock and the amount of time after the ynchronizer maximum clock-to- time that i allowed to reolve metatable event. For example, conider the method for determining the MTBF for a Cypre PALC22V0 regitered PL ued a a ynchronizer in a ytem with the following characteritic: W t w f c f d 0.25 p 90 p ytem clock frequency 25 MHz average aynchronou data frequency 0 MHz In addition to thee value, the PL maximum operating frequency, f max, i taken directly from the data heet. The frequency i pecified a the internal feedback maximum operating frequency. It i calculated a f max MHz t cf + t where t cf i the clock-to-feedback time. If the data heet doe not pecify t cf, you can ue t co a t cf upper bound. Uing f max, you calculate the amount of time that a metatable event i allowed to reolve, t r, with t r n f c f max 25MHz 4.6MHz Now you enter thee value into the MTBF equation, making ure to keep all unit in econd: MTBF t r t w e f c f d W e year Almot forever ln( MTBF) t r ln( f t c f d W) w Eq. 3 If the operating frequency of the ytem, f c, i imply changed to 33.3 MHz, Graphically, the parameter t w i /lope of the line on thi graph. The equation for t w from the graph i t r t r2 t w ln( MTBF ) ln( MTBF 2 ) Eq e MTBF

7 the ytem fail, on the average, about every 9,700 year till beyond the ytem normal lifetime. And if f c i changed to f max (4.6 MHz), MTBF e the ytem fail, on the average, every 9.62 m. A 6-n difference in reolve time, t r, reult in almot 36 order of magnitude difference in MTBF. bviouly, accurate data i needed to deign a ytem with a high degree of reliability without being overly cautiou. Characterization of Metatability Many author (Reference 6, 8, 9, 0,, and 2) have performed numerou experiment on circuit to predict the likelihood of device metatability. Thee reearcher have ued everal teting theorie and apparatu that can be claified into three baic type (Reference 4). Intermediate voltage enor contitute the firt type. Two voltage comparator determine whether the output voltage,, lie between two given voltage. The fixture produce an error output if ha a level that i neither HIGH nor LW, hence metatable. Figure 4 how an intermediate voltage enor. Figure 4. Intermediate Voltage Senor The econd type of apparatu ue an output proximity enor to determine if the and output have approximately the ame voltage, which would indicate that the device i metatable. Figure 5 how an output proximity enor. HIGH THRESHL LW THRESHL V METASTAB Figure 5. utput Proximity METASTAB The lat type of apparatu ue a late-tranition enor to tet for metatability. Note that if one or more gate eparate the enor from the metatable ignal, the metatability might not be detected. The tet circuitry mut infer the occurrence of metatability by ome other mean. Figure 6 how an example of a late-tranition enor. The ample input i detected at time t, then at a later time t 2. If thee two ignal diagree, the device under tet wa metatable at t. ASYNC INPUT CLCK ELAY METASTAB Figure 6. Late-Tranition Senor Information from Manufacturer Many emiconductor companie provide metatability data on their part. However, mot companie do not preent the data in a format the engineer can ue. They either preent inconcluive and incomplete data or they aume the engineer can ue the data without further explanation. Few companie compare their device with imilar device. PL manufacturer provide little data largely becaue of a fear that telling the deign community that device can fail in ynchronizing application will caue deigner to ue a competitor part. The truth i that no company can provide a device that i guaranteed never to become metatable when ued a a ynchronizer. At a given operating frequency, with a given aynchronou input, and given enough time, the device become metatable. Cypre provide you with data you can ue to build a ytem to any given level of reliability when uing Cypre PL. Cypre ha performed numerou tet and collected extenive data on Cypre PL, a well a PL from other companie. Thi data give you a perpective of the part that are bet uited for a pecific application. Specific data on the metatability characteritic of Cypre PL i found in thi application note in the Tet Reult ection. The Tet Circuit Cypre ue a tet that fall into the category of the late-tranition detection. irectly meauring the output of the flip-flop in a PL are impoible due to the additional circuitry that lie between the flip-flop and the outide world. The metatability detection circuitry mut, intead, infer the flip-flop tate. Figure 7 how the metatability tet circuit implemented in each tet PL. Thi circuit allow the PL under tet to effectively tet itelf. The device under tet will both produce and record metatable condition. Figure 8 i a tate diagram howing the operation of the device. uring normal operation, the two flip-flop output (F, F 2 ) tranition between tate S and S 2, depending on the ynchronizer tate. uring normal operation, the Excluive-R on thee output produce a HIGH. Thi indicate either that metatability ha not occurred within the device or that metatability that ha occurred ha reolved before the next clock cycle. If a metatable event cannot reolve before the next clock cycle, the tate machine move to tate S 3 or S 4. In thi cae, 7

8 SYNCHRNIZER ASYNC CLCK STATE REGISTERS Figure 7. Metatability Tet Circuit F ERRR F2 the tate flip-flop have interpreted the ignal from the ynchronization regiter differently; excluive-ring thi ignal produce a LW at the device output, indicating that unreolved metatability ha occurred. Thi tet circuit doe not catch all metatable event. Specifically, it doe not record metatable event that reolve before the next clock cycle. But metatability caue an error only when it ha not reolved by the time the ignal i needed. The Cypre tet thu reveal the information deigner need to know: how often metatability create an error in the ytem. SYNCH 0, F/F2 0 S SYNCH 0, F/F2 0 SYNCH X, F/F2 ERRR SYNCH X, F/F2 00 SYNCH 0, F/F2 0 S3 SYNCH X, F/F2 S4 ERRR 0 SYNCH X, F/F2 00 ERRR 0 SYNCH, F/F 0 SYNCH X, F/F2 S2 SYNCH X, F/F2 00 SYNCH, F/F 0 ERRR SYNCH, F/F 0 Figure 8. Metatability Teting State iagram The tet circuit alo include the ability to check the maximum operating frequency of the device under tet (Figure 9). At V CC T CLCK CLK Figure 9. Maximum perating Frequency Tet T T2 FAIL each clock edge, the firt regiter output toggle. When the device reache it maximum operating frequency, the PL array cannot reolve the changing ignal fat enough to produce a valid output. At thi peed, one regiter might reolve the ignal correctly and one might not, or both might produce invalid ignal reolution. In any cae, when Excluive-Ring the tate T /T 2 of the two maximum-frequency teting regiter reult in anything other than a HIGH, the part maximum operating frequency i exceeded. The Tet Board A four-layer printed circuit board with two ignal plane, a ground plane, and a power plane i ued to perform the metatability meaurement. Uing thi four-layer board give a quiet teting environment with reliable, repeatable reult. Figure 20 how a block diagram of the tet board, with the 8

9 complete chematic hown in Figure 2. The device under tet (UT) i decoupled with 0.0-mF and 00-pF capacitor. The tet circuit i deigned to fit all indutry-tandard and Cypre-proprietary PL. The ocket allow UT pin, 2, and 4 to erve a clock pin. Pin 3 i the device aynchronou input. The ERRR condition i located on pin 27 of a 28-pin device, and the FAIL condition i on pin 20. Two additional output, F and F 2, monitor the tate of the metatability tet circuit flip-flop. RESET METASTABILITY ASYNC_IN TESTING CLCK EVENT CUNTING METASTABILILITY EVENT ISPLAY ERRR F F2 MAXIMUM FAIL FREUENCY TESTING Figure 20. Metatability Tet Board Block iagram ERRR BNC2 FAIL BNC2 CLCK BNC R3 50 ASYNC_IN BNC U9 R4 50 BANANA V CC U0 UC 74AS04 U 74AS04 UA 74AS04 UB 74AS04 UT 28PSKT C2.0 µf C3 00 pf U2 CK I I V SS V CC!E PAL6R8 C4.0 µf U4 CK I I V SS V CC!E PAL6R8 C6.0 µf F GAB F A B CC E C P E GC P F GA B F A B CC E C P E GC P U6 LE7SEG U7 LE7SEG U3 V CC CK II I!E V SS PAL6R8 C5.0 µf U5 V CC CK II I!E V SS PAL6R8 C7.0 µf RESET BANANA GRUN F BNC UE SW R7 0K U8A U8B 74AS04 PB SW C 0 µf 74AS04 74AS04 F2 BNC UF 74AS04 All input and output connect with BNC connector located around the board. The clock line, which i terminated with a 50Ω reitor to match the coax input impedance, i buffered with a 74AS04 and iolated from other ignal by a ground Figure 2. Metatability Tet Board Schematic trace. The input line i alo terminated with a 50Ω reitor and buffered with a 74AS04. Four PL drive a four-digit LE diplay that count metatability occurrence. 9

10 VLTAGE SUPPLY TEK HP 8082A PULSE GEN 2465 CTS SCILL HP 8082A PULSE GEN V CC CLCK ASYNC FAIL EVICE UNER TEST AS9200 LGIC ANALYZER Figure 22. Metatability Tet Set-Up TIMER METASTABILITY EVENT ISPLAY TEST BAR After going LW in repone to a metatable event, the ER- RR ignal automatically tranition HIGH again at the next ytem clock. Thi LW-to-HIGH pule produce a clock to the input of the firt PL, which in turn increment the diplay of metatable event. When a digit reache 9, the next occurrence of metatability generate a cacade ignal to the next higher digit. In thi way, the tet board can record a maximum of 9,999 metatable event. If a metatable event i received at 9,999, all LE witch to E, indicating that an overflow condition occurred. A reet button reet all counter and initialize the UT. Tet Set-Up Figure 22 how a block diagram of the tet et-up ued for metatability teting. Two independent pule generator (Hewlett-Packard 8082A) produce the CLCK and the ASYNC_IN ignal to the tet board. A Tektronix AS9200 logic analyzer record metatable event. A 2465 CTS digital ocillocope with frequency counter accurately determine the UT maximum operating frequency and the ASYNC_IN and CLCK frequencie. Tet Procedure Cypre ha teted all it 20-, 24-, and 28-pin PL. The fatet peed grade of each device type were teted becaue thee device have the bet metatable reolution time and thu make the bet ynchronizer. Several part from each device type were teted to enure an average metatability characteritic for that product. Where poible, part from different date code were elected to eliminate variation among different wafer lot. Teting for a pecific device tart by creating the high-level decription written in VHL to be ued with the Warp2 VHL Compiler. Figure 23 lit the behavioral decription ued for generating a JEEC file. All device were programmed uing JEEC file generated by Warp2. package tet i component metatability port ( clock, aync_in, reet : in bit; fail, perror, f, f2 : out bit); end component; end tet; entity metatability i port ( clock, aync_in, reet : in bit; fail, perror, f, f2 : out bit); end metatability; ue work.bv_math.all architecture fm of metatability i ignal ync : bit; ignal tync : bit; ignal t,t2 : bit; ignal f_tmp, f2_tmp : bit; ignal error_tmp : bit; ignal fail_tmp : bit; begin proc: proce begin wait until clock ; ync < aync_in; end proce; Figure 23. Warp2 VHL Behavorial ecription for Metatability Teting 0

11 proc2: proce begin wait until clock ; f_tmp < ync; f2_tmp < inv(ync); end proce; proc3: proce begin wait until clock ; error_tmp < ((((inv(reet) and f_tmp) and inv(f2_tmp)) or ((inv(reet) and inv(f_tmp)) and f2_tmp)) or (reet and inv(error_tmp))); end proce; proc4: proce begin wait until clock ; if (tync ) then tync < 0 ; ele tync < ; end if; end proce; proc5: proce begin wait until clock ; t < tync; t2 < inv(tync); end proce; proc6: proce begin wait until clock ; fail_tmp < (t xor t2); end proce; fail < inv(fail_tmp); perror < inv(error_tmp); f < inv(f_tmp); f2 < inv(f2_tmp); end fm; Figure 23. Warp2 VHL Behavorial ecription for Metatability Teting (continued) Each part i programmed, then teted for it maximum operating frequency, f max. By attaching the FAIL output to the ocillocope and oberving the clock frequency at which the device tarted to malfunction (FAIL going LW periodically), the maximum operating frequency for that part i determined. f max indicate the maximum rate at which metatability meaurement can be taken with accurate reult. Above thi frequency, metatable event are inditinguihable from error caued by exceeding f max. To determine each device metatability characteritic, meaurement are taken of the number of metatable event that occurred in a given time interval for everal different clock and data frequencie. Equation 3 can be ued to decribe the graph of the metatability characteritic of the device: ln( MTBF) t r ln( f t c f c W) w The lope of the line, t w, can be determined only by forcing the Y intercept of the graph (ln(f c f d W)) to a contant value when uing Equation 4: t r t r2 t w ln( MTBF ) ln( MTBF 2 ) Note that t w i a contant, device-pecific parameter.

12 Becaue W i alo a contant, device-pecific parameter, it i only neceary to hold the product f c f d contant to make ln(f c f d W) contant. The independent variable t r i varied by changing f c to produce change in the dependent variable ln(mtbf). ecreaing the frequency f c from it f max value increae the metatable reolution time, t r, and decreae the probability that a metatable event will lat longer than t r. A f c i decreaed below a certain limit, the MTBF become too large to meaure accurately. A metatable event occurring every minute i choen a the upper limit for MTBF meaurement. The range of clock rate for metatability teting i then between f max and the metatable-event-per-minute clock rate. Between thee two rate, a elected frequency contant (f c f d ) enure that no point in thi range ha a clock frequency le than twice the data frequency. Thi i becaue a data ignal that tranition more than once per clock period cannot be effectively ampled. After determining thi contant, data i taken from everal tet point within the tet range by varying f c and f d. The data at each tet point i averaged among all tet device, and the equation for the line through thee point i determined uing a linear regreion analyi. The correlation between the line and the data point verifie that the metatability equation accurately decribe the tet data. From the calculated reult, the contant W and t w are extracted. Tet Reult Table and the Appendix lit the reult of the metatability analyi of Cypre PL. Table alo lit the maximum data book operating frequency, f max ; the metatability equation contant, W and t w ; the metatability reolve time, t r, required for a 0-year MTBF; and the proce for that part. You can ue thi data to determine the maximum metatability reolve time (t r ) that you mut ue in a ytem to yield a given degree of reliability. The graph and contant (W and t w ) can be ued with any peed grade of the device, but it i uggeted that the fatet peed grade of the pecific PL be ued for optimum ynchronizer performance. Thee graph indicate the time (t r ) and the device minimum clock period that mut be ued to produce a deired degree of reliability. For example, to determine the operating parameter of the Cypre PALC22V0-20 from Table when uing the device a a ynchronizer, determine the deired MTBF. With a 0-yr ( ) MTBF, for intance, a ynchronization failure will occur once every 0 year on the average. The maximum operating frequency (f max ) from the PALC22V0 data heet i 4.6 MHz. From thi information, you can determine the minimum time (t r ) beyond the device minimum operating period that mut be added for metatability reolution: t r MTBF t w e f c f d W t r t w ( ln( MTBF) + ln( f c f d W) ) t r ( ) [ ln( ) + ln( )] 4.73 n Thi analyi aume that the clock, f c, operate at f max (4.6 MHz) and that the average aynchronou data frequency i no more than half the clock frequency. The latter condition enure effective data ampling by the ynchronizer. f d, a explained in the Statitical Analyi of Metatability ection repreent the rate at which the data change tate. f d i twice the average frequency of the aynchronou data input becaue, during any given aynchronou data period, the aynchronou data change tate twice: once from LW to HIGH and again from HIGH to LW. Becaue either of thee tate change can caue a metatable event, f d mut be et to twice the average aynchronou data frequency when determining the wort-cae MTBF. ue to the real-world uncertainty in factor uch a trace delay and the kew in clock generator, 5 n i ued intead of 4.73 n for t r. The ynchronizer maximum operating frequency, f c, in thi ytem i then f c t + t cf + t r MHz 0n + 2n + 5n The effective MTBF uing thee new value for t r and f c i MTBF e year Table.Metatability Characteritic of Cypre PL. evice f max (MHz) W () t w () t r for 0-yr MTBF (n) PALC6R E E PLC20G E E PALC20RA E E PALCE22V E E PALC22V0B E E PALC22V E E CY7C E E CY7C E E CY7C E E

13 Another example focue on the CY7C ued a a ynchronizer in a ytem whoe output regiter are clocked at an f c of 35.7 MHz, and the data ha an average frequency of 0 MHz. The MTBF for thi device ued a a ynchronizer i calculated by firt determining the metatable reolution time, t r, allowed for ynchronization. The maximum operating frequency of the part i pecified in Cypre ata Book a f max t co + t i where t co in thi cae pecifie the clock-to-feedback delay, and t pecifie the et-up time of the output regiter. t r i calculated with the equation: t r n f c f max 35.7MHz 50.0MHz With thi reult, the MTBF i MTBF e year Thi equation ue the ame value for W and t w with thi 50-MHz device a with the 66-MHz device lited in Table. A tated previouly, the contant lited intable are valid for all peed grade of a pecific device. Alo note that the 0-MHz average data frequency i doubled to produce the frequency of data tranition, f d. The lat example illutrate how to ue a Cypre PALC22V0C-0 a a ynchronizer. For a 0-year MTBF, auming the maximum f c from Cypre ata Book and f d, the required t r i t r ( ) [ ln( ) + ln( )] 3.0 n Uing thi reult, the ynchronizer maximum operating frequency i reduced from 90.9 MHz to f c MHz t f r n max 90.9MHz Two-Stage Synchronization A explained earlier, you can ue a econd regiter in erie to perform two-tage ynchronization (Figure 4). Thi i accomplihed by feeding the output of the firt ynchronization regiter to the input of the econd ynchronization regiter. In PL, thi method i common becaue the firt ynchronization tage can ynchronize the aynchronou input ignal, and the econd ynchronization tage can perform a Boolean function on a combination of the input and output ignal. Boolean function can be performed at either tage; the metatability characteritic lited in Table apply to PL regiter aynchronou input that are ued directly a well a aynchronou input ued a a Boolean combination of exiting input and output. When implementing a two-tage ynchronizer in a PL, the probability that a ynchronizer i metatable after the econd tage of ynchronization i the quare of the probability that a ynchronizer i metatable after the firt tage of ynchronization. The MTBF equation i MTBF t r t 2 w e f c f d W From thi reult, the equation for t r become t w ( ln( MTBF) + 2 ln( f c f d W) ) t r Uing thi reult for a two-tage ynchronizer in a Cypre PALC22V0C, the t r for a 0-year MTBF i reduced from 3.0 n to t r ( 0.5) ( ) [ ln( ) + ln( )] 7.65 n The maximum f c increae from 4.6 MHz to f c MHz t f r n max 90.9MHz Thi example how that if the cycle of latency caued by the additional ynchronization tage i acceptable, you can dramatically increae the ynchronizer maximum operating frequency. 3

14 Reference. Lubkin, S., (Electronic Computer Corp.), Aynchronou Signal in igital Computer, Mathematical Table and ther Aid to Computation, Vol. 6, No. 40, ctober 952, pp Nootbaar, Keith, (Applied Microcircuit Corp.), eign, Teting, and Application of a Metatable-Hardened Flip-Flop, WESCN 87 (San Francico, CA, Nov. 7-9, 987), Electronic Convention Management, Lo Angele, CA Stoll, Peter A., How to Avoid Synchronization Problem, VLSI eign, November/ecember 982, pp Chapiro, aniel M., Globally-Aynchronou Locally-Synchronou Sytem, Stanford Univerity, epartment of Computer Science Report No. STAN-CS , ctober Hortmann, Jen U., Eichel, Han W., Coate, Robert L., Metatability Behavior of CMS ASCI Flip-Flop in Theory and Tet, IEEE Journal of Solid-State Circuit, Vol. 24, No., February 989, pp Wormald, E.G., A Note on Synchronizer or Interlock Maloperation, Profeional Program Seion Record 6, WESCN 87, November 7-9, 987, Electronic Convention Management, Lo Angele, CA Pechouchek, Mirolav, Anomalou Repone Time of Input Synchronizer, IEEE Tran. Computer, Vol. C-25, No. 2, February 976, pp Chaney, T. J., Comment on A Note on Synchronizer or Interlock Maloperation, IEEE Tran. Computing, Vol. C-28, No. 0, ct. 979, pp Couranz, George R., Wann, onald F., Theoretical and Experimental Behavior of Synchronizer perating in the Metatable Region, IEEE Tran. Computer, Vol. C-24, No. 6, June 975, pp Veendrick, Harry J.M., The Behavior of Flip-Flop Ued a Synchronizer and Prediction of Their Failure Rate, IEEE Journal of Solid-State Circuit, Vol. SC-5, No. 2., April 980, pp Kacprzak, Tomaz, Albicki, Alexander, Analyi of Metatable peration in RS CMS Flip-Flop, IEEE Journal of Solid-State Circuit, Vol. SC-22, No., February 987, pp Flannagan, Stephen T., Synchronization Reliability in CMS Technology, IEEE Journal of Solid-State Circuit, Vol. SC-20, No. 4, Aug 985, pp Wakerly, John F., A eigner Guide to Synchronizer and Metatability, Center for Reliable Computing Technical Report, CSL TN #88-34, February, 988 Computer Sytem Laboratory, epartment of Electrical Engineering and Computer Science, Stanford Univerity, Stanford, CA. 4.Freeman, Gregory G., Liu, ick L., Wooley, Bruce, and McCluky, Edward J., Two CMS Metatability Senor, CSL TN# , June 986, Computer Sytem Laboratory, Electrical Engineering and Computer Science epartment, Stanford Univerity, Stanford, CA. 5.Rubin, Kim, Metatability Teting in PAL, WESCN 87 (San Francico, CA, Nov. 7-9, 987), Electronic Convention Management, Lo Angele, CA

15 MTBF () MTBF () Are Your PL Metatable?.00E+09 Appendix A. Metatability Graph of Cypre evice Cypre PALC6R E+07.00E+05.00E+03.00E+0.00E 0.00E 03.00E 05.00E Tr (n) Cypre PLC20G E+08.00E+06.00E+04.00E+02.00E+00.00E 02.00E Tr (n) 5

16 MTBF () MTBF () Are Your PL Metatable?.00E+09 Appendix A. Metatability Graph of Cypre evice (continued) Cypre PALC20RA0-5.00E+07.00E+05.00E+03.00E+0.00E 0.00E 03.00E E+09 Tr (n) Cypre PALC22V E+07.00E+05.00E+03.00E+0.00E 0.00E Tr (n) 6

17 MTBF () Are Your PL Metatable? Appendix A. Metatability Graph of Cypre evice (continued) Cypre PALC22V0B-5.00E+09.00E+07.00E+05 MTBF ().00E+03.00E+0.00E 0.00E 03.00E 05.00E 07.00E Tr (n) Cypre PALC22V0-7.00E+07.00E+05.00E+03.00E+0.00E 0.00E 03.00E Tr (n) 7

18 .00E+09 Appendix A. Metatability Graph of Cypre evice (continued) Cypre CY7C E+07.00E+05 MTBF ().00E+03.00E+0.00E 0.00E 03.00E 05.00E E+09 Tr (n) Cypre CY7C E+07 MTBF ().00E+05.00E+03.00E+0.00E 0.00E Tr (n) 8

19 .00E+09 Appendix A. Metatability Graph of Cypre evice (continued) Cypre CY7C E+07.00E+05.00E+03 MTBF ().00E+0.00E 0.00E 03.00E 05.00E Tr (n) Cypre Semiconductor Corporation, 997. The information contained herein i ubject to change without notice. Cypre Semiconductor Corporation aume no reponibility for the ue of any circuitry other than circuitry embodied in a Cypre Semiconductor product. Nor doe it convey or imply any licene under patent or other right. Cypre Semiconductor doe not authorize it product for ue a critical component in life-upport ytem where a malfunction or failure may reaonably be expected to reult in ignificant injury to the uer. The incluion of Cypre Semiconductor product in life-upport ytem application implie that the manufacturer aume all rik of uch ue and in doing o indemnifie Cypre Semiconductor againt all charge.