The Traffic Image Is Dehazed Based on the Multi Scale Retinex Algorithm and Implementation in FPGA Cui Zhe1, a, Chao Li2, b *, Jiaqi Meng3, c

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1 3rd Internatonal Conference on Mechatroncs and Industral Informatcs (ICMII 2015) The Traffc Image Is Dehazed Based on the Mult Scale Retnex Algorthm and Implementaton n FPGA Cu Zhe1, a, Chao L2, b *, Jaq Meng3, c 1 Shannx Provnce Transportaton Plannng and Research Insttute, X an, Chna 2 Hghway College, Chang an Unverst X an, Chna 3 CCCC Frst Hghway Consultants CO. Ltd, X an, Chna a Keywords: Retnex; mage dehazng; FPGA Abstract: Ths paper based on Retnex algorthm for mage processng go fog, and Retnex algorthm for some optmzaton n FPGA, n slghtly affect mage qualty whle sgnfcantly reducng the FPGA resources. Then on the successful mplementaton of the algorthm n FPGA, and wth the effect on matlab found to compare wth the orgnal fog effect FPGA matlab results are bascally the same. Introducton In the scenaros of Safe Cty project, bankng, museolog hotel, offce buldng, resdence communt safe vllage, campus, harbor, hghwa street, etc., conventonal camera s dffcult to meet the need of 24 hours contnuous montorng due to hgh performance demand, so low llumnaton cameras become a prorty. In the mentoned scenaros, there s nether enough llumnaton nor possblty to nstall lghtng faclty on a large scale. In ths case, hgh performance and low llumnaton cameras are requred to ensure montorng qualty and smplfy system framework, whch leads to good relablty and low cost. Along wth applcaton growth of low llumnaton camera, the technology s n constant progress. There were types of low llumnaton cameras: electronc day and nght camera, slow shutter camera, professonal super low llumnaton camera (usually ICR, mechancal color to black type). Electronc day and nght camera uses electronc crcut to swtch colored mages nto monochrome n order to mprove ts ISO n low llumnaton. Slow shutter camera, also named frame accumulaton camera, can ncrease mage brghtness by extendng exposure tme. When ts slow shutter s on, the output mages are not real tme. As long as the camera shutter decelerates more than 4 tmes, mage ghostng can be obvously seen on the montor[1]. Slow shutter camera enhances mage sharpness by sacrfcng nstantanety not mprovng devce hardware performance. Professonal super low llumnaton camera (usually ICR, mechancal color to black type) enhances mage qualty under low llumnaton by adoptng hgh-performance CCD, professonal low llumnaton crcut desgn, ICR flter swtcher, etc., whch guarantees real tme and vvd mage output. Demand for the product functon s more practcal to mplement. For nstance, defocus occurs after transformaton from color to black and frequent day and nght swtch happens when low llumnaton camera cooperates wth nfrared lght. However, the 3 cameras are monochrome wthout color nformaton, whch nfluences practcablty[2] The authors - Publshed by Atlants Press 226

2 Along wth technology development, more and more new theores sprng to solve the problems. Color constancy means that n dfferent envronments, human eyes sensng to color s constant n some certan range. Color constancy theory smulates the unque functon of human vsual system to process mages wth hgh recognton to get better vsual effect[3]. Land and McCann proposed the color constancy algorthm representng human vsual system, named as Retnex thoery after the combnaton of retna and cortex[4]. However, due to uneven llumnancy of mages, Land rased the random walk algorthm, whch s too complcated to acheve. Then Jobson et al. put forward the classc center/around theory sngle-scale Retnex(SSR)[5], whch solve the complcatedness problem. But other problem came up due to scale of SSR, some scholars suggested mult-scale Retnex(MSR)[6] to solve the scale ssue. Meanwhle chromatc aberraton of MSR s serous, mult-scale recovered color Retnex(MSRCR) was rased. MSRCR s good at decrease chromatc aberraton, but stll complcated n achevng the real tme montorng. Implementaton of low llumnaton algorthms are currently usng hgh performance dgtal sgnal processor(dsp), but t s also dffcult to acheve real-tme. Recently development of mcroelectroncs technology and manufacture technology of ultra large scale ntegrated crcut, especally Feld Programmable Gate Array(FPGA), provded new thoughts and method for mprovng performance of mage processng system[7]. FPGA s one of the most hghly ntegrated crcuts. Users can reconfgure the nternal logc module and I/O module of FPGA to mplement functon needed. FPGA s ntalzed through puttng code nto chps and electrfyng, whle t can be coded onlne to restructure system. The FPGA s rch n logcal unts, and easy to acheve a varety of crcut desgn and perform complcated operatons, so desgners just need to modfy nner logcal functons for dfferent mage process requrements by software. Meanwhle, hghly ntegrated FPGA makes mage panel smpler, layout more compact. Ths paper proposed the low llumnaton desgn soluton based on FPGA, amng to acheve low llumnaton algorthm and real tme through usng FPGA as process chps, Hardware parallel algorthm and ppelned structure[8]. MSR algorthm and optmzaton MSR algorthm s evolved from Sngle-Scale Retnex algorthm, and the formula to acqure SSR mages s shown below[9]: R log { I } log{ F( x, I } R(x, s noted as the channel value of output mage, I(x, as the channel I value of orgnal mage, representng convoluton, and F(x, as Gaussan template, whch s calculated below: F( x, Ke ( x+ y )/ c K s noted as normalzed factor, and ths factor should meet the condton below: F dxdy 1 In formula (2), c represents scale of dfferent Gaussan templates, namely the dameter of Gaussan template. And fnal MSR output s the weghted sum of several SSR output at dfferent scales, whch s formulated as: (1) (2) (3) 227

3 N RM w, n 1 w R c ) n n RM(x, s noted as the MSR output of channel, c {c1,c2 cn} represents dfferent scales, and w {w1,w2 wn} represents weght of dfferent scales and t meets N n 1 w n (4). Theoretcally scale changes along actual condtons, most of tme 3 dfferent scales are requred, 15, 80, and 250 pxels for nstance, and weght can be the same. However, color mage looks grey due to low contrast after ordnary MSR process, one more step need to be done[10]: R R M M wc,, wc, ) I (5) Where I s: I I log 1 + C 3 1 I Here the ntal log form log(x) s replaced by log(1+x) to make sure all the results postve whch s favorable for FPGA mplementaton later. And C value comes from experence[11], whch wll not make much dfferent to the mage effect, so t s set at 125. Consderng that FPGA s resource lmted and hard to run log, two hardware optmzatons on ntal MSR algorthm are made for easy FPGA mplementaton: 1. Cut the ntal mage twce, horzontal and vertcal respectfully and get the quarter to process Gaussan Blur, whch decrease the sze of both the mage and the Gaussan template, the resource consumpton s cut by 3 quarters at least. 2. Approxmate the log nto arthmetc n formula (4) and (5), and combne them as: R M C w, c, I N n 1 n n { w [ F( x, c ) I ]} After that, the operatons are reduced and all the results are postve. And wth MSR processng, just lnear Enhancement to the hstogram can acheve mage dehaze effect. (6) (7) FPGA mplementaton Due to FPGA propertes of ASIC fuson and processor based system, t can be programmed n hgh speed parallel scene to make hgh speed parallel data processng, complex calculaton, mass data processng. By the development of IC craft, FPGA becomes more and more mportant n dgtals wth ts advantages lke good performance, cost, stablty and convenence n mantenance and upgrade. FPGA outruns PC software and DSP/ARM on effcency and bandwdth through 228

4 hardware acceleraton n dgtal mages processng. Meanwhle FPGA has succeeded n ARM and logcal embedded system whch s advantageous to parallel computng and complex control. Ths paper uses FPGA of Altera Cyclone IV generaton, type s EP4CE22E17C8N, ths chp has LE, 132 embedded multplers, 594KB RAM, 154 user IO, etc. whch s enough for Retnex mplementaton. The software s Quartus II 13.0, programmed through Verlog HDL, usng logc crcut to mplement and verfy hardware acceleraton of Retnex mage process algorthm. USB communcaton mechansm s appled to complete partcular mages transmts for process and analyss. And the framework of FPGA hardware acceleraton mage processng s shown n fgure 1: Fg.1 FPGA hardware framework of Retnex algorthm Shown n Fg. 1, through PC software termnal and USB 2.0 protocol, the partcular mages would be sent to FPGA. The hardware uses proven USB 2.0 controllers of Cypress to complete data transmt-receve. FPGA through the ranks of the cache and the parallel hardware acceleraton mplements Retnex algorthm logcal schema. After mage processng, FPGA passes mages to PC by USB and to VGA for dsplay by SDRAM n order to observe, save, and analyze. It s very approprate to mplement Retnex on mage real tme processng wth Verlog HDL programmng and rch multplers and RAM n FPGA. In ths paper, through Shft-RAM wthn the FPGA, complete mage cache operatons on a certan scale. Ths algorthm has only several clock perods, whch means even nothng comparng to PC software. Shown as Fg. 2, t s smulaton wave form result usng Modelsm for Shf-RAM and sngle channel Retnex. The experment verfes that the results ft the desgn algorthm and logc applcaton can be acheved. Fg.2 Modelsm Retnex Algorthm Smulaton Test Wave 229

5 Result and analyss Fg. 1, 2 and 3 are all processed by Retnex, (a) s orgnal mage, (b) s processed by matlab, ( s processed by FPGA. It s can be seen that Rentnex has good dehaze effect and mage qualty damaged a lttle after FPGA mplementaton. (a) (b) ( Fg.3 Effect mages of Retnex Algorthm Concluson Ths paper mproved and optmzed Retnex algorthm based on FPGA propertes, speeded up the mage processng whle balanced the algorthm effect. And transplant the optmzed algorthm to FPGA development kt of Altera whch verfed t doable and correctness. Compared to software mplementaton, FPGA sgnfcantly mproved the processng effcency of the algorthm and made cost lower and carrage easer whch would fully satsfy the dehaze of mages n transportaton. Reference [1]. E. Land, J. McCann. Lghtness and retnex theory. J. Journal of the Optcal Socety of Amerca,1971,(01):7-21. [2]. E. Land. An alternatve technque for the computaton of the desgnator n the retnex theory of color vson. J. Proceedngs of the Natonal Academy of Scences(USA),1986,(10): [3]. D. J. Jobson, Z. U. Rahman, G. A. Woodell. Propertes ans performance of a center/surround Retnex. J. IEEE Transactons on Image Processng,1997,(03): [4]. Z. U. Rahman, D. J. Jobson, G. A. Woodell. A multscale retnex for color redton and dynamc range ccompresson. on do ,2012. [5]. Y. Lu, X. Gao. New algorthm for nght Vson mage enhancement processng. J. INFRARED AND LASER ENGINEERING S4: [6]. Altera. Quartus II 13.0 Handbook. Amerca, [7]. X. Sun, A. Yu. VC++ n-depth Xangje. Electrc Industral Press

6 [8]. Altera. Cyclone v handbook. Amerca, [9]. Zhaguo Fang, Huang We, Cheng Yun desgn [J] FPGA-based USB nterface camera mage data transmsson system of the Sxth Natonal sgnals and Intellgent Informaton Processng and Applcaton Conference [10] Lang A fast adaptve scale Retnex-based mage enhancement algorthm [J]. Nnth Natonal Optcal Technology Symposum [11]. L,Yuecheng Zhang, Hong You etc. A mult-scale retnex mplementaton on FPGA for an outdoor applcaton[j]. Internatonal Congress on Image and Sgnal Processng (CISP 2011)

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