GALS System Design. Side Channel Attack Secure Cryptographic Accelerators. Frank K. Gürkaynak. Integrated Systems Laboratory ETH Zurich
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1 GLS System esign Side Channel ttack Secure Cryptographic ccelerators Frank K. Gürkaynak Integrated Systems Laboratory ETH Zurich 22 November 2005 Ph.. Thesis Presentation
2 Intro GLS Crypto cacia Results G C R KGF Contents Motivation Outline 1 Outline 2 Globally-synchronous Locally-Synchronous (GLS) esign 3 Cryptography 4 GLS implementation of the ES lgorithm 5 Results and Conclusions GLS System esign kgf, Integrated Systems Laboratory (IIS) 2 / 48
3 Intro GLS Crypto cacia Results G C R KGF Contents Motivation What is wrong with the way we design chips now? Modern System-on-Chip circuits... Contain millions of transistors Require clock rates exceeding 100s of MHz Include 100s of subblocks Use 10s of different clock domains GLS System esign kgf, Integrated Systems Laboratory (IIS) 3 / 48
4 Intro GLS Crypto cacia Results G C R KGF Contents Motivation What is wrong with the way we design chips now? Modern System-on-Chip circuits... Contain millions of transistors, trend increasing Require clock rates exceeding 100s of MHz, trend increasing Include 100s of subblocks, trend increasing Use 10s of different clock domains, trend increasing GLS System esign kgf, Integrated Systems Laboratory (IIS) 3 / 48
5 Intro GLS Crypto cacia Results G C R KGF Contents Motivation What is wrong with the way we design chips now? Modern System-on-Chip circuits... Contain millions of transistors, trend increasing Require clock rates exceeding 100s of MHz, trend increasing Include 100s of subblocks, trend increasing Use 10s of different clock domains, trend increasing... are not easy to design The clock signal must be distributed to an increasing number of elements with increased precision Many independently designed components must be combined to a large system. ll subsystems must be able to reliably exchange data GLS System esign kgf, Integrated Systems Laboratory (IIS) 3 / 48
6 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages Globally-synchronous Locally-Synchronous esign GLS is a methodology to enable the design of complex digital systems on chip. System is divided into smaller GLS modules Each module works synchronously Interconnected modules communicate asynchronously GLS System esign kgf, Integrated Systems Laboratory (IIS) 4 / 48
7 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages Globally-synchronous Locally-Synchronous esign GLS is a methodology to enable the design of complex digital systems on chip. System is divided into smaller GLS modules Each module works synchronously Interconnected modules communicate asynchronously Was first developed by. Chapiro in 1984 First chip implementation by J. Muttersbach in 1999 GLS System esign kgf, Integrated Systems Laboratory (IIS) 4 / 48
8 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages Globally-synchronous Locally-Synchronous esign GLS is a methodology to enable the design of complex digital systems on chip. System is divided into smaller GLS modules Each module works synchronously Interconnected modules communicate asynchronously Was first developed by. Chapiro in 1984 First chip implementation by J. Muttersbach in 1999 GLS implementations differ in: synchronization method between blocks specific asynchronous communication protocol used GLS System esign kgf, Integrated Systems Laboratory (IIS) 4 / 48
9 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages Basic GLS Structure ata Synchronous Block Synchronous Block B Clk Clk Synchronous system Two large functional blocks of a synchronous system GLS System esign kgf, Integrated Systems Laboratory (IIS) 5 / 48
10 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages Basic GLS Structure GLS Module GLS Module B Locally Synchronous Island ataout atain Locally Synchronous Island B Lclk Lclk Local Clock Generator Local Clock Generator Local clock generators GLS modules are formed by adding a local clock generator for each functional block GLS System esign kgf, Integrated Systems Laboratory (IIS) 5 / 48
11 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages Basic GLS Structure GLS Module GLS Module B Locally Synchronous Island Pen Ta ataout Port Req ck atain Port Pen Ta Locally Synchronous Island B Lclk Local Clock Generator Ri i Ri i Lclk Local Clock Generator GLS system Port controllers are added to regulate data transfers between GLS modules GLS System esign kgf, Integrated Systems Laboratory (IIS) 5 / 48
12 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages GLS Works GLS at IIS J. Muttersbach First implementation T. Villiger S. Oetiker F. K. Gürkaynak GLS System esign kgf, Integrated Systems Laboratory (IIS) 6 / 48
13 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages GLS Works GLS at IIS J. Muttersbach T. Villiger Multi-point interconnect S. Oetiker F. K. Gürkaynak GLS System esign kgf, Integrated Systems Laboratory (IIS) 6 / 48
14 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages GLS Works GLS at IIS J. Muttersbach T. Villiger S. Oetiker Local clock generators F. K. Gürkaynak GLS System esign kgf, Integrated Systems Laboratory (IIS) 6 / 48
15 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages GLS Works GLS at IIS J. Muttersbach T. Villiger S. Oetiker F. K. Gürkaynak esign and test flow GLS System esign kgf, Integrated Systems Laboratory (IIS) 6 / 48
16 Intro GLS Crypto cacia Results G C R KGF Overview Structure GLS@IIS dvantages Why GLS? dvantages No global clock distribution problems Modular design flow Potential for low-power design Offers new possibilities for designers GLS System esign kgf, Integrated Systems Laboratory (IIS) 7 / 48
17 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P Cryptography 101 LICE OSCR BOB Plain-text Encryption Cipher-text ecryption Plain-text Cipher-key Cipher-key Private key ciphers lice encrypts plain-text information by using a cipher-key. Bob can decrypt the resulting cipher-text only if he has access to the same cipher-key. GLS System esign kgf, Integrated Systems Laboratory (IIS) 8 / 48
18 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P Cryptography 102 LICE OSCR BOB Plain-text Encryption Cipher-text ecryption Plain-text Cipher-key Cipher-key Security Oscar wishes to obtain the plain-text Oscar knows everything about the cryptographic algorithm Oscar can observe/modify the cipher-text but.. GLS System esign kgf, Integrated Systems Laboratory (IIS) 9 / 48
19 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P Cryptography 102 LICE OSCR BOB Plain-text Encryption Cipher-text ecryption Plain-text Cipher-key Cipher-key Security Oscar wishes to obtain the plain-text Oscar knows everything about the cryptographic algorithm Oscar can observe/modify the cipher-text but.. Oscar does not know the cipher-key GLS System esign kgf, Integrated Systems Laboratory (IIS) 9 / 48
20 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P dvanced Encryption Standard (ES) Plaintext RoundKey ES Standard by NIST bit data 128 bit key 10/12/14 rounds Components ShiftRows State Register S00 S10 S20 S30 S01 S11 S21 S31 S02 S12 S22 S32 S03 S13 S23 S33 ShiftRows ddroundkey SubBytes MixColumns X X X X X X X X X X X X X X X X Ciphertext GLS System esign kgf, Integrated Systems Laboratory (IIS) 10 / 48
21 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P dvanced Encryption Standard (ES) Plaintext RoundKey ES Standard by NIST bit data 128 bit key 10/12/14 rounds Components ShiftRows ddroundkey State Register S00 S10 S20 S30 S01 S11 S21 S31 S02 S12 S22 S32 S03 S13 S23 S33 ShiftRows ddroundkey SubBytes MixColumns X X X X X X X X X X X X X X X X Ciphertext GLS System esign kgf, Integrated Systems Laboratory (IIS) 10 / 48
22 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P dvanced Encryption Standard (ES) Plaintext RoundKey ES Standard by NIST bit data 128 bit key 10/12/14 rounds Components ShiftRows ddroundkey SubBytes State Register S00 S10 S20 S30 S01 S11 S21 S31 S02 S12 S22 S32 S03 S13 S23 S33 ShiftRows ddroundkey SubBytes MixColumns X X X X X X X X X X X X X X X X Ciphertext GLS System esign kgf, Integrated Systems Laboratory (IIS) 10 / 48
23 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P dvanced Encryption Standard (ES) Plaintext RoundKey ES Standard by NIST bit data 128 bit key 10/12/14 rounds Components ShiftRows ddroundkey SubBytes MixColumns State Register S00 S10 S20 S30 S01 S11 S21 S31 S02 S12 S22 S32 S03 S13 S23 S33 ShiftRows ddroundkey SubBytes MixColumns X X X X X X X X X X X X X X X X Ciphertext GLS System esign kgf, Integrated Systems Laboratory (IIS) 10 / 48
24 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P Side-Channels Once an otherwise secure algorithm is implemented in either Hardware or Software it gains physical properties that can be observed: Time required to finish the operation Power consumption Electromagnetic Radiation Heat dissipation Sound These properties are called Side Channels Side-Channel ttacks In 1996, P. Kocher showed that it is possible to obtain additional information on the cipher-key by observing these side-channels. GLS System esign kgf, Integrated Systems Laboratory (IIS) 11 / 48
25 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P ifferential Power nalysis (P) 1 Select a subkey and a target operation 2 Use a simple model to predict the power consumption for S input vectors Cryptographic Hardware Under ttack Measurement S input vectors Simple Power Model of Cryptographic Hardware P 0 P 1 P 2 S vectors H 0,0 H 1,0 H 0,1 H 1,1 H 0,2 H 1,2 H K,0 H K,1 H K,2 P S H 0,S H 1,S H K,S Statistical Evaluation of Model and Measurement GLS System esign kgf, Integrated Systems Laboratory (IIS) 12 / 48
26 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P ifferential Power nalysis (P) 1 Select a subkey and a target operation 2 Use a simple model to predict the power consumption for S input vectors 3 predict the power consumption for all K subkey permutations Cryptographic Hardware Under ttack Measurement P 0 P 1 P 2 S input vectors S vectors Simple Power Model of Cryptographic Hardware K subkeys H 0,0 H 0,1 H 0,2 H 1,0 H 1,1 H 1,2 H K,0 H K,1 H K,2 P S H 0,S H 1,S H K,S Statistical Evaluation of Model and Measurement GLS System esign kgf, Integrated Systems Laboratory (IIS) 12 / 48
27 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P ifferential Power nalysis (P) 1 Select a subkey and a target operation 2 Use a simple model to predict the power consumption for S input vectors 3 predict the power consumption for all K subkey permutations 4 Measure the power consumption using the same S input vectors Cryptographic Hardware Under ttack Side Channel Information Measurement S vectors P 0 P 1 P 2 P S S input vectors Simple Power Model of Cryptographic Hardware H 0,0 H 0,1 H 0,2 H 0,S H 1,0 H 1,1 H 1,2 H 1,S H K,0 H K,1 H K,2 H K,S Statistical Evaluation of Model and Measurement GLS System esign kgf, Integrated Systems Laboratory (IIS) 12 / 48
28 Intro GLS Crypto cacia Results G C R KGF Basics Security ES Side-Channel ttacks P ifferential Power nalysis (P) 1 Select a subkey and a target operation 2 Use a simple model to predict the power consumption for S input vectors 3 predict the power consumption for all K subkey permutations 4 Measure the power consumption using the same S input vectors 5 etermine if one of the power hypotheses shows a distinctively higher correlation to the measurement. Cryptographic Hardware Under ttack Measurement S vectors S input vectors S vectors Statistical Evaluation of Model and Measurement Simple Power Model of Cryptographic Hardware K subkeys GLS System esign kgf, Integrated Systems Laboratory (IIS) 12 / 48 P 0 P 1 P 2 P S? H 0,0 H 0,1 H 0,2 H 0,S H 1,0 H 1,1 H 1,2 H 1,S H K,0 H K,1 H K,2 H K,S
29 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock CCI Clock Handshake ata 16 Block iagram The GLS implementation is called cacia. Operations are divided between a 128-bit Goliath and a 32-bit avid unit GOLITH Key Generator Round Key Memory INTERFCE bit Reg ddroundkey ShiftRows 32 VI 32-bit Reg SubBytes MixColumns GLS System esign kgf, Integrated Systems Laboratory (IIS) 13 / 48
30 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock CCI Clock Handshake ata 16 Block iagram The GLS implementation is called cacia. Operations are divided between a 128-bit Goliath and a 32-bit avid unit avid and Goliath are separate GLS modules GOLITH_GLS GOLITH Key Generator Round Key Memory INTERFCE 128 g2s 128-bit Reg ddroundkey ShiftRows Local Clock Generator g2d 32 VI_GLS d2g VI 32-bit Reg SubBytes MixColumns Local Clock Generator GLS System esign kgf, Integrated Systems Laboratory (IIS) 13 / 48
31 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Block iagram The GLS implementation is called cacia. Operations are divided between a 128-bit Goliath and a 32-bit avid unit avid and Goliath are separate GLS modules There is a second avid unit running in parallel. One round of ES requires 1 Goliath and 4 avid operations. CCI Clock Handshake ata 16 GOLITH_GLS Local Clock Generator GOLITH g2d d2g Key Generator Round Key Memory 32 VI_GLS 32-bit Reg SubBytes MixColumns VI Local Clock Generator g2s VI 128 VI_GLS INTERFCE 128-bit Reg ddroundkey ShiftRows 32-bit Reg SubBytes 32 MixColumns g2d d2g Local Clock Generator GLS System esign kgf, Integrated Systems Laboratory (IIS) 13 / 48
32 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Implemented Countermeasures ddkey / ShiftR S01 S02 S03 S04 MixC 1 S05 S06 S07 S08 MixC 2 S09 S10 S11 S12 MixC 3 S13 S14 S15 S16 MixC 4 Normal Operation The attacker will normally target a single operation, and will measure the power consumption of this particular clock cycle. GLS System esign kgf, Integrated Systems Laboratory (IIS) 14 / 48
33 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Implemented countermeasures ummy Oper. ummy Oper. ddkey / ShiftR S01 S02 S03 S04 S05 S06 S07 S08 S09 S10 S11 S12 S13 S14 S15 S16 ummy MixC 1 ummy ummy MixC 2 MixC 3 MixC 4 Inserting dummy operations Inserting random dummy cycles will confuse the attacker, since the targeted operation will not always be executed at a specific clock cycle. Unfortunately, this also increases the run-time. GLS System esign kgf, Integrated Systems Laboratory (IIS) 15 / 48
34 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Implemented Countermeasures ummy Oper. ummy Oper. ddkey / ShiftR S06 S08 S07 S05 S16 S14 S15 S13 S04 S02 S03 S01 S12 S10 S09 S11 ummy ummy MixC 2 MixC 4 ummy MixC 1 MixC 3 Change ordering of operations Independent operations can be re-ordered arbitrarily. Contrary to inserting dummy cycles, this does not increase the run-time. GLS System esign kgf, Integrated Systems Laboratory (IIS) 16 / 48
35 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Implemented Countermeasures ummy Oper. ummy Oper. ddkey / ShiftR S06 S16 S08 S07 S05 S14 S15 S13 ummy ummy MixC 2 MixC 4 S04 S02 S03 S01 S12 S10 S09 S11 MixC 3 ummy MixC 1 Parallelization Executing operations in parallel creates more activity at the same time, this appears as noise for the attacker. GLS System esign kgf, Integrated Systems Laboratory (IIS) 17 / 48
36 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Implemented Countermeasures ummy Oper. ummy Oper. ddkey / ShiftR S06 S08 S07 S05 S16 S14 S13 S15 ummy ummy MixC 2 MixC 4 S12 S09 S10 S11 S02 S03 S04 S01 MixC 3 ummy MixC 1 Parallelization Executing operations in parallel creates more activity at the same time, this appears as noise for the attacker. GLS System esign kgf, Integrated Systems Laboratory (IIS) 17 / 48
37 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Implemented Countermeasures ummy ummy ummy ummy Oper. ummy Oper. ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ddkey / ShiftR ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. S06 S08 S02 S03 S07 S05 S04 S01 MixC 4 MixC 3 MixC 2 MixC 1 S16 S14 S13 S12 S09 S15 S10 S11 Parallelization Executing operations in parallel creates more activity at the same time, this appears as noise for the attacker. GLS System esign kgf, Integrated Systems Laboratory (IIS) 17 / 48
38 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Implemented Countermeasures Goliath ummy ummy ummy ummy Oper. ummy Oper. ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ddkey / ShiftR ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. S06 S08 S02 S03 S07 S05 S04 S01 MixC 4 MixC 3 MixC 2 MixC 1 ummy Oper. avid Perels avid Tschopp S16 S14 S13 S12 S09 S15 S10 S11 Introducing GLS modules GLS modules have their own local clock generator, their clocks are independent and can not be controlled by the attacker GLS System esign kgf, Integrated Systems Laboratory (IIS) 18 / 48
39 Intro GLS Crypto cacia Results G C R KGF Block Basic ummy Re-order Parallel GLS Variable Clock Implemented Countermeasures Goliath ummy ummy ummy ummy Oper. ummy Oper. ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ummy ddkey / ShiftR ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. ummy Oper. S06 S08 S02 S03 S07 S05 S04 S01 MixC 4 MixC 3 MixC 2 MixC 1 ummy Oper. avid Perels avid Tschopp ummy S16 S14 S13 S12 S09 S15 S10 S11 Variable clock periods Each GLS module can randomly change its own clock period. This adds even more uncertainity GLS System esign kgf, Integrated Systems Laboratory (IIS) 19 / 48
40 Intro GLS Crypto cacia Results G C R KGF Chip Conclusions Final Chip Photo cacia UMC 0.25 µm CMOS Total area 1.75 mm 2 avid mm 2 Goliath mm 2 Sync mm 2 Rate Mb/s Energy mj/mb This part of the chip occupied by two independent ES designs: Baby and Pampers Synchronous Interface & Reference esign Clockgen Clockgen avid g2s Goliath d2g g2d d2g g2d Clockgen avid GLS System esign kgf, Integrated Systems Laboratory (IIS) 20 / 48
41 Intro GLS Crypto cacia Results G C R KGF Chip Conclusions Final Conclusions Conclusions novel GLS based crypto SIC implementing the ES algorithm was presented. In addition to traditional P countermeasures, the chip also includes GLS modules that use randomly varying clocks which make known attacks extremely difficult The GLS design methodology was refined. The presented design was designed using mainly standard E tools. combination of functional and scan-chain based testing allows a stuck-at-coverage of more than 99.8%. GLS System esign kgf, Integrated Systems Laboratory (IIS) 21 / 48
42 Intro GLS Crypto cacia Results G C R KGF Chip Conclusions Final Conclusions Conclusions novel GLS based crypto SIC implementing the ES algorithm was presented. In addition to traditional P countermeasures, the chip also includes GLS modules that use randomly varying clocks which make known attacks extremely difficult The GLS design methodology was refined. The presented design was designed using mainly standard E tools. combination of functional and scan-chain based testing allows a stuck-at-coverage of more than 99.8%. Is this really secure? We don t know yet. The security has to be evaluated by cryptanalysts. GLS System esign kgf, Integrated Systems Laboratory (IIS) 21 / 48
43 Intro GLS Crypto cacia Results G C R KGF Chip Conclusions Final QUESTIONS? cknowledgements for GLS Stephan Oetiker, Thomas Villiger, Hubert Kaeslin, Norbert Felber cknowledgements for Crypto-chips Stefan chleitner, Gérard Basler, ndres Erni, ominique Gasser, Peter Haldi, Franco Hug, drian Lutz, Norbert Pramstaller, Stefan Reichmuth, Pieter Rommens, Jürg Treichler, Stefan Zwicky and ndreas Burg, Matthias Braendli, Stefan Eberli, Simon Haene Stefan Mangard, Elisabeth Oswald, S. Berna Örs GLS System esign kgf, Integrated Systems Laboratory (IIS) 22 / 48
44 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow Timing iagram Locally Synchronous Island Clock Pen Ta Receiving GLS Module Req ck Local Clock Generator Ri i 1 GLS port is activated by the Pen signal, which enables Req GLS System esign kgf, Integrated Systems Laboratory (IIS) 23 / 48
45 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow Timing iagram Locally Synchronous Island Clock Pen Ta Receiving GLS Module Req ck Local Clock Generator Ri i 2 The receiving GLS module sets ck, clock pause request Ri is set GLS System esign kgf, Integrated Systems Laboratory (IIS) 23 / 48
46 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow Timing iagram Locally Synchronous Island Clock Pen Ta Receiving GLS Module Req ck Local Clock Generator Ri i 3 The clock pause is acknowledged by i, the LS Island is paused GLS System esign kgf, Integrated Systems Laboratory (IIS) 23 / 48
47 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow Timing iagram Locally Synchronous Island Clock Pen Ta Local clock is paused Receiving GLS Module Req ck Local Clock Generator Ri i 4 ata transfer is complete, Ta is set and Req is reset GLS System esign kgf, Integrated Systems Laboratory (IIS) 23 / 48
48 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow Timing iagram Locally Synchronous Island Clock Pen Ta Local clock is paused Receiving GLS Module Req ck Local Clock Generator Ri i 5 ll handshake signals return to their initial values, local clock is released GLS System esign kgf, Integrated Systems Laboratory (IIS) 23 / 48
49 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow Timing iagram Locally Synchronous Island Clock Pen Ta Local clock is paused Receiving GLS Module Req ck Local Clock Generator Ri i 6 Normal operation resumes, Ta remains active until the Pen is reset GLS System esign kgf, Integrated Systems Laboratory (IIS) 23 / 48
50 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow Local Clock Generator Ri i Ri i LClk elcntrlxsi ExtClk MUTEX MUTEX elay Register Programmable elay Line Muller-C elcntrlxsi(0) elcntrlxsi(1) elcntrlxsi(2) elcntrlxsi(15) ClkToelayxCI MUX22 N22 1 O212 N22 O212 N22 O212 0 N22 ClkelayedxCO 1 Fine elay elay Slice elay Slice elay Slice elay Slice GLS System esign kgf, Integrated Systems Laboratory (IIS) 24 / 48
51 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow Mutual exclusion element Vdd 3.9µ 0.24µ 3.9µ 0.24µ R1 2.56µ 0.24µ 2.56µ 0.24µ 3.9µ 0.24µ 1.28µ 0.24µ G2 Vdd 3.9µ 0.24µ 3.9µ 0.24µ R2 2.56µ 0.24µ 2.56µ 0.24µ 3.9µ 0.24µ 1.28µ 0.24µ G1 GLS System esign kgf, Integrated Systems Laboratory (IIS) 25 / 48
52 Intro GLS Crypto cacia Results G C R KGF Timing Clock Mutex Flow esign flow for GLS (as used in Shir-Khan) Self-timed library.stg 3 (UCS).eqn eqn2gate (ETHZ).v Signal Trans. Logic Graph Equations Local clock generator Gate Level Netlist.vhdl esign nalyzer (Synopsys).v Silicon Ensemble (Cadence).lef Pearl Timing n. (Cadence).tlf VHL Gate Level Source Code Netlist SIM micro-controller MacroCell Layout Timing Model.vhdl esign nalyzer (Synopsys).v Silicon Ensemble (Cadence).lef Pearl Timing n. (Cadence).tlf VHL Source Code GLS modules Gate Level Netlist MacroCell Layout Timing Model.gals module assembler (ETHZ).vhdl esign nalyzer (Synopsys).v Silicon Ensemble (Cadence).lef Pearl Timing n. (Cadence).tlf Configuration File.scr VHL Source Code Gate Level Netlist MacroCell Layout Timing Model Control Scripts GLS system.vhdl esign nalyzer (Synopsys).v Silicon.lef Pearl Calibre Ensemble Timing n. RC/LVS (Cadence) (Cadence) (Mentor).gds VHL Source Code Gate Level Netlist Layout Final Layout GLS System esign kgf, Integrated Systems Laboratory (IIS) 26 / 48
53 Intro GLS Crypto cacia Results G C R KGF Chips SubBytes Countermeasures P Setup ES implementations at IIS Riddler Fastcore res Baby / Pampers 2 x 128 bit parallel 128 bit 128 / 32 bit 16 bit 2.16 Gb/s (pipelined) 2.12 Gb/s 1.15 Gb/s (128 bit) / Gbit/s 37.8 mm 2 (0.6 µm) 3.56 mm 2 (0.25 µm) 1.2 mm 2 (0.25 µm) 0.35 / 0.58 mm 2 (0.25 µm En/ecryption (ECB) En/ecryption (all) Encryption (ECB/OFB) Encryption (ECB/OFB) Parallel atapath Independent Enc/ec Includes masking Plain / Countermeasures GLS System esign kgf, Integrated Systems Laboratory (IIS) 27 / 48
54 Intro GLS Crypto cacia Results G C R KGF Chips SubBytes Countermeasures P Setup SubBytes determines ES performance atapath width 8-bit 16-bit 32-bit 64-bit 128-bit Parallel SubBytes units Complexity (gate eq) 5,052 6,281 7,155 11,628 20,410 rea (normalized) Clock cycles for ES Critical path (normalized) Total time (normalized) GLS System esign kgf, Integrated Systems Laboratory (IIS) 28 / 48
55 Intro GLS Crypto cacia Results G C R KGF Chips SubBytes Countermeasures P Setup Countermeasures against P attacks Protect your weak spots P measures power consumption dd Noise (unrelated switching activity) to confuse the measurements P targets a specific operation Change the operation order by inserting Random Operations Power consumption of CMOS is data dependent Use lternative Logic Styles There are direct operations between input and output Prevent direct operations by Masking the key with random data GLS System esign kgf, Integrated Systems Laboratory (IIS) 29 / 48
56 Intro GLS Crypto cacia Results G C R KGF Chips SubBytes Countermeasures P Setup P attacks work Key 0x Correlation Number of measurements GLS System esign kgf, Integrated Systems Laboratory (IIS) 30 / 48
57 Intro GLS Crypto cacia Results G C R KGF Chips SubBytes Countermeasures P Setup P attack setup GLS System esign kgf, Integrated Systems Laboratory (IIS) 31 / 48
58 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag rea overhead of GLS avid Goliath rea µm 2 183, % 551, % rea µm 2 -LSFRs 26, % 73, % rea µm 2 -ClockGen 7, % 7, % rea µm 2 -Ports 6, % 11, % rea µm 2 -GLS 196, % 570, % rea µm 2 -TOTL 963,855 GLS System esign kgf, Integrated Systems Laboratory (IIS) 32 / 48
59 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag Latency overhead of GLS Synchronous GLS+P avid Goliath avid Goliath Critical path (ns) Latency (cycles) Clock freq. (MHz) Enc(clock cycles) Enc time (ns) GLS System esign kgf, Integrated Systems Laboratory (IIS) 33 / 48
60 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag Block diagram of avid atainxi ataoutxo 32 PolicyxI ModexSI PenxSO TaxSI ebugatainxi ebugenxsi ebugclkxci bit LFSR Controller Reg ffine Transform InvMixColumns Mult. Inverse Mult. Inverse MixColumns Inverse ffine T. Multiplicative Inverse Output Select ffine Transformation MixColumns GLS System esign kgf, Integrated Systems Laboratory (IIS) 34 / 48
61 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag Block diagram of Goliath atainxi ataoutxo ebugatainxi ebugddrinxi ebugenxsi ebugclkxci ModexSI PenxSO TaxSI bit LFSR 128 Controller Reg InvShiftRows Key Expansion x 32 SRM Reg-32 Reg-32 ddroundkey Output Select ShiftRows Reg-128 avid Communication ShiftRows ddroundkey Round Key Generator ToavidTxO FrmavidTxI FrmavidPxI ToavidPxO GLS System esign kgf, Integrated Systems Laboratory (IIS) 35 / 48
62 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag Goliath to Synchronous Interface Req+ Pen+ O211 Ri+ Pen i Ta INV1 i+ ck+ Req- Ta+ Ta- Req i OR21 Pen Req i Req NN41 NN21 NN31 Ri NN21 ck- Ri- Pen- i i- Req i N21 ck GLS System esign kgf, Integrated Systems Laboratory (IIS) 36 / 48
63 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag Goliath to avid O211 Pen+ i Pen Ta Req+ Ri+ Pen- Ta- O211 INV1 i+ INV1 ck+ Ta+ i- Req N21 Pen Ri ck- Req- Ri- N21 i ck GLS System esign kgf, Integrated Systems Laboratory (IIS) 37 / 48
64 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag avid to Goliath Ta- O211 i- Pen- Pen+ Pen i Z INV1 N21 Ri- Req+ Pen Req BUFL ck- ck+ ck Ri INV1 Req- Ta+ Ri+ i i+ Z OR21 Pen N31 Ta GLS System esign kgf, Integrated Systems Laboratory (IIS) 38 / 48
65 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag Scan-test configuration GLS Module LS Island GLS Module LS Island Pen Ta FSM Req ck FSM Pen Ta Lclk Ri i Ri i Lclk Local Clock Local Clock Generator Local Clock Local Clock Generator ScanIn ScanEn ScanClk ScanOut GLS System esign kgf, Integrated Systems Laboratory (IIS) 39 / 48
66 Intro GLS Crypto cacia Results G C R KGF rea Latency avid Goliath G2S G2 2G Test Coverag Stuck-at-fault test coverage Stuck-at-fault testing There are a total of stuck-at faults in the entire circuit Only 182 of these faults are within the asynchronous finite state machines straighforward test vector generation using TetraMax fails to detect faults Using a simple encryption/decryption operation of these faults were detected by simulation. The total test coverage obtained by combining these two methods exceeds 99.8%. GLS System esign kgf, Integrated Systems Laboratory (IIS) 40 / 48
67 Intro GLS Crypto cacia Results G C R KGF Modes Sim Performance Period Freq Power Power/Mode istribution of the first SubBytes operation Frequency Frequency Frequency Frequency Mode 00 : s fast as possible Mode 01 : Slightly Random Mode 10 : Mostly Random Mode11: Pre-programmed Policy Time [ns] GLS System esign kgf, Integrated Systems Laboratory (IIS) 41 / 48
68 Intro GLS Crypto cacia Results G C R KGF Modes Sim Performance Period Freq Power Power/Mode Simulation result Interface Clk Req ck Req Input for Next Operation ck Output of Last Operation Strb Goliath Request to start cknowledge Req ck Start End Clk avid Tschopp more random less random fast less random more random Clock Pause Req ck Clk avid Perels Req ck Clk ~100MHz ~120MHz ~170MHz ~190MHz ~200MHz ~200MHz ~200MHz ~190MHz ~180MHz ~150MHz 7200 ns 7600 ns 8 us GLS System esign kgf, Integrated Systems Laboratory (IIS) 42 / 48
69 Intro GLS Crypto cacia Results G C R KGF Modes Sim Performance Period Freq Power Power/Mode Operation modes of cacia Operation I/O Clock Encr. Throughput Energy Mode [MHz] [ns] [Mb/s] [mj/mb] cacia cacia cacia , cacia Synchronous GLS System esign kgf, Integrated Systems Laboratory (IIS) 43 / 48
70 Intro GLS Crypto cacia Results G C R KGF Modes Sim Performance Period Freq Power Power/Mode Clock period versus delay-line settings cacia Local Clock Generator Period (Chip #1) 14 Goliath. Perels. Tschopp Simulation 12 Local Clock Period [ns] Number of elay Slices GLS System esign kgf, Integrated Systems Laboratory (IIS) 44 / 48
71 Intro GLS Crypto cacia Results G C R KGF Modes Sim Performance Period Freq Power Power/Mode Clock frequency versus delay-line settings Goliath Clock Generator Frequency (Chip #1-Chip #14) Chip #1 Chip #14 Simulation Local Clock Frequency [MHz] Number of elay Slices GLS System esign kgf, Integrated Systems Laboratory (IIS) 45 / 48
72 Intro GLS Crypto cacia Results G C R KGF Modes Sim Performance Period Freq Power Power/Mode Power consumption vs maximum GLS module frequency 260 cacia Power issipation 240 Power Consumption [mw] Clock Frequency of GLS Modules [MHz] GLS System esign kgf, Integrated Systems Laboratory (IIS) 46 / 48
73 Intro GLS Crypto cacia Results G C R KGF Modes Sim Performance Period Freq Power Power/Mode Power consumption of different operation modes Mode00 Mode01 Mode10 Mode11 cacia Power issipation with ifferent Operation Modes 230 Power Consumption [mw] I/O Clock Period [MHz] GLS System esign kgf, Integrated Systems Laboratory (IIS) 47 / 48
74 Intro GLS Crypto cacia Results G C R KGF F. Kağan Gürkaynak in KG GLS System esign kgf, Integrated Systems Laboratory (IIS) 48 / 48
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