Momentary Changes in Outputs. State Machine Signaling. Oscillatory Behavior. Hazards/Glitches. Types of Hazards. Static Hazards

Transcription

1 State Machine Signaling Momentary hanges in Outputs Timing ehavior Glitches/hazards and how to avoid them SM Partitioning What to do when the state machine doesn t fit! State Machine Signaling State Machine Retiming Introducing Idle States (synchronous model) our ycle Signaling (asynchronous model) ealing with synchronous Inputs Metastability and synchronization S 5 - Spring 24 Lec #6 Signaling - an be useful pulse shaping circuits an be a problem incorrect circuit operation (glitches/hazards) Example: pulse shaping circuit ' = delays matter in function remains high for three gate delays after changes from low to high S 5 - Spring 24 Lec #6 Signaling - 2 is not always pulse 3 gate-delays wide Oscillatory ehavior Hazards/Glitches nother pulse shaping circuit resistor open switch + Hazards/glitches: unwanted switching at the outputs Occur when different paths through circuit have different propagation delays s in pulse shaping circuits we just analyzed angerous if logic causes an action while output is unstable May need to guarantee absence of glitches close switch initially undefined open switch Usual solutions ) Wait until signals are stable (by using a clock): preferable (easiest to design when there is a clock synchronous design) 2) esign hazard-free circuits: sometimes necessary (clock not used asynchronous design) S 5 - Spring 24 Lec #6 Signaling - 3 S 5 - Spring 24 Lec #6 Signaling - 4 Types of Hazards Static Hazards Static -hazard Input change causes output to go from to to Static -hazard INput change causes output to go from to to ue to a literal and its complement momentarily taking on the same value Thru different paths with different delays and reconverging May cause an output that should have stayed at the same value to momentarily take on the wrong value Example: ynamic hazards Input change causes a double change from to to to OR from to to to S S S' S' static- hazard static- hazard hazard S 5 - Spring 24 Lec #6 Signaling - 5 S 5 - Spring 24 Lec #6 Signaling - 6

2 ynamic Hazards Eliminating Static Hazards ue to the same versions of a literal taking on opposite values Thru different paths with different delays and reconverging May cause an output that was to change value to change 3 times instead of once Example: 3 2 dynamic hazards 2 S 5 - Spring 24 Lec #6 Signaling hazard ollowing 2-level logic function has a hazard, e.g., when inputs change from = to G G G3 G3 \ \ = = No Glitch in this case This is the fix \ Glitch in this case G G G G3 G3 G3 \ \ = = ( is still ) = ( is ) S 5 - Spring 24 Lec #6 Signaling - 8 Eliminating ynamic Hazards SM Partitioning \ \ G Slow G3 \ G4 V ery slow G5 Very difficult! circuit that is static hazard free can still have dynamic hazards est approach: esign critical circuits to be two level and eliminate all static hazards OR, use good clocked synchronous design style Why Partition? What if programmable logic is limited in number of inputs and outputs that can be used in a particular device? or PLs/PLs, the number of product terms are limited, thus limiting the complexity of the next state and output functions S 5 - Spring 24 Lec #6 Signaling - 9 S 5 - Spring 24 Lec #6 Signaling - Partitioning the State Machine Partitioning the State Machine Suppose that SM is partitioned so that states at the right are in one partition and states at the left are in the other How do you support intersignaling between the state machine partitions? It is usually a good idea to partition the machine so there are as few cross links as possible (min cut set in graph theoretic terms) Solution: introduce idle states S and S Machine at left enters S allowing machine at right to exit S When machine at right returns to S, machine at left exits S S 5 - Spring 24 Lec #6 Signaling - S 5 - Spring 24 Lec #6 Signaling - 2

3 Rules for Introducing Idle States Example: Partitioning the Up/own ounter S 5 - Spring 24 Lec #6 Signaling - 3 S 5 - Spring 24 Lec #6 Signaling - 4 Example Partitioning: Traffic Light ontroller Partitioned SM lock iagram Main ontroller vs. ounter/timer ST triggers transfer of control TS or TL triggers return of control TS' (TL )' TL / ST HY HG Reset TS / ST Y TS' T T T2 T3 ST T9 T8 T7 T T T2 T9 [TL] T8 T7 T6 reset traffic light controller ST TS TL timer HR HY HG R Y G Interface between the two partitions are the signals ST, TS, TL NOTE: Main ontroller and Timer use the same clock and are operating in a synchronous mode TS / ST TL+' / ST G (TL+')' T4 [TS] T6 T3 T5 (a) Main controller T5 (b) ounter/timer T4 S 5 - Spring 24 Lec #6 Signaling - 5 S 5 - Spring 24 Lec #6 Signaling - 6 State Machine Retiming State Machine Retiming Moore vs. (sync) Mealy Machine Vending Machine Example Retiming the Moore Machine: aster generation of outputs Synchronizing the Mealy Machine: dd a, delaying the output These two implementations have identical timing behavior Open asserted only when in state 5 S 5 - Spring 24 Lec #6 Signaling - 7 Open asserted when last coin inserted leading to state 5 Push the N gate through the State s and synchronize with an output Like computing open in the prior state and delaying it one state time S 5 - Spring 24 Lec #6 Signaling - 8

4 State Machine Retiming Generalized Inter-SM Signaling Timing behavior is the same, but are the implementations really identical? Interlocked Synchronized Signaling input in retimed Moore implementation Only difference in don t care case of nickel and dime at the same time input in synchronous Mealy implementation S 5 - Spring 24 Lec #6 Signaling - 9 S 5 - Spring 24 Lec #6 Signaling - 2 synchronous Signaling synchronous Signaling lso known as speed-independent signaling uester/client/master vs. Provider/Server/Slave locked Subsystem S requester client master ommunications Signals uest ata low cknowledgement locked Subsystem S 5 - Spring 24 Lec #6 Signaling - 2 S2 provider server slave irst consider the common clock case (synchronous) Master asserts uest Slave recognizes request, processes request, indicates completion by asserting cknowledgement Master accepts results, removes uest ata ck lk Slave see uest removed, removes cknowledge S 5 - Spring 24 Lec #6 Signaling - 22 synchronous Signaling True synchronous Signaling What if Slave can t respond in single cycle? Solution: Wait signaling ata W ait lk Slave inhibits master by asserting wait When slave unasserts wait, master knows request has been processed, and can latch results S 5 - Spring 24 Lec #6 Signaling - 23 Now remove the assumption of a single common clock How do we make sure that receiver has seen the sender s signal? Solution: Interlocked signaling our cycle signaling: assert, process request, assert ack, latch result, remove, remove ck and start again Sometimes called Return to Zero signaling ata ck S 5 - Spring 24 Lec #6 Signaling - 24

5 True synchronous Signaling True synchronous Timing lternative scheme: Two-ycle Signaling Non-return-to-zero signaling Transaction start by lo-to-hi, finishes ck lo-to-hi Next transaction starts by hi-to-lo, finishes ck hi-to-lo ata uires EXTR state to keep track of the current sense of the transitions faster than 4 cycle case, but usually involves more hardware Self-Timed ircuits Uses /ck signaling as described omponents can be constructed with NO internal clocks etermines on its own when the request has been processed oncept of the delay line simply slows down the pass through of the to the ck usually matched to the worst case delay path ecoming MORE important for large scale VLSI chips were global clock distribution is a challenge Input ombinational logic elay Output ck ck S 5 - Spring 24 Lec #6 Signaling - 25 S 5 - Spring 24 Lec #6 Signaling - 26 Metastability and synchronous inputs Synchronization ailure locked synchronous circuits Inputs, state, and outputs sampled or changed in relation to a common reference signal (called the clock) E.g., master/slave, edge-triggered synchronous circuits Inputs, state, and outputs sampled or changed independently of a common reference signal (glitches/hazards a major concern) E.g., R-S latch synchronous inputs to synchronous circuits Inputs can change at any time, will not meet setup/hold times angerous, synchronous inputs are greatly preferred annot be avoided (e.g., reset signal, memory wait, user input) S 5 - Spring 24 Lec #6 Signaling - 27 Occurs when input changes close to clock edge may enter a metastable state neither a logic nor May stay in this state an indefinite amount of time Is not likely in practice but has some probability logic logic logic logic small, but non-zero probability oscilloscope traces demonstrating that the output will get stuck synchronizer failure and eventual in an in-between state decay to steady state S 5 - Spring 24 Lec #6 Signaling - 28 ealing with Synchronization ailure Handling synchronous Inputs Probability of failure can never be reduced to, but it can be reduced () slow down the system clock: this gives the synchronizer more time to decay into a steady state; synchronizer failure becomes a big problem for very high speed systems (2) use fastest possible logic technology in the synchronizer: this makes for a very sharp "peak" upon which to balance (3) cascade two synchronizers: this effectively synchronizes twice (both would have to fail) Never allow asynchronous inputs to fan-out to more than one flip-flop Synchronize as soon as possible and then treat as synchronous signal sync Input locked Synchronous System lock sync Input Synchronizer lock asynchronous input synchronized input lock lock lk S 5 - Spring 24 Lec #6 Signaling - 29 synchronous system S 5 - Spring 24 Lec #6 Signaling - 3

6 Handling synchronous Inputs (cont d) Signaling Summary What can go wrong? In LK Input changes too close to clock edge (violating setup time constraint) S 5 - Spring 24 Lec #6 Signaling - 3 In is asynchronous and fans out to and one catches the signal, one does not inconsistent state may be reached! Glitches/Hazards Introduce redundant logic terms to avoid them OR use synchronous design! SM Partitioning Replacing monolithic State Machine with simpler communicating state machine Technique of introducing idle states State Machine Retiming Rearranging the logic/s in a state machine to speed up its output signaling behavior Machine-to-machine Signaling Synchronous vs. asynchronous our vs. Two ycle Signaling synchronous inputs and their dangers Synchronizer failure: what it is and how to minimize its impact S 5 - Spring 24 Lec #6 Signaling - 32