Introduction to Digital Logic Missouri S&T University CPE 2210 Flip-Flops

Transcription

1 Introduction to igital Logic Missouri S&T University CPE 2210 Flip-Flops Egemen K. Çetinkaya Egemen K. Çetinkaya epartment of Electrical & Computer Engineering Missouri University of Science and Technology 7 March 2018 rev Egemen K. Çetinkaya

2 Introduction Flip-flops and types Summary Flip-Flops Outline 2

3 igital Logic Circuit Types What are the type of digital circuits? 3

4 igital Logic Circuit Types What are the type of digital circuits? Combinatorial output solely depends on present values of input(s) no memory basic blocks of circuits e.g.: lamp with light sensor Sequential output depends on present and past values of input(s) output depends on present state e.g.: calculator 4

5 Sequential Logic Circuits Examples Egemen K. Çetinkaya What are examples of sequential circuit elements? 5

6 Sequential Logic Circuits Examples Examples of sequential logic elements: Latches Flip-flops Registers Controllers Counters 6

7 Basic SR Latch Using NOR Gates We can change state of simple memory using latch NOR gates are connected cross-coupled style S (set) SR latch S R t ( ) 0 0 1/0 0/1 no change R (reset)

8 Level-Sensitive SR Latch Circuit and Symbol SR latch with enable input is a level-sensitive SR latch C is the enable input S C R Level-sensitive SR latch S1 R1 C S R (t+1) 0 x x no change no change x S C R Level-sensitive SR latch symbol 8

9 Level-Sensitive Latch Circuit and Symbol SR latch with enable input and inverter is a latch C is the enable input S S1 latch C (t+1) C 0 x no change C R R latch symbol 9

10 Review uestion Overview Can we do latch functions using NAN gates? instead of NOR gates 10

11 Review uestion Overview 11

12 Review uestion Overview 12

13 Latch Problem elay When C is 1, how many latches will the signal travel? Y 1 1? 1? 1? C1 C2 C3 C4 Clk 13

14 Latch Problem elay When C is 1, how many latches will the signal travel? epends on clk signal: Clk_A: signal may travel through multiple latches Clk_B: signal may travel through fewer latches Y 1 1? 1? 1? C1 C2 C3 C4 Clk Clk_A Clk_B 14

15 1 S1 Latch Problem elay latch 0 >1 0 >1 2 0 >1 S2 0 >1 latch C1 C Clk Clk 1 1/2 S2 R2 2 R1 1 0 >1 Long clock 2nd latch set 1 >0 15 Clk 1 1/2 S2 R2 2 R2 1 >0 2 0 >1 Short clock C3 1 doesn't change C4

16 Latch Problem elay Issue: how to adjust clock cycle for right timing? Can we design bit storage that only stores a value on the rising edge of the clock signal? 16

17 Latch Problem elay Issue: how to adjust clock cycle for right timing? Can we design bit storage that only stores a value on the rising edge of the clock signal? rising edges Clk Level-sensitive vs. edge-triggered: level-sensitive: sensitive to signal level edge-triggered: sensitive to rise/fall of the signal 17

18 Edge-Triggered Flip-Flop Master-Servant esign Flip-flop: stores 1 bit on clock edge flip-flop uses two latches Master-servant is one design, there are others flip-flop latch m m s latch s Cm Cs s master servant Clk 18

19 Clk=0 Edge-Triggered Flip-Flop Timing iagram Egemen K. Çetinkaya master enabled, loads, appears at m, servant disabled Clk=1 Clk master disabled, m stays same servant latch enabled, loads m, appears at s latch m Cm m master s Cs flip-flop latch s servant s 19 Clk /m Cm m/s Cs s

20 Edge-Triggered Flip-Flop Symbols Egemen K. Çetinkaya Symbol for rising-edge triggered flip-flop rising edges Clk Symbol for falling-edge triggered flip-flop Clk falling edges 20

21 Edge-Triggered Flip-Flop Timing iagram Egemen K. Çetinkaya Solves problem of not knowing through how many latches a signal travels when C=1 How many flip-flops does signal travel in each cycle Y Two latches inside each flip-flop Clk Clk_A Clk_B 21

22 Edge-Triggered Flip-Flop Timing iagram Solves problem of not knowing through how many latches a signal travels when C=1 How many flip-flops does signal travel in each cycle? Signal travels exactly one flip-flop per cycle Y Two latches inside each flip-flop Clk Clk_A Clk_B 22

23 Latch vs. Flip-Flop Comparison Latch is level-sensitive, stores when C=1 Flip-flop is edge triggered, stores when C 0 1 Clk ( latch) ( flip-flop) Latch follows while Clk is 1 Flip-flop only loads during Clk rising edge 23

24 Review uestion Overview Construct the timing diagram for the following a Clock Clk a Clock b a b b c c c 24

25 Review uestion Overview Construct the timing diagram for the following a Clock Clk a Clock b a b b c c c 25

26 Similar to SR latch SR Flip-Flop Overview However, instead of changing state with level change It changes state with edge rise/fall 26

27 SR Flip-Flop Symbol and Characteristic Table SR flip-flop: Similar to SR latch, edge-triggered Egemen K. Çetinkaya S R S R (t+1) 0 0 no change (t) X 27

28 T flip-flop: toggle flip-flop T Flip-Flop Overview The output toggles on the rising edge of clock The circuit diagram: T Clock 28

29 T Flip-Flop Symbol and Characteristic Table T flip-flop: toggle flip-flop The output toggles on the rising edge of clock T T (t+1) 0 (t) 1 (t) 29

30 T flip-flop: toggle flip-flop T Flip-Flop Timing iagram The output toggles on the rising edge of clock T T (t+1) 0 (t) 1 (t) Clock T 30

31 T flip-flop: toggle flip-flop T Flip-Flop Timing iagram The output toggles on the rising edge of clock T T (t+1) 0 (t) 1 (t) Clock T 31

32 JK Flip-Flop Overview JK flip-flop: combines features of SR and T flip-flops Instead of T only, we use J and K inputs = J +K The circuit: J K Clock 32

33 JK Flip-Flop Symbol and Characteristic Table JK flip-flop: toggle flip-flop Egemen K. Çetinkaya J K J K (t+1) 0 0 no change (t) toggle (t) 33

34 Flip-Flops Clear and Preset It might be needed to have clear and preset button If clear is 0, is forced to be in 0 e.g. clear counter to be initial state to be 0 If preset is 0, is forced to be in 1 e.g. insert specific value as initial value of a counter Preset Clear 34

35 Clock Signals Overview Clock input is connected to clock signal It is from an oscillator signal Generates pulsing signal What is the period? What is the frequency? How many cycles are there? Osc. Clk 1 Clk 0 Time: 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns

36 Clock Signals Overview Clock input is connected to clock signal It is from an oscillator signal Generates pulsing signal What is the period? 20 ns What is the frequency? 1/20 ns=50 MHz How many cycles are there? 3.5 Osc. Clk 1 Clk 0 Time: 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns

37 Clock Signals Overview Clock input is connected to clock signal It is from an oscillator signal Generates pulsing signal T=1/f Synchronous circuit: storage elements change with clock Asynchronous circuit: storage elements that does not use clock 37

38 Storing Multiple Bits Registers Register: multiple flip-flops sharing common clock More about registers later I3 I2 I1 I0 clk 4-bit register I3 I2 I1 I0 reg(4)

39 Flip-flops store one bit Flip-Flops Summary Latches are level-sensitive Flip-flops are edge-triggered Signal travels one cycle per flip-flop -flip-flops are most commonly used Flip-flop types: SR, JK,, T Two types of flip-flops: edge-triggered: active edge of the clock impacts the state master-slave: with two gated latches 39

40 References and Further Reading [V2011] Frank Vahid, igital esign with RTL esign, VHL, and Verilog, 2nd edition, Wiley, [BV2009] Stephen Brown and Zvonko Vranesic, Fundamentals of igital Logic with VHL esign, 3rd edition, McGraw-Hill, [S2017] John Seiffertt, igital Logic for Computing, 1st edition, Springer,

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