Syed Muhammad Yasser Sherazi CURRICULUM VITAE

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1 Syed Muhammad Yasser Sherazi Date of Birth: 16th July 1982 Adress: Rydvagen 104A, Linköping, Sweden Cell: E-post: Objective CURRICULUM VITAE To obtain a position that will utilize my education, experience, interpersonal & Leadership skills, as well as provide career opportunities for the growth and advancement in the organization and my life. To pursue a long term carrier with a reputable organization by meeting challenging tasks and carrier oriented growth opportunities Education : Master's of Engineering in System on Chip (SOC) from University of Linköping (LIU), Sweden. Title of Master Thesis: Reduction of Simultaneous Switching Noise in Analog Signal Band on a 130nm Chip : Bachelor of Computer Engineering from COMSATS Institute of Technology, Islamabad, Pakistan. Title of Final Thesis: Development of an FPGA Based Fault Monitoring and Alarm Processing Unit for Nuclear Channels, A system for PINSTECH (Pakistan Institute of Nuclear Science and Technology). Work Experience 2006: Lecturer at COMSATS Institute of Information Technology, Islamabad, Pakistan. Responsibilities: Delivered lectures to the bachelors of engineering students, for Basic Electronics, Digital Electronics, Networking, Computer Architecture : Research Associate COMSATS Institute of Information Technology, Islamabad, Pakistan. Responsibilities: Worked on a project of re-engineering of an optical encoder machine for NDC (National Defense College). I instructed labs for the students of electrical engineering at bachelor s level. The assigned lab were for Digital Design Logic, Computer Networks, Computer Architecture, Advance Digital Design 2003: Internship Engineer at Civil Aviation Authorities (CAA), Islamabad. Responsibilities: Working under a supervisor and test the electronic equipments. Language Skill Urdu: English: Mother Tongue Fluent

2 Areas of Expertise VLSI Design Mixed Signal Processing Digital Integrated Circuits Analog and Discrete Time System Design Advance Computer Architecture Asynchronous Circuits Cadence Integrated Designing Design for Test for Digital Circuits Tools and Applications Operating Systems: Microsoft Windows (XP, Vista), Apple Mac OS ( Leopard), Unix, Linux, SUN Solaris Engineering Software Packages: Cadence Integrated Designing, Xilinx, ORCAD, Matlab, Leonardo Spectrum, DFTAdvisor, FlexTest, Trainer1149, ATACS, Simulink, C/C++, Verilog, and VHDL. General Skills Strong Presentation and Documentation skills Strong visualization and artistic temperaments Strong skills for Researching, Logics and Reasoning Projects 06/ /2008: Master Thesis: Reduction of Simultaneous Switching Noise in Analog Signal Band on a Chip. The idea is to reduce Simultaneous Switching Noise (SSN) by half of the clock frequency in the frequency band. This frequency band often corresponds to the analog signal band of a digital-toanalog converter. To evaluate the method two pipelined adders have been implemented on layout level in a 0.13 μm CMOS technology. Where the DCVSL circuit is implemented with our method and will be called the test circuit and the reference circuit with static CMOS logic. The design has been implemented in 0.13 μm technology. It has both the test circuits and the reference circits along with Test circuitry that enables us to perfrom random test on the circuits. For the test perpose PRBS hand ROM with control logic have been designed. The Chip has 40 Pin in it and the total area is of 1mm 2. MATLAB ModelSim Cadence Integrated Design 06/ /2008: Modelling and Implementation of a Physical Layer in FPGA. The goal of the project was to design and implement IEEE a WLAN standard in FPGA. The of the project was to develop skills in solving complex design problems using a well structured design process that assures that the design goal is reached as well as provide advanced knowledge in both the electronics and application domain.

3 This was a course project that covered all essential steps in the design and implementation of a multi-carrier based communication system. Basic theory for the multicarrier system and current standards for radio LAN was studied. A top-down design-flow was used, starting from the system specification, partitioning, algorithms, mapping to a software/hardware resource structure, and ending with a working implementation in FPGA (Field-Programmable Gate Array). The design process was centered on building a sequence of models with increasing level of detail. The modeling, realization, verification of functionality, and implementation of the communication system was based on using high-level tools such as Simulink. Simulink MATLAB 01/ /2007: VLSI designing and Implementation of Delay Lock Loop with Clock Multiplier in 0.35 μm technology It was a project to design and fabrication of Very Large Scale Integrated (VLSI) circuits in submicron CMOS technology, to acquired considerable insight into VLSI design methodology, transistor level design, high-performance and low-power circuit techniques, circuit layout, and chip design. It was an academic course project supports the CDIO project highlights and the LIPS project model to promote teamwork and communication skill required by industry to run large and complex VLSI projects. The complete system consists of Delay Lock Loop and a clock multiplier that worked on the detection of different phases of the clock in the delay line. We also had built analog temperature compensator. Cadence Integrated design 01/ /2007: Designing a Mixed Signal Processing System In this academic project we designed a complete Mixed Signal System containing an integrated analog anti-aliasing filter with corresponding tuning circuitry, and an analog-to-digital converter with possible error correction or self-calibration preceding a digital signal processing block. The processed digital data is often then reconstructed into an analog signal by a digital-to-analog converter followed by an analog anti-imaging filter. It was an industrial oriented project to develop skills of problem analysis and structuring, writing project and time plans, working in a group, creativity, oral and written presentation techniques, modelling, design, and evaluation of mixed-signal systems, design methodology, and writing requirement and design specifications. The outcome of the project work is an executable simulation model of an advanced mixed-signal processing system. This project deals with hybrid systems that employ both analog and digital signals. These systems are very complicated to design and model at the signal level as well as at the electrical level. Matlab AHDL Cadence Integrated design

4 08/ /2006: Designing Digital Audio Processor on FPGA The project includes methods and tools for design and implementation of complex electronic systems, it emphasis the design process. VHDL is used to describe the digital system. Models using increasing levels of details has been built and mixed as well as test benches used to validate every new model. Programmable circuits such as FPGAs are increasingly used to replace ASICs as well as for verification of a design in advance of an ASIC manufacturing. The focus of this Project is to design a system called Digital Audio Processor that capable of interfacing with the VGA monitor an keyboard without using computer. The system receives analog signals, makes signal conversions and displays the digital signal on its own VGA monitor using the features of XStend Board produced by the XESS Corporation. The system makes balance and volume control using the keyboard, and it displays the amplitude of the signals on the VGA monitor according. FPGA Advantage VHDL 02/ /2005: Reengineering of an optical encoder machine The project was a reengineering of an optical encoder machine for NDC (National Defense College). It was a project given to our University CIIT from NDC and I did this project as a research engineer The controller of the machine and its peripheries were developed using Verilog in Xilinx ISE 6 and made a complete system was built around XC2S200E Spartan FPGA. Xilinx ISE 6.1 Verilog Visual Basic 04/ /2004: Development of an FPGA Based Fault monitoring And Alarm Processing Unit for Nuclear Channels It was my bachelors final year project. The project s main focus was on the Development of an FPGA Based Fault monitoring And Alarm Processing Unit for Nuclear Channels, A system for PINSTECH (Pakistan Institute of Nuclear Science and Technology). The code was written in Verilog for XC2S200E Spartan FPGA. A complete panel was made for the monitoring of faults on the PCB with a KEYPAD & LCD Interface. This was then plugged in with the DS2B Prototyping Board to complete the system. Xilinx ISE 6.1 Verilog

5 Awards /Positions Won a scholarship form Higher Education Commision Pakistan for Master Studies in Sweden. Secured over all 3 rd position in the spring 2001 batch and received Bronze Medal from COMSATS Institute of Information Technology. Secured 2 nd position in 6 th and 8 th semesters and received cash prize in 6 th semester of BSc. Secured 2 nd position in Electronics Exhibition held by COMSATS Institute of Information Technology in Extra Curricular Activities Organized a stall representing Pakistan on International Day organized by Linköping University. Remained captain of the university football team for one year. Participated as an Usher in the 1 st convocation COMSATS Institute of Information Technology held in Convention Centre Islamabad. Arranged and managed a Cricket Tournament in COMSATS Institute of Information Technology. References Prof. Mark Vesterbacka. Prof. Kent Palmkvist (markv@isy.liu.se) (kentp@isy.liu.se)