High Speed Link Validation Group Wireless Division.
|
|
|
- Cody Parrish
- 5 years ago
- Views:
Transcription
1 Curriculum Vitae Personal Information Name: Address: Telephone(s): Skype ID: Objective Rahul Bhattacharya Quarter No - 57, Block-4 Eminent Academics Apartment New Type Quarter, Type-IV n Institute of Technology(ISM), Dhanbad PIN State-Jharkhand, (Mobile) rahulece83@gmail.com rahul.bhattacharya6 Intend to build a career, committed and dedicated to state-of-the-art research in a hi-tech environment which helps me to explore myself fully and realize my potential. Academic Experience Organization: Duration: Assistant Professor Department of Electronics Engineering, n Institute of Technology (ISM) Dhanbad, Jharkhand,. June 2013 to till date Professional Experience Senior Design Engineer High Speed Link Validation Group Wireless Division. Work location: ST-Ericsson Pvt. Ltd, Bangalore, Duration: November, May, 2013 Project Title: Establishment of CAD based Verification Platform for LLI (Low Latency Interface) Interoperability based on MIPI Standard M-PHY Technology Integration of LLI IP with ARM Cortex-R4 based integrated sub-system which contains ARM Cortex- R4 model (from ARM) integrated with different ARM IPs e.g. Interrupt controller, GPIO, Timer, UART, Interconnect bus matrix, Debug Access Port, TCM(using FPGA Block RAM) etc. Test bench creation to emulate different test scenarios targeting LLI IOT, to generate different clock frequencies required for ARM IPs, bus matrices. Functional verification of different IPs of ARM subsystem executing read/write test cases at their periphery. Bringing up CAD environment integrating two M-PHY test chip models back to back. Execution of various MIPI compliant LLI test cases to set up a communication between two test chips for IOT purpose. Generation of test coverage matrix. Project Engineer Semiconductor and Consumer Electronics Division. Work location: Wipro Technologies, Electronic City, Phase-I, Bangalore
2 Duration: August, August, 2006 Project Title: DFT (Design for Testability) Methodologies for ARM-based Microcontroller Insertion of DFT logic in a netlist for ARM based Microcontrollers. Generation of test patterns using Synopsys-Tetramax for different DFT methodologies following some of standard DFT guide lines to get target test coverage. Writing procedure for Scan chain insertion. Pattern simulation using Mentor Graphics-Modelsim without and with sdf (Standard Delay Format) and debugging to resolve miscompares. Academic Projects Location: Research Consultant Advanced VLSI Design Laboratory, n Institute of Technology Kharagpur,. Duration: January, October, 2010 Projects Title: Concurrent Virtual Test Platform Development sponsored by National Semiconductor Corporation, USA Activity: Emulation of Behavioral Models of Analog and Mixed Signal Circuits on FPGA Proposed a technique to emulate an AMS integrated circuit on high-end FPGA based on DSP algorithm. Emulation of 100 khz linear Analog PLL and 200 khz Current Programmed DC-DC Buck Converter. System level modeling (floating-point and fixed-point bit-true) of linear analog PLL and 200 khz current program controlled DC-DC buck converter using Xilinx-System Generator in MATLAB- Simulink platform. Generation of RTL netlist and modeling wrapper for interfacing with test I/O, DFT logic etc. Activity: Optimization of word-length to minimize hardware resources for MATLAB based DSP Implementation on FPGA Proposed an algorithm to optimize the word-length for MATLAB based DSP implementation on FPGA constraint to a given performance metric. Validated on fixed-point bit-true of linear PLL, current programmed DC-DC buck converter and benchmark analog filters to implement on FPGA. Analysis of complexity of word-length optimization algorithm. Activity: Selection of appropriate frequency to avoid timing violation for MATLAB-based DSP Implementation on FPGA Proposed an algorithm to select appropriate sampling frequency to achieve best performance without timing violation for a MATLAB based FPGA design constraint to given performance metric. Validated on fixed-point bit-true model of linear PLL, current programmed DC-DC buck converter. Project Title: A New approach for testing of digital modules in mixed signal VLSI Circuits Developed a new approach for testing of digital modules embedded in mixed signal VLSI circuits exploiting analog back trace. Minimized the DFT overheads in traditional test practices. Validated on a mixed-signal system consisting of a BPF (band pass filter) as an analog block and ISCAS S349 as digital block. Project Title: Assembly Language Programming (ALP) of a PIC 16F877 Micro controller to Generate Patterns and Detect Faults in a JTAG compliant board. Writing ALP for PIC 16F877 Micro controller for Boundary Scan Testing. To control the standard test access registers. To send/capture the patterns through JTAG pins. To detect faults in the board.
3 Teaching Experience Teaching (IIT-ISM Dhanbad) Theory Subjects Laboratory Semester Electronics Engineering Electronics Engineering 1 st Yr. B.Tech (Common) Lab Electronics Devices Lab 2 nd Yr. B.Tech(ECE) Power Electronics Power Electronics Lab 3 rd Yr. B.Tech(ECE) and 3 rd Yr. B.Tech(EIE) VLSI Design Lab 3 rd Yr. B.Tech(ECE) Microelectronics and 3 rd Yr. B.Tech(ECE) VLSI VLSI Circuits 1 st Yr. M.Tech(ECE) Testing(Elective) Microelectronics and VLSI Lab 1 st Yr. M.Tech(ECE) Research Experience Name of Sponsoring Organization IIT (ISM) Dhanbad (under Faculty Research Scheme) IIT (ISM) Dhanbad (under the aegis of TEQIP-II) Summary of Sponsored Project Title of Project Project No. Period Amount (in Lakhs) Test development of analog and mixed signal circuits by emulation and implementation of their behavioral models on FPGA Feasibility study on fault emulation of linear analog circuits on a programmable hardware FRS(83)/ /ECE 3 years (from Feb,2015) 6 months (from Nov, 2016) Education and Training Academic Records MS (Master of Science by Research) Department: Electrical Engineering, IIT Kharagpur Specialization: VLSI Design and Test Duration: January, 2007 October, 2010 University: n Institute of Technology Kharagpur, Thesis Title: CGPA: 8.92 Design of a Chip Emulation System for Test Development of Analog and Mixed Signal Circuits BE(Bachelor of Engineering) Department: Electronics and Communication Engineering, NIT Durgapur Duration: August, 2001 July, 2005 University: National Institute of Technology Durgapur,
4 CGPA: 8.55 (78%) Higher Secondary School Level Examination Specialization: Science, Mathematics Board: West Bengal Board of Higher Secondary Education Duration: July, 1999 June, 2001 Institute: Ramakrishna Mission Residential College, Narendrapur, West Bengal, Marks: 84.1% Secondary School Level Examination Specialization: Science, Mathematics, English, Bengali, History, Geography Board: West Bengal Board of Secondary Education Year of Passing: June, 1999 Institute: Ramakrishna Mission Vidyalaya, Narendrapur, West Bengal, Marks: 87.75% Training Sponsor Organization: ST-Ericsson Pvt. Ltd. Training Organization: ARM Ltd. Purpose: Cortex-A15 Software and M4 Overview Duration: September 27 th, 2011 September 30 th, 2011 Sponsor Organization: IIT Kharagpur, Training Organization: Tessolve Services Pvt. Ltd, Bangalore Purpose: Training on A575 ATE Program Duration: November 16 th, 2006 November 24 th, 2006 Sponsor Organization: NIT Durgapur, Training Organization: Variable Energy Cyclotron Centre, Kolkata Purpose: Summer Training on Instrument Communication and Control through GPIB Interface Duration: May, 2004 June, 2004 Personal Skills and Competences Languages Known English (Understanding, Speaking, Writing) Hindi (Understanding, Speaking, Writing) Bengali (Mother Tongue) Technical Skills and Competences EDA Tools: HDL Language: Programming/Scripting Skill: Configuration Tool: NC-Sim, Xilinx ISE, Synplify Pro, Xilinx-System Generator (in MATLAB-Simulink), Cadence- Verilog XL, OrCAD Capture CIS (SPICE Modeling), ModelSim. Verilog, Verilog A C (with Data Structure), MATLAB, TCL scripting Clear Case (IBM Certified) Computer Skills and Competences Operating Systems: Windows, Solaris. Other Skills and Competences Playing Soccer, Cycling, Internet Surfing, Fond of Music.
5 Special Awards/Honours Received Awarded prizes and certificate of merit for 5th position in All Science Talent Examination. Participated in QUIZ-CONTESTS at School level. Awarded certificate on Paper Presentation in AAROHAN-2K4 National Level Tech Fest held in NIT Durgapur. Awarded Peer to Peer Recognition in ST-Ericsson Pvt. Ltd. for successful establishment of simulation based verification set up for LLI IOT. Reviewer of books by Cambridge University Press for undergraduate Electronics Engineering students. Reviewer of ICICA 2014 International Conference organized by NIT Durgapur. Membership of Professional Bodies 1. Member of IEEE (Membership No ). 2. Member of VSI (VLSI Society of ). 3. Member of ACM (Association for Computing Machinery). Publications Conferences M. Rajneesh, R. Bhattacharya, S. Biswas, S. Mukhopadhyay ''A NEW APPROACH FOR TESTING OF DIGITAL MODULES IN MIXED SIGNAL VLSI CIRCUITS'', IEEE VLSI Design and Test, 2007, Page(s): M. Rajneesh, R. Bhattacharya, S. Biswas, S. Mukhopadhyay ''A NEW APPROACH FOR TESTING OF DIGITAL MODULES IN MIXED SIGNAL VLSI CIRCUITS'' IEEE Advanced Computing and Communications, ADCOM 2007,Page(s): R. Bhattacharya, S. Biswas, S. Mukhopadhyay FPGA based Chip Emulation System for Test Development of Analog and Mixed Signal Circuits, 18th annual ACM/SIGDA international symposium on Field programmable gate arrays, 2010, Page: 284. R. Bhattacharya, S. Kumar, A New Approach for Modeling Parametric Faults in Linear Analog VLSI Circuits, 6 th IEEE international conference on Computers and Devices for Communication (CODEC), December 16-18, 2015, DOI: /CODEC Anjali Rai, Rahul Bhattacharya, Parametric Fault Detection for Instrumentation Amplifier Circuit, 2 nd IEEE International Conference on Recent Advances and Innovations in Engineering (ICRAIE-2016), December 23-25, 2016, Jaipur,. Journals (International) R. Bhattacharya, S. Biswas, S. Mukhopadhyay FPGA based chip emulation system for test development of analog and mixed signal circuits: A case study of Buck converter, Journal of the International Measurement Confederation, Elsevier, vol. 45, issue. 8, pp , Rahul Bhattacharya, Subindu Kumar and Santosh Biswas Resource Optimization for Emulation of Behavioral Models of Mixed Signal Circuits on FPGA: A case study of DC-DC buck converter, International Journal of Circuit Theory and Applications, Wiley, Version of Record online: 1 st FEB DOI: /cta.2323 Declaration: I hereby certify that the information furnished above is factually correct & true to the best of my knowledge.
6 References Dr Siddhartha Mukhopadhyay Professor Department of Electrical Engineering IIT Kharagpur Kharagpur Phone: (O), (M) Dr Santosh Biswas Associate Professor Department of Computer Science and Engineering IIT Guwahati Guwahati Phone: (O), (M)
Using on-chip Test Pattern Compression for Full Scan SoC Designs
Using on-chip Test Pattern Compression for Full Scan SoC Designs Helmut Lang Senior Staff Engineer Jens Pfeiffer CAD Engineer Jeff Maguire Principal Staff Engineer Motorola SPS, System-on-a-Chip Design
FPGA Development for Radar, Radio-Astronomy and Communications
John-Philip Taylor Room 7.03, Department of Electrical Engineering, Menzies Building, University of Cape Town Cape Town, South Africa 7701 Tel: +27 82 354 6741 email: tyljoh010@myuct.ac.za Internet: http://www.uct.ac.za
Syed Muhammad Yasser Sherazi CURRICULUM VITAE
Syed Muhammad Yasser Sherazi Date of Birth: 16th July 1982 Adress: Rydvagen 104A, 58431 Linköping, Sweden Cell: 0046762323697 E-post: smy_sherazi@yahoo.com Objective CURRICULUM VITAE To obtain a position
Powerful Software Tools and Methods to Accelerate Test Program Development A Test Systems Strategies, Inc. (TSSI) White Paper.
Powerful Software Tools and Methods to Accelerate Test Program Development A Test Systems Strategies, Inc. (TSSI) White Paper Abstract Test costs have now risen to as much as 50 percent of the total manufacturing
EEM Digital Systems II
ANADOLU UNIVERSITY DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING EEM 334 - Digital Systems II LAB 3 FPGA HARDWARE IMPLEMENTATION Purpose In the first experiment, four bit adder design was prepared
TKK S ASIC-PIIRIEN SUUNNITTELU
Design TKK S-88.134 ASIC-PIIRIEN SUUNNITTELU Design Flow 3.2.2005 RTL Design 10.2.2005 Implementation 7.4.2005 Contents 1. Terminology 2. RTL to Parts flow 3. Logic synthesis 4. Static Timing Analysis
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14)
Lecture 23 Design for Testability (DFT): Full-Scan (chapter14) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads Scan design system Summary
RAPID SOC PROOF-OF-CONCEPT FOR ZERO COST JEFF MILLER, PRODUCT MARKETING AND STRATEGY, MENTOR GRAPHICS PHIL BURR, SENIOR PRODUCT MANAGER, ARM
RAPID SOC PROOF-OF-CONCEPT FOR ZERO COST JEFF MILLER, PRODUCT MARKETING AND STRATEGY, MENTOR GRAPHICS PHIL BURR, SENIOR PRODUCT MANAGER, ARM A M S D E S I G N & V E R I F I C A T I O N W H I T E P A P
Lecture 23 Design for Testability (DFT): Full-Scan
Lecture 23 Design for Testability (DFT): Full-Scan (Lecture 19alt in the Alternative Sequence) Definition Ad-hoc methods Scan design Design rules Scan register Scan flip-flops Scan test sequences Overheads
Tutorial 11 ChipscopePro, ISE 10.1 and Xilinx Simulator on the Digilent Spartan-3E board
Tutorial 11 ChipscopePro, ISE 10.1 and Xilinx Simulator on the Digilent Spartan-3E board Introduction This lab will be an introduction on how to use ChipScope for the verification of the designs done on
L12: Reconfigurable Logic Architectures
L12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following sources and are used with permission. Frank Honore Prof. Randy Katz (Unified Microelectronics
Adding Analog and Mixed Signal Concerns to a Digital VLSI Course
Session Number 1532 Adding Analog and Mixed Signal Concerns to a Digital VLSI Course John A. Nestor and David A. Rich Department of Electrical and Computer Engineering Lafayette College Abstract This paper
Scan. This is a sample of the first 15 pages of the Scan chapter.
Scan This is a sample of the first 15 pages of the Scan chapter. Note: The book is NOT Pinted in color. Objectives: This section provides: An overview of Scan An introduction to Test Sequences and Test
Achieving Timing Closure in ALTERA FPGAs
Achieving Timing Closure in ALTERA FPGAs Course Description This course provides all necessary theoretical and practical know-how to write system timing constraints for variety designs in ALTERA FPGAs.
VHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress
VHDL Design and Implementation of FPGA Based Logic Analyzer: Work in Progress Nor Zaidi Haron Ayer Keroh +606-5552086 zaidi@utem.edu.my Masrullizam Mat Ibrahim Ayer Keroh +606-5552081 masrullizam@utem.edu.my
Design and Implementation of SOC VGA Controller Using Spartan-3E FPGA
Design and Implementation of SOC VGA Controller Using Spartan-3E FPGA 1 ARJUNA RAO UDATHA, 2 B.SUDHAKARA RAO, 3 SUDHAKAR.B. 1 Dept of ECE, PG Scholar, 2 Dept of ECE, Associate Professor, 3 Electronics,
Design for Testability
TDTS 01 Lecture 9 Design for Testability Zebo Peng Embedded Systems Laboratory IDA, Linköping University Lecture 9 The test problems Fault modeling Design for testability techniques Zebo Peng, IDA, LiTH
Testing of Cryptographic Hardware
Testing of Cryptographic Hardware Presented by: Debdeep Mukhopadhyay Dept of Computer Science and Engineering, Indian Institute of Technology Madras Motivation Behind the Work VLSI of Cryptosystems have
LAB NAME: ELECTRONICS LABORATORY. Ammeters (0-1mA, 0-10mA, 0-15mA, 0-30mA, 0-50mA, 0-100mA,0-50µA,0-
LAB NAME: ELECTRONICS LABORATORY 1 Ammeters (0-1mA, 0-10mA, 0-15mA, 0-30mA, 0-50mA, 0-100mA,0-50µA,0-100µA,0-500µA) 2 Cathode Ray Oscilloscope (20MHZ, 30MHZ,) 3 Decade Inductance Box 4 Decade Resistance
FPGA Laboratory Assignment 4. Due Date: 06/11/2012
FPGA Laboratory Assignment 4 Due Date: 06/11/2012 Aim The purpose of this lab is to help you understanding the fundamentals of designing and testing memory-based processing systems. In this lab, you will
Design and analysis of microcontroller system using AMBA- Lite bus
Design and analysis of microcontroller system using AMBA- Lite bus Wang Hang Suan 1,*, and Asral Bahari Jambek 1 1 School of Microelectronic Engineering, Universiti Malaysia Perlis, Perlis, Malaysia Abstract.
Saving time & money with JTAG
Saving time & money with JTAG AltiumLive 2017: ANNUAL PCB DESIGN SUMMIT Simon Payne CEO, XJTAG Ltd. Saving time and money with JTAG JTAG / IEEE 1149.X Take-away points Get JTAG right from the start Use
VLSI Test Technology and Reliability (ET4076)
VLSI Test Technology and Reliability (ET476) Lecture 9 (2) Built-In-Self Test (Chapter 5) Said Hamdioui Computer Engineering Lab Delft University of Technology 29-2 Learning aims Describe the concept and
L11/12: Reconfigurable Logic Architectures
L11/12: Reconfigurable Logic Architectures Acknowledgements: Materials in this lecture are courtesy of the following people and used with permission. - Randy H. Katz (University of California, Berkeley,
International Journal of Scientific & Engineering Research, Volume 5, Issue 9, September ISSN
International Journal of Scientific & Engineering Research, Volume 5, Issue 9, September-2014 917 The Power Optimization of Linear Feedback Shift Register Using Fault Coverage Circuits K.YARRAYYA1, K CHITAMBARA
Equivalence Checking using Assertion based Technique
Equivalence Checking using Assertion based Technique Shailesh Kumar NIT Bhopal Sameer Arvikar DAVV Indore Saurabh Jha STMicroelectronics, Greater Noida Tarun K. Gupta, PhD Asst. Professor NIT Bhopal ABSTRACT
A Briefing on IEEE Standard Test Access Port And Boundary-Scan Architecture ( AKA JTAG )
A Briefing on IEEE 1149.1 1990 Standard Test Access Port And Boundary-Scan Architecture ( AKA JTAG ) Summary With the advent of large Ball Grid Array (BGA) and fine pitch SMD semiconductor devices the
DC Ultra. Concurrent Timing, Area, Power and Test Optimization. Overview
DATASHEET DC Ultra Concurrent Timing, Area, Power and Test Optimization DC Ultra RTL synthesis solution enables users to meet today s design challenges with concurrent optimization of timing, area, power
Sharif University of Technology. SoC: Introduction
SoC Design Lecture 1: Introduction Shaahin Hessabi Department of Computer Engineering System-on-Chip System: a set of related parts that act as a whole to achieve a given goal. A system is a set of interacting
Simulation Mismatches Can Foul Up Test-Pattern Verification
1 of 5 12/17/2009 2:59 PM Technologies Design Hotspots Resources Shows Magazine ebooks & Whitepapers Jobs More... Click to view this week's ad screen [ D e s i g n V i e w / D e s i g n S o lu ti o n ]
RAJASTHAN TECHNICAL UNIVERSITY, KOTA
2 nd Year: Electronics & Communication Engineering III Semester No. Course Code Category Course Title Hours Marks Credits 1 3EC2-01 BSC Advanced Engineering Mathematics-I 2 3EC1-02/ 3EC1-03 HSMC Technical
OF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS
IMPLEMENTATION OF AN ADVANCED LUT METHODOLOGY BASED FIR FILTER DESIGN PROCESS 1 G. Sowmya Bala 2 A. Rama Krishna 1 PG student, Dept. of ECM. K.L.University, Vaddeswaram, A.P, India, 2 Assistant Professor,
Certus TM Silicon Debug: Don t Prototype Without It by Doug Amos, Mentor Graphics
Certus TM Silicon Debug: Don t Prototype Without It by Doug Amos, Mentor Graphics FPGA PROTOTYPE RUNNING NOW WHAT? Well done team; we ve managed to get 100 s of millions of gates of FPGA-hostile RTL running
A First Laboratory Course on Digital Signal Processing
A First Laboratory Course on Digital Signal Processing Hsien-Tsai Wu and Hong-De Chang Department of Electronic Engineering Southern Taiwan University of Technology No.1 Nan-Tai Street, Yung Kang City,
Using an IEEE Test Bus for Fault Diagnosis of Analog Parts of Electronic Embedded Systems. Zbigniew Czaja 1, Bogdan Bartosinski 2
Using an IEEE1149.1 Test Bus for Fault Diagnosis of Analog Parts of Electronic Embedded Systems Zbigniew Czaja 1, Bogdan Bartosinski 2 1 Gdansk University of Technology, Faculty of Electronics, Telecommunications
Overview: Logic BIST
VLSI Design Verification and Testing Built-In Self-Test (BIST) - 2 Mohammad Tehranipoor Electrical and Computer Engineering University of Connecticut 23 April 2007 1 Overview: Logic BIST Motivation Built-in
EXOSTIV TM. Frédéric Leens, CEO
EXOSTIV TM Frédéric Leens, CEO A simple case: a video processing platform Headers & controls per frame : 1.024 bits 2.048 pixels 1.024 lines Pixels per frame: 2 21 Pixel encoding : 36 bit Frame rate: 24
18 Nov 2015 Testing and Programming PCBA s. 1 JTAG Technologies
8 Nov 25 Testing and Programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge costs
Authentic Time Hardware Co-simulation of Edge Discovery for Video Processing System
Authentic Time Hardware Co-simulation of Edge Discovery for Video Processing System R. NARESH M. Tech Scholar, Dept. of ECE R. SHIVAJI Assistant Professor, Dept. of ECE PRAKASH J. PATIL Head of Dept.ECE,
for Digital IC's Design-for-Test and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ
Design-for-Test for Digital IC's and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ 07458 www.phptr.com ISBN D-13-DflMfla7-l : Ml H Contents Preface Acknowledgments Introduction
OpenXLR8: How to Load Custom FPGA Blocks
OpenXLR8: How to Load Custom FPGA Blocks Webinar Breakdown: Introduc*on to pseudorandom number generator (LFSR) code Review of Verilog wrapper interface to microcontroller Simula*on with Mentor Graphics
BSDL Validation: A Case Study
ASSET InterTech, Inc. Validation: A Case Study Michael R. Johnson Sr. Applications Engineer ASSET InterTech, Inc. Agilent Boundary Scan User Group Meeting December 15, 2008 About The Presenter Michael
Testability: Lecture 23 Design for Testability (DFT) Slide 1 of 43
Testability: Lecture 23 Design for Testability (DFT) Shaahin hi Hessabi Department of Computer Engineering Sharif University of Technology Adapted, with modifications, from lecture notes prepared p by
Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6. - Introductory Digital Systems Laboratory (Spring 006) Laboratory - Introduction to Digital Electronics
Page 1 of 6 Follow these guidelines to design testable ASICs, boards, and systems. (includes related article on automatic testpattern generation basics) (Tutorial) From: EDN Date: August 19, 1993 Author:
Radar Signal Processing Final Report Spring Semester 2017
Radar Signal Processing Final Report Spring Semester 2017 Full report report by Brian Larson Other team members, Grad Students: Mohit Kumar, Shashank Joshil Department of Electrical and Computer Engineering
16 Dec Testing and Programming PCBA s. 1 JTAG Technologies
6 Dec 24 Testing and Programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge costs
AC : DIGITAL DESIGN MEETS DSP
AC 2011-754: DIGITAL DESIGN MEETS DSP Christopher S Greene, University of Saint Thomas Christopher Greene received his Ph.D. in Electrical Engineering from the Massachusetts Institute of Technology (MIT)
Design of Low Power Efficient Viterbi Decoder
International Journal of Research Studies in Electrical and Electronics Engineering (IJRSEEE) Volume 2, Issue 2, 2016, PP 1-7 ISSN 2454-9436 (Online) DOI: http://dx.doi.org/10.20431/2454-9436.0202001 www.arcjournals.org
VLSI System Testing. BIST Motivation
ECE 538 VLSI System Testing Krish Chakrabarty Built-In Self-Test (BIST): ECE 538 Krish Chakrabarty BIST Motivation Useful for field test and diagnosis (less expensive than a local automatic test equipment)
Available online at ScienceDirect. Procedia Computer Science 46 (2015 ) Aida S Tharakan a *, Binu K Mathew b
Available online at www.sciencedirect.com ScienceDirect Procedia Computer Science 46 (2015 ) 1409 1416 International Conference on Information and Communication Technologies (ICICT 2014) Design and Implementation
Modeling and Implementing Software-Defined Radio Communication Systems on FPGAs Puneet Kumar Senior Team Lead - SPC
Modeling and Implementing Software-Defined Radio Communication Systems on FPGAs Puneet Kumar Senior Team Lead - SPC 2012 The MathWorks, Inc. 1 Agenda Integrated Model-Based Design to Implement SDR on FPGA
Introduction to The Design of Mixed-Signal Systems on Chip 1
Introduction to The Design of Mixed-Signal Systems on Chip 1 Ken Kundert Cadence Design Systems Design of Mixed-Signal Systems on Chip 35 th Design Automation Conference, 1998 Henry Chang Felicia James
Tools to Debug Dead Boards
Tools to Debug Dead Boards Hardware Prototype Bring-up Ryan Jones Senior Application Engineer Corelis 1 Boundary-Scan Without Boundaries click to start the show Webinar Outline What is a Dead Board? Prototype
7 Nov 2017 Testing and programming PCBA s
7 Nov 207 Testing and programming PCBA s Rob Staals JTAG Technologies Email: robstaals@jtag.com JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before
Chapter 8 Design for Testability
電機系 Chapter 8 Design for Testability 測試導向設計技術 2 Outline Introduction Ad-Hoc Approaches Full Scan Partial Scan 3 Design For Testability Definition Design For Testability (DFT) refers to those design techniques
nmos transistor Basics of VLSI Design and Test Solution: CMOS pmos transistor CMOS Inverter First-Order DC Analysis CMOS Inverter: Transient Response
nmos transistor asics of VLSI Design and Test If the gate is high, the switch is on If the gate is low, the switch is off Mohammad Tehranipoor Drain ECE495/695: Introduction to Hardware Security & Trust
Ilmenau, 9 Dec 2016 Testing and programming PCBA s. 1 JTAG Technologies
Ilmenau, 9 Dec 206 Testing and programming PCBA s JTAG Technologies The importance of Testing Don t ship bad products to your customers, find problems before they do. DOA s (Death On Arrival) lead to huge
LUT Optimization for Memory Based Computation using Modified OMS Technique
LUT Optimization for Memory Based Computation using Modified OMS Technique Indrajit Shankar Acharya & Ruhan Bevi Dept. of ECE, SRM University, Chennai, India E-mail : indrajitac123@gmail.com, ruhanmady@yahoo.co.in
Hardware Modeling of Binary Coded Decimal Adder in Field Programmable Gate Array
American Journal of Applied Sciences 10 (5): 466-477, 2013 ISSN: 1546-9239 2013 M.I. Ibrahimy et al., This open access article is distributed under a Creative Commons Attribution (CC-BY) 3.0 license doi:10.3844/ajassp.2013.466.477
Verification Methodology for a Complex System-on-a-Chip
UDC 621.3.049.771.14.001.63 Verification Methodology for a Complex System-on-a-Chip VAkihiro Higashi VKazuhide Tamaki VTakayuki Sasaki (Manuscript received December 1, 1999) Semiconductor technology has
LFSRs as Functional Blocks in Wireless Applications Author: Stephen Lim and Andy Miller
XAPP22 (v.) January, 2 R Application Note: Virtex Series, Virtex-II Series and Spartan-II family LFSRs as Functional Blocks in Wireless Applications Author: Stephen Lim and Andy Miller Summary Linear Feedback
Analysis of Low Power Test Pattern Generator by Using Low Power Linear Feedback Shift Register (LP-LFSR)
Analysis of Low Power Test Pattern Generator by Using Low Power Linear Feedback Shift Register (LP-LFSR) Nelli Shireesha 1, Katakam Divya 2 1 MTech Student, Dept of ECE, SR Engineering College, Warangal,
LogiCORE IP Video Timing Controller v3.0
LogiCORE IP Video Timing Controller v3.0 Product Guide Table of Contents Chapter 1: Overview Standards Compliance....................................................... 6 Feature Summary............................................................
T1 Deframer. LogiCORE Facts. Features. Applications. General Description. Core Specifics
November 10, 2000 Xilinx Inc. 2100 Logic Drive San Jose, CA 95124 Phone: +1 408-559-7778 Fax: +1 408-559-7114 E-mail: support@xilinx.com URL: www.xilinx.com/ipcenter Features Supports T1-D4 and T1-ESF
Design and Implementation of Partial Reconfigurable Fir Filter Using Distributed Arithmetic Architecture
Design and Implementation of Partial Reconfigurable Fir Filter Using Distributed Arithmetic Architecture Vinaykumar Bagali 1, Deepika S Karishankari 2 1 Asst Prof, Electrical and Electronics Dept, BLDEA
Design and Implementation of an AHB VGA Peripheral
Design and Implementation of an AHB VGA Peripheral 1 Module Overview Learn about VGA interface; Design and implement an AHB VGA peripheral; Program the peripheral using assembly; Lab Demonstration. System
An Efficient High Speed Wallace Tree Multiplier
Chepuri satish,panem charan Arur,G.Kishore Kumar and G.Mamatha 38 An Efficient High Speed Wallace Tree Multiplier Chepuri satish, Panem charan Arur, G.Kishore Kumar and G.Mamatha Abstract: The Wallace
4. Formal Equivalence Checking
4. Formal Equivalence Checking 1 4. Formal Equivalence Checking Jacob Abraham Department of Electrical and Computer Engineering The University of Texas at Austin Verification of Digital Systems Spring
AbhijeetKhandale. H R Bhagyalakshmi
Sobel Edge Detection Using FPGA AbhijeetKhandale M.Tech Student Dept. of ECE BMS College of Engineering, Bangalore INDIA abhijeet.khandale@gmail.com H R Bhagyalakshmi Associate professor Dept. of ECE BMS
Using SignalTap II in the Quartus II Software
White Paper Using SignalTap II in the Quartus II Software Introduction The SignalTap II embedded logic analyzer, available exclusively in the Altera Quartus II software version 2.1, helps reduce verification
From Theory to Practice: Private Circuit and Its Ambush
Indian Institute of Technology Kharagpur Telecom ParisTech From Theory to Practice: Private Circuit and Its Ambush Debapriya Basu Roy, Shivam Bhasin, Sylvain Guilley, Jean-Luc Danger and Debdeep Mukhopadhyay
Enhancing Performance in Multiple Execution Unit Architecture using Tomasulo Algorithm
Available Online at www.ijcsmc.com International Journal of Computer Science and Mobile Computing A Monthly Journal of Computer Science and Information Technology ISSN 2320 088X IMPACT FACTOR: 6.017 IJCSMC,
TEST PATTERN GENERATION USING PSEUDORANDOM BIST
TEST PATTERN GENERATION USING PSEUDORANDOM BIST GaneshBabu.J 1, Radhika.P 2 PG Student [VLSI], Dept. of ECE, SRM University, Chennai, Tamilnadu, India 1 Assistant Professor [O.G], Dept. of ECE, SRM University,
Figure 1: Feature Vector Sequence Generator block diagram.
1 Introduction Figure 1: Feature Vector Sequence Generator block diagram. We propose designing a simple isolated word speech recognition system in Verilog. Our design is naturally divided into two modules.
Individual Project Report
EN 3542: Digital Systems Design Individual Project Report Pseudo Random Number Generator using Linear Feedback shift registers Index No: Name: 110445D I.W.A.S.U. Premaratne 1. Problem: Random numbers are
Static Timing Analysis for Nanometer Designs
J. Bhasker Rakesh Chadha Static Timing Analysis for Nanometer Designs A Practical Approach 4y Spri ringer Contents Preface xv CHAPTER 1: Introduction / 1.1 Nanometer Designs 1 1.2 What is Static Timing
Why FPGAs? FPGA Overview. Why FPGAs?
Transistor-level Logic Circuits Positive Level-sensitive EECS150 - Digital Design Lecture 3 - Field Programmable Gate Arrays (FPGAs) January 28, 2003 John Wawrzynek Transistor Level clk clk clk Positive
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm Mustafa Parlak and Ilker Hamzaoglu Faculty of Engineering and Natural Sciences Sabanci University, Tuzla, 34956, Istanbul, Turkey
[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785
![[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785](/thumbs/84/89645202.jpg "[Krishna*, 4.(12): December, 2015] ISSN: (I2OR), Publication Impact Factor: 3.785")
IJESRT INTERNATIONAL JOURNAL OF ENGINEERING SCIENCES & RESEARCH TECHNOLOGY DESIGN AND IMPLEMENTATION OF BIST TECHNIQUE IN UART SERIAL COMMUNICATION M.Hari Krishna*, P.Pavan Kumar * Electronics and Communication
Peak Dynamic Power Estimation of FPGA-mapped Digital Designs
Peak Dynamic Power Estimation of FPGA-mapped Digital Designs Abstract The Peak Dynamic Power Estimation (P DP E) problem involves finding input vector pairs that cause maximum power dissipation (maximum
COE758 Xilinx ISE 9.2 Tutorial 2. Integrating ChipScope Pro into a project
COE758 Xilinx ISE 9.2 Tutorial 2 ChipScope Overview Integrating ChipScope Pro into a project Conventional Signal Sampling Xilinx Spartan 3E FPGA JTAG 2 ChipScope Pro Signal Sampling Xilinx Spartan 3E FPGA
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow Bradley R. Quinton*, Mark R. Greenstreet, Steven J.E. Wilton*, *Dept. of Electrical and Computer Engineering, Dept.
Design and Implementation of Timer, GPIO, and 7-segment Peripherals
Design and Implementation of Timer, GPIO, and 7-segment Peripherals 1 Module Overview Learn about timers, GPIO and 7-segment display; Design and implement an AHB timer, a GPIO peripheral, and a 7-segment
On-Chip Instrumentation and In-Silicon Debug Tools for SoC Dr. Neal Stollon HDL Dynamics
On-Chip Instrumentation and In-Silicon Tools for SoC Dr. Neal Stollon HDL Dynamics neals@hdldynamics.com So What do we mean by On-Chip Instrumentation and In-Silicon? What will this talk cover An Overview
Bit Swapping LFSR and its Application to Fault Detection and Diagnosis Using FPGA
Bit Swapping LFSR and its Application to Fault Detection and Diagnosis Using FPGA M.V.M.Lahari 1, M.Mani Kumari 2 1,2 Department of ECE, GVPCEOW,Visakhapatnam. Abstract The increasing growth of sub-micron
2e 23-1 Peta Bits Per Second (Pbps) PRBS HDL Design for Ultra High Speed Applications/Products
2e 23-1 Peta Bits Per Second (Pbps) PRBS HDL Design for Ultra High Speed Applications/Products 1 2 Prof.PNVM SASTRY DR.D.N.RAO Dean- Engineering-IT EDA Software Industry CELL Principal & R&D CELL & ECE
CHAPTER 3 EXPERIMENTAL SETUP
CHAPTER 3 EXPERIMENTAL SETUP In this project, the experimental setup comprised of both hardware and software. Hardware components comprised of Altera Education Kit, capacitor and speaker. While software
Design of Fault Coverage Test Pattern Generator Using LFSR
Design of Fault Coverage Test Pattern Generator Using LFSR B.Saritha M.Tech Student, Department of ECE, Dhruva Institue of Engineering & Technology. Abstract: A new fault coverage test pattern generator
Based on slides/material by. Topic 14. Testing. Testing. Logic Verification. Recommended Reading:
Based on slides/material by Topic 4 Testing Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College London!! K. Masselos http://cas.ee.ic.ac.uk/~kostas!! J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html
Clock Gating Aware Low Power ALU Design and Implementation on FPGA
Clock Gating Aware Low ALU Design and Implementation on FPGA Bishwajeet Pandey and Manisha Pattanaik Abstract This paper deals with the design and implementation of a Clock Gating Aware Low Arithmetic
Introduction to JTAG / boundary scan-based testing for 3D integrated systems. (C) GOEPEL Electronics -
Introduction to JTAG / boundary scan-based testing for 3D integrated systems (C) 2011 - GOEPEL Electronics - www.goepelusa.com Who is GOEPEL? World Headquarters: GÖPEL electronic GmbH Göschwitzer Straße
Digital Blocks Semiconductor IP
Digital Blocks Semiconductor IP DB1825 Color Space Converter & Chroma Resampler General Description The Digital Blocks DB1825 Color Space Converter & Chroma Resampler Verilog IP Core transforms 4:4:4 sampled
MANAGING POWER SYSTEM FAULTS. Xianyong Feng, PhD Center for Electromechanics The University of Texas at Austin November 14, 2017
MANAGING POWER SYSTEM FAULTS Xianyong Feng, PhD Center for Electromechanics The University of Texas at Austin November 14, 2017 2 Outline 1. Overview 2. Methodology 3. Case Studies 4. Conclusion 3 Power
CMOS Testing-2. Design for testability (DFT) Design and Test Flow: Old View Test was merely an afterthought. Specification. Design errors.
Design and test CMOS Testing- Design for testability (DFT) Scan design Built-in self-test IDDQ testing ECE 261 Krish Chakrabarty 1 Design and Test Flow: Old View Test was merely an afterthought Specification
3. Configuration and Testing
3. Configuration and Testing C51003-1.4 IEEE Std. 1149.1 (JTAG) Boundary Scan Support All Cyclone devices provide JTAG BST circuitry that complies with the IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan
Analog, Mixed-Signal, and Radio-Frequency (RF) Electronic Design Laboratory. Electrical and Computer Engineering Department UNC Charlotte
Analog, Mixed-Signal, and Radio-Frequency (RF) Electronic Design Laboratory Electrical and Computer Engineering Department UNC Charlotte Teaching and Research Faculty (Please see faculty web pages for
Investigation of Look-Up Table Based FPGAs Using Various IDCT Architectures
Investigation of Look-Up Table Based FPGAs Using Various IDCT Architectures Jörn Gause Abstract This paper presents an investigation of Look-Up Table (LUT) based Field Programmable Gate Arrays (FPGAs)
Innovative Fast Timing Design
Innovative Fast Timing Design Solution through Simultaneous Processing of Logic Synthesis and Placement A new design methodology is now available that offers the advantages of enhanced logical design efficiency
Remote Diagnostics and Upgrades
Remote Diagnostics and Upgrades Tim Pender -Eastman Kodak Company 10/03/03 About this Presentation Motivation for Remote Diagnostics Reduce Field Maintenance costs Product needed to support 100 JTAG chains