Design and Implementation of Johnson Counter using Set D-Flip Flop

Transcription

1 International Journal of Control Theory and Applications ISSN : International Science Press Volume 10 Number Design and Implementation of Johnson Counter using Set D-Flip Flop M. Anto Bennet a, T.R. Dinesh Kumar b, M. Pooja c, K. Anusuya d and A.P. Kokila e a Professor of Electronics and Communication Engineering, VEL TECH, Avadi, Chennai , Tamil Nadu, India. bennetmab@ gmail.com b Assistant Professor of Electronics and Communication Engineering, VEL TECH, Avadi, Chennai , Tamil Nadu, India c-e UG Students of Electronics and Communication Engineering, VEL TECH, Avadi, Chennai , Tamil Nadu, India 1. Abstract: Low power design of devices is necessary since there is an increase in demand of portable devices. This work proposes the modified Single Edge Triggered (SET) D-flip flop design for the low power applications. The overall area of the design is optimized to increase the chip density by introducing the 10-transistor model. Design of flip flop is performed at 125nm technology. The simulation software used in this work is Tanner EDA. Simulation results can be obtained in such a way that area and power can be largely reduced. This SET D-FF design provides the better choice for portable applications. This design is further implemented to form a counter. The overall power consumed by the counter is reduced and power consumed by this design is about 40%. Keywords: Personal Digital Assistants (PDA s), Single Edge Triggered (SET), D-flip flop, Tanner EDA (Electronic Device Automation), Counter. Introduction The energy consumed by the circuit has become one of the important factors in digital systems, because of the requirement of reducing this energy in the high-density circuits that are possible with submicron technology, and of extending the battery life in portable systems, such as high performance portable computers and personal digital assistants (PDA s) with multimedia and wireless communication capabilities. The design of low power circuits can be tackled at different levels, from system to technology. We here concentrate on techniques at the logic level for CMOS technology, aiming at reducing the average energy consumed in the data path registers during an operation. This energy accounts for a large fraction of the total energy of the system. The latency of the flip-flops or latches should become lesser portion of the cycle time since clocking networks and flip-flops consume about 30-70% of the total power in the system. Power, area, delay of the flip flop should be reduced and also should be made available for operation in the threshold region. The advance in portable applications such as Laptops, mobile phones and PDAs requires low power VLSI devices. Performance degradation occurs due to double edge triggering method because of complex design. The fact is that, when the complexity gets increased, it affects the signal propagation along the critical path. Double-edge triggered (DET) flip-flops have 59 International Journal of Control Theory and Applications

2 M. Anto Bennet, T.R. Dinesh Kumar, M. Pooja, K. Anusuya and A.P. Kokila been proposed as one of the techniques that can produce significant energy savings (20%) for this type of systems. However, the synchronization model imposed by DET flip flops is not always applicable. For this reason, we focus more on the conventional single-edge triggered (SET) flip-flops. Flip-flop structures are proposed and models for energy consumption were developed, resulting in criteria to select the most-appropriate structure depending on the flip-flop activity. The energy consumed by a D flip-flop (called in the sequel ), is used as a framework and a reference to compare with the proposed structures. Moreover, the energy consumed during a transition depends on the present and next states of the flip-flop and on the relative timing of the transitions. Output state of the flip flop should be maintained even if clock is removed, produces defective logic degrees as when clock is removed. It takes place because of charge leakage from the output node capacitances. The logic gate delays in a clock duration is lowering by using 25% consistent generation in high-performance microprocessors, and is approaching value of 10% or below beyond 0.13um technology. Ultra-low-power designs have relied upon aggressively reducing the power supply voltage, in some cases causing sub-threshold operation in addition to threshold voltage (V th ) hopping. Research in the sub-threshold region of operation highlights the advantage of operating transistors below their threshold voltage. Another circuit design technique devised to reduce the power consumption of high-speed circuits is the addition of switched-source impedance to logic gates. This method successfully lowers sub-threshold current when the circuit is in standby mode and can decrease power consumption in memory circuits by several orders of magnitude. However, the drawback is the requirement of predictable standby node voltages for proper placement of switched-source impedances. One characteristic of this scheme is that an extra two transistors must be added to the circuit for each logic gate or memory cell to account for the switch and the impedance. Some architectural approaches have been able to produce performance improvements across the spectrum of operating regions. In the Low voltage swapped body design, substrate of all PMOS transistor are related to floor and substrate of all NMOS transistors are linked to the supply voltage (Vdd) in this sort of substrate connection, bulk voltage is much less than the source voltage (VB < VS). As a end result, all devices acquire an amount of ahead frame bias equal to Vdd. but on this sub threshold grounded body layout, substrate of all NMOS and PMOS transistors are connected to ground. This form of substrate connection reduces the complexity of the design. Device sizing for circuits is examined with the view that these circuits could be optimized for sub-threshold but also operate effectively in super-threshold. There have been continual research efforts in recent years to explore the ultra-low power (low speed) region of operation. These efforts have been effective in applications where ultra low power consumption is a primary requirement and speed is of secondary consideration. 2. LITERATURE SURVEY There are several ways to implement a double edge-triggered flip-flop; these methods can be categorized into two ideas. The ideas the primary concept is to insert additional circuitry to generate internal pulse signals on each clock part the second idea is to replicate the pathway to permit the flip-flop to sample facts on every clock part. For the flip-flops with a pulse generator scheme, the essential idea is to use an inverter chain to have a series of delayed clock signals. Based upon the time difference of the clock edge and the delayed clock edges, the inserted circuitry will generate a new pulse [1,3]. When those new pulses return to the flip-flop circuitry, the whole component becomes a double edge-triggered flip-flop. One implementation of this idea is the symmetric pulse generator flip-flop proposed by [Anto bennet et. al.,]. Another implementation of the pulse generation idea is the conditional pre-charged double edge triggered flip-flop proposed by [Anto Bennet et. al.,]. However, both of these designs need a considerable increase in transistors for the implementation. For the two-way data path idea, there are several existing designs. [Anto bennet et. al.,] developed a static double edge triggered flip-flop. The design kept the same transistor count as the conventional transmission gate based SETFF, but reduced the operating frequency by half when compared to the SETFF for a fixed data through put. Two DETFFs are presented with International Journal of Control Theory and Applications 60

3 Design and Implementation of Johnson Counter using Set D-Flip Flop the same design idea, but one is implemented with pass transistors, and the other one is based on transmission gates. This design only needs 14 or 16 transistors, depending upon which gates are chosen. However, a clock chain is required to produce the correct timing that enables the circuit to function; this requirement increased the entire power consumption of the design. Besides, the transmission gate implementation actually saves more power than the pass transistor one although it has more transistors [4,6]. This power savings is because pass transistors will send out weak logic values under some certain circumstances due to the threshold voltage. Those weak logic values may cause spikes or prolong the unstable time of the system, which will result in extra power consumption. This result will also be shown in this project. Pass transistor based DETFF [7]. Another design made by [Tang], created a DETFF. This design connects two latches together in parallel, and uses pass transistors as switches to realize the two stages that transfer data and perform path selection. Tang s design was compared with those previous DETFF designs [2][6][8] for power, D-to-Q, and energy consumption [7], and was shown to provide the best results on all of the categories. Therefore, we set Tang s DETFF as our benchmark for the rest of this work.the merits of Tang s design include the following: (i) there is no need for a reversed clock signal and (ii) it requires only 12 transistors to implement whole design. However, the drawbacks are also obvious. First, the weak logic feature of pass transistors made the output of Tang s flip-flop take longer to reach stability, which will consume a lot undesired power. This result can be verified in [5], and in our simulation results as well. Second, although Tang s flip-flop requires a small numbers of transistors, it does not prove that the final area it required is the smallest. In order to satisfy the timing requirement of functionality, transistor MP1 and MP3 in Tang s design cannot use minimum-sized devices; they should be increased to 3 times larger than the minimum size. The use of the two multiplexers can ensure that the DET flip-flop is in the transparent phase only for a short time period after the rising and the falling edge of the clock. During the transparent phase, the complementary data signals can change the state of the latch. When the multiplexing transistors are off. The DET flip-flop is in the no transparent phase, where the last sampled data have been latched and the outputs Q and Qb are detached from the data signals D and Db respectively. In order to obtain the transparent phase periods a technique similar to that found in earlier systems is applied. Presents the pulses generated by the clocking circuitry. The same figure also shows that the CLK. CLK3 can be used to produce a narrow pulse. Having a high value for the time period tt-t: Immediately after the rising edge of the clock. As a result, the two series connected NMOS (MS. M6 and M9. M10) driven by CLK and CLK.3 respectively). Operate as an NMOS transistor driven by the narrow pulse CLK.CLK3. The same principle is applied for generating a narrow pulse (CLKl, CLK4) from CLKI and CLK4. After the falling edge of the clock (time period tq-t.,). Inhis case the series connected transistors M7. M8 and MI. MI2 operate as an NMOS transistor driven by the narrow pulse CLKI.CLK4. As a result, the DET flip-flop is in the transparent phase for a short time period immediately after the rising and the falling edge of the clock, ensuring its double edge-triggered operation. The voltage drop caused by the threshold voltage of the multiplexing NMOS transistors is not crucial. Since the latch has the ability to sense small voltage differences between the coniplenientuy sisals. Moreover no DC power consumption is caused, as the latch restores the reduced swing input from the multiplexer, to a full-swing output signal. As aresult no PMOS transistors are needed to Fermi complementary transmission gates. Also the lack of output inverters make the proposed flip-flop unsuitable for driving large capacitive loads. However as considered in [4] a typical heavy load value for a flip-flop can approach 200fF. Which can be accommodated from the proposed circuit without the need of additional output inverters.the double edge-triggered flip-flop has been compared by simulations to the static implementations of DET flip-flop is reported. Amodified version of SI has been also included in the simulations. In the modified [10] DET flip-flop a PMOS transistor (with w = l0uni) is connected in parallel with each of the transistors MI, M3, M4, M6, to Fermi a complementary transmission gate, Compared to the modified [9] DET flip-flop presents improved delay characteristics and in some cases lower power dissipation, but the total transistor count is lager. 61 International Journal of Control Theory and Applications

4 3. PROPOSED SYSTEM Set D Flip-Flop Design M. Anto Bennet, T.R. Dinesh Kumar, M. Pooja, K. Anusuya and A.P. Kokila Conventional SET D flip-flop operates both at growing edge or falling edge of the clock. For the correct operation of the flip-flop, the enter price needs to be maintained consistent just before setup time (t-setup) and just after maintain time (t-hold) the triggering fringe of the clock. A PMOS transistor is used inside the feedback path because it ends in a extra compact layout than the use of a NMOS transistor. In excessive noise environment, pass transistors may be changed with transmission gates. The design of 10-transistor terrible edge triggered SET D flip-flop is shown in Figure 1 in this design the comments circuit of the grasp phase is removed and in slave phase, feedback loop consists of transmission gate when clock level is excessive, grasp latch is practical and the inverse of the records is stored to an intermediate node X. When the clock is goes to LOW logic stage, the slave latch consisting of transistor TN2 and regenerative comments loop L1 will become purposeful and produces records at the output Q and QB. The SET D flip-flop continues the logic degree even if clock is completely grounded (stopped), proves that it is static in nature. The issue ratios of the transistors involved inside the SET D turn flop design may be determined out. In assessment to the traditional SET D flip-flop the 10-transistor SET D turn flop is nice due to decreased transistor count. The aspect ratios of the transistors involved in the SET D flip flop design can be found out. In comparison to the conventional SET D flip-flop the ten-transistor SET D flip flop is advantageous because of reduced transistor count. Figure 1: Design of 10 transistor negative edge triggered SET D ff This work ambitions the amendment of the 10-transistor design to lessen the overall region and strength consumption such that the design turns into higher applicable for the low power application. To keep with this, the design is first modified by way of changing the substrate connections. Buffering inverters on Figure 1 provide realistic Data and Clock signals, while they fed from ideal voltage sources. Capacitive loads simulate the fanout signal degradation. Since buffering inverters dissipate power even without any external load (due to their internal capacitances) we made the corrections of measured power of the shaded inverters, by interpolating the power over the wide range of loads. In case of the Data inverter, the correction took into account not only the inverter s intrinsic capacitance, but also the load Cl. Supply voltage has been scaled down in order to keep the power consumption under control. Hence, the transistor threshold voltage has to be commensurately scaled to maintain a high drive current and achieve performance improvement. Threshold or weak inversion conduction current between source and drain in an MOS transistor occurs when gate voltage is below. At the circuit design level, considerable potential for power savings exists with the aid of right desire of a good judgment style for imposing combinational circuits. That is because all of the crucial parameters governing power dissipation switching capacitance, transition activity, and quick-circuit currents are strongly influenced through the chosen good judgment style. Depending at the utility, the form of circuit to be implemented, and the layout approach used, exclusive performance elements come to be crucial, disallowing the formulation of universal rules for most useful logic styles. The good judgment style utilized in logic gates basically affects the speed, length, electricity International Journal of Control Theory and Applications 62

5 Design and Implementation of Johnson Counter using Set D-Flip Flop dissipation, and the wiring complexity of a circuit. The circuit postpone is decided through the wide variety of inversion ranges, the variety of transistors in series, transistor sizes (i.e., channel widths), and intra- and intermobile wiring capacitances. Circuit size depends at the number of transistors and their sizes and on the wiring complexity. Energy dissipation is determined with the aid of the switching hobby and the node capacitances (made from gate, diffusion, and twine capacitances), the latter of which in turn is a characteristic of the identical parameters that also manipulate circuit length. Finally, the wiring complexity is decided via the number of connections and their lengths and via whether single-rail or dual-rail good judgment is used. The characteristics may additionally vary considerably from one common sense fashion to another and therefore make the proper desire of logic fashion essential for circuit overall performance. As far as cell-primarily based layout strategies (e.g., standard-cells) and good judgment synthesis are involved, ease-of-use and generality of good judgment gates is of importance as nicely. Robustness with respect to voltage and transistor scaling in addition to various manner and operating situations, and compatibility with surrounding circuitries are important factors influenced by the implemented logic style Implementation using 10 Transistor The 10-transistor SET D flip-flop designs are examined in 125nm technology using Tanner EDA device v12.6. It gives the assessment result of the two designs. It s miles clean that the power and delay and hence the power delay made from the 10-transistor layout is better than the conventional 16-transistor layout. For that reason similarly the 10-transistor SET D flip-flop layout may be taken into consideration within the work. Figure 2: Modified SET D-Flip flop 10-tramsistor design The power delay product and frequency of operation plays significant role in designing of flip flop. Performance of earlier conventional flip flop with the proposed modified SET D flipflop bias flip flop for various lengths of interconnects is analyzed. The simulation results indicates that the modified SET D flipflop bias flip flop circuit operates in medium frequency range with better power-delay product as compared with the previous flip flop. The temperature sustainability and performance with the variation of aspect ratio is also better for modified SET D flipflop bias flip flop. Reduction of overall delay, power dissipation as well as operation of the flip flop at higher frequencies can lead to the better performance of the VLSI chip in on this design, substrate of all NMOS and PMOS transistors are related to ground shown in Figure 2. This form of substrate connection reduces the complexity of the design. All of the NMOS transistors are at no frame bias condition and 63 International Journal of Control Theory and Applications

6 M. Anto Bennet, T.R. Dinesh Kumar, M. Pooja, K. Anusuya and A.P. Kokila all PMOS are at ahead body bias circumstance. Modified SET D flipflop design is less sensitive towards supply and ground noise. The power delay product and frequency of operation plays significant role in designing of flip flop. Performance of earlier conventional flip flop with the proposed modified SET D flipflop bias flip flop for various lengths of interconnects is analyzed. Circuits can be compared at various frequencies to check its compatibility with the various applications. In each case, we can measure power consumed, delay introduced by the circuit. The circuit having less power-delay product should be considered better. Design better in one technology may not perform well in other technology, so the design must be tested in at least two technologies, to make it universally accepted. During the simulation and calculation, the designs are tested in 125 nm and technologies to prove their technology independence. Further the aspect ratios of the designs are reduced to see the effect on the output. Designs are tested taking power consumption as a measurement parameter at W/L = 2 and W/L = 2. The supply voltage is taken 0.3V, frequency of the signal 10 MHz at temperature of 25oC. Both designs are showing better output performance in terms of power consumption at less aspect ratio, but the output is better in case of W/L = 2 as the rise time and fall time of the output is 5% and 20% less respectively in comparison to the output at W/L = 1. More the aspect ratio less will be the rise and fall time. So the trade-off is required between area and performance according to the requirement in application. Earlier proposed design [10] with the reported aspect ratio and No Body Biasing is compared with the modified SET D flipflop design with W/L ratio 2.Design which is better in one technology may not perform well in other technology, so the design must be tested in at least two technologies, to make it universally accepted. During the simulation and calculation, the designs are tested in 125 nm technologies to prove their technology independence. In micropower analog circuits, on the other hand, weak inversion is an efficient operating region, and sub threshold is a useful transistor mode around which circuit functions are designed. Thus, by this method we can actually make the flip flop to operate in threshold region. Static Mode Of Operation The SET flip-flops are typically configured as master-slave configuration numerous single facet-induced D flip-flop designs have been proposed [6], [7] within the past to reduce either power or vicinity or delay vast research has been completed to optimize the place, power and delay and usually there is a change-off a number of the 3 [8], [9] other type of flip-flop is double aspect prompted which samples facts on both clock edges. SET flip-flops have lower power requirement (~ 20%) than set flip-flop. Double-part induced flip-flops suffer overall performance degradation whilst as compared to their single-edge counterparts, because of extra complicated design and the fact that most of the complexity boom influences the signal propagation along the vital route [10]. With the non-stop scaling of CMOS devices, sub threshold and gate leakage has becoming a chief contributor to the whole energy consumption. To manipulate the growing leakage in CMOS circuits, solution for leakage reduction need to be sought each at the manner generation and circuit degrees at the technique era stage, properly-engineering strategies by using retrograde and halo doping are used to reduce leakage and enhance brief-channel characteristics W/L = 2 is displaying less power consumption than the sooner proposed design with the mentioned aspect ratio and No-frame Biasing and thus it s far better desire for low power VLSI application all the NMOS transistors are at no body bias situation and all PMOS are at forward frame bias situation. For low power applications, sub-threshold operation is a better choice. Low power systems are slower ones, because of trade-off between power and speed as a result the flip flop circuit operating in sub-threshold area at medium frequencies is a higher alternative. The sub-threshold logic operates with the power supply Vdd much less than the threshold voltage Vth of the transistor. In this work the changed SET D flipflop biasing method is proposed, NMOS is grounded and PMOS is hooked up to supply and simulation and calculation guarantees the higher performance than the traditional flip flop. On this work emphasis is at the decrease delay and capacity to perform at better frequencies with out International Journal of Control Theory and Applications 64

7 Design and Implementation of Johnson Counter using Set D-Flip Flop compromising with the power dissipation in threshold area. The changed SET D flipflop bias layout of the flip flop works at better frequencies and having decrease delay, which in flip reduces power -delayed product.as a end result, all devices get hold of an amount of forward frame bias identical to Vdd. This sort of substrate connection reduces the complexity of the design. Johnson Counter using D Flip Flop Counters using D flip-flops can be designed in the same way as those using JK flip-flops. It is easier to construct the transition table because the inputs required are simply the outputs wanted in the next state. The logic is more complicated because there are no don t care states to simplify the K-maps. Formally, the system with D flipflops separates the two main functions of the system: storage of the present state (the D flip-flops) determination of the next state (the combinational logic connected to the inputs of the flip-flops) shown in Figure 3. Figure 3: Block diagram of Johnson counter A Johnson counter (or switch tail ring counter, twisted-ring counter, strolling-ring counter, or Moebius counter) is a changed ring counter, where the output from the final stage is inverted and fed again as input to the first level. The register cycles through a chain of bit-styles, whose length is same to two times the duration of the shift sign up, continuing indefinitely. These counters discover specialist applications, along with those much like the decade counter, virtual-to-analog conversion, and so forth. They may be applied without problems using D- or JK-type flip-flops. The main advantage of this type of ring counter is that it only needs half the number of flip-flops compared to the standard ring counter then its modulo number is halved. The Johnson counter within the fundamental interactive circuit is just one type of counter. It has 4 D-flipflops, and it counts from G1 to G8. This mathematical courting, in which 2 * flipflops = count, is a unique assets of the Johnson counter. To count from 1 to 10 we might want 5 flipflops; from 1-30 we might want 15 flipflops. in addition to the 4 D-flipflops, the circuit has eight two-enter AND gates. This too is a peculiarity of the Johnson counter: the circuit makes use of one two-enter AND gate in step with be counted, in order that the number of AND gates in the circuit is two times the quantity of D-flipflops.From every other attitude, the Johnson counter is the mixture of a decoder and a ring counter, a transfer-tail ring counter to be precise. From that view, our counter is a 4 bit switch-tail ring counter related to a 4-to-8 bit decoder. Circuit Model D-flip flop is exceptional acceptable for designing the Johnson counter. In this design, we will continually become aware of an unlawful counting sequence because more than one output may be high (logic 1). Seeing that each output is enabled with the aid of a transition from zero to 1 or from 1 to zero in a particular role within the counter, more than one transition will produce more than one output. The Johnson counter counts up and then down as the initial logic 1 passes thru it to the right replacing the preceding logic 0. A 4-bit Johnson ring counter passes blocks of four good judgment 0 and then four logic 1 thereby producing an eight-bit pattern. As the inverted output Q is attached to the enter D this 8-bit sample continually repeats. (proven in Figure 4) 65 International Journal of Control Theory and Applications

8 M. Anto Bennet, T.R. Dinesh Kumar, M. Pooja, K. Anusuya and A.P. Kokila Figure 4: Johnson counter circuit The ring counter that serves as the backbone of the Johnson counter. The circuit is referred to as a twisted ring counter due to the fact because the clock cycles, the circuit actions (or stretches) a signal thru a round chain of flipflops. The modifier transfer-tail is to emphasise that the source of the signal is the bad tail of the circuit; in different words, the complemented output of the remaining flipflop in the chain feeds the input of the first flipflop within the chain. Therefore, the final flipflop supplies the supply signal this is propagated through the flipflop chain. An essential element approximately the Johnson counter is that the circuit should be initialized efficiently so as for it to generate the desired counting collection. While the Johnson counter is first initialized, the handiest asserted piece of twine is the only connecting the complemented output of the closing flipflop to the input of the primary flipflop inside the counter. Then because the clock cycles, the signal originating from final turn flop propagates although all the flipflops till it reaches the output E. once the propagating signal reaches E, the signal at E adjustments level, in order that at the following clock cycle the brand new sign emanating from E will begin making its way through the counter. Table 1 Truth table of Johnson counter Clock pulse Input Output A Output B Output C Output D Sequence repeats In the above Table 1 the Johnson counter works within the following way : It takes the initial country of the counter to be On the primary clock pulse, the inverse of the remaining flip-flop can be fed into the first flip-flop, generating the nation On the second one clock pulse, because the final flip-flop continues to be at degree 0, every other 1 will be fed into the first flip-flop, giving the nation On the 0.33 clock pulse, the country 1110 is produced. At the fourth clock pulse, the inverse of the closing flip-flop, now a zero, might be shifted to the first flip-flop, giving the nation On the 5th, 6th and seventh clock pulse, the inverse of the remaining flip-flop, now a 0, will be shifted to the first flip-flop, giving the kingdom 0111,0011 and 0001.Then, after the following clock pulse, the primary nation of the flip flop repeats. Consequently, this Johnson counter has 8 distinct states : 0000, 1000, 1100, 1110, 1111, 0111,0011,0001 and the collection is repeated as long as there is enter pulse. As a consequence this is a MOD-8 Johnson counter. The MOD wide variety of a Johnson counter is twice the quantity of flip-flops. In the example above, 4 flip-flops have been used to create the MOD- International Journal of Control Theory and Applications 66

9 Design and Implementation of Johnson Counter using Set D-Flip Flop eight Johnson counter. So for a given MOD quantity, a Johnson counter calls for best 1/2 the variety of turnflops wanted for a ring counter. However, a Johnson counter calls for decoding gates whereas a hoop counter does not. As with the binary counter, one logic gate (AND gate) is needed to decode every state, however with the Johnson counter, every gate calls for simplest two inputs, irrespective of the quantity of flip-flops inside the counter. Notice that we re comparing with the binary counter the use of the rate up approach mentioned above. A Johnson counters constitute a center ground among ring counters and binary counters. A Johnson counter requires fewer flip-flops than a ring counter however typically greater than a binary counter; it has more decoding circuitry than a hoop counter but much less than a binary counter. for that reason, it every so often represents a logical desire for positive applications. 4. EXPERIMENTAL RESULTS Set D Flip Flop Output Waveform Figure 5: Output Waveforms of D-Flipflop Figure 5: Output Waveforms of Johnson counter 67 International Journal of Control Theory and Applications

10 M. Anto Bennet, T.R. Dinesh Kumar, M. Pooja, K. Anusuya and A.P. Kokila From the figure 5, we can see that, when the clock pulse remains in the falling edge, the input gets transferred to the output. And if, the clock pulse is present in the rising edge, then the output obtained is same as that of the previous output. Power Results: v1 from time 0 to 2e-007 Average power consumed -> e-007 watts Max power e-002 at time e-008 Min power e-007 at time 3.6e-008 Johnson Counter Output Waveform The above waveform of Johnson counter 9(shown in Figure 6) works in the following way : It takes the preliminary state of the counter to be On the primary clock pulse, the inverse of the last flip-flop may be fed into the primary flip-flop, producing the statem On the second one clock pulse, because the ultimate flip -flop remains at level 0, another 1 can be fed into the first flip-flop, giving the state on the 1/3 clock pulse, the state 1110 is produced. at the fourth clock pulse, the inverse of the final flip-flop, now a 0, can be shifted to the primary flip-flop, giving the state on the 5th, sixth and seventh clock pulse, the inverse of the remaining flip-flop, now a 0, could be shifted to the primary flip-flop, giving the state 0111,0011 and Power Results: v1 from time 0 to 2e-007 Average power consumed -> e-005 watts Max power e-002 at time e-010 Min power e-007 at time e-007 Table 2 Comparision table of Johnson counter by using 16 transistor and 10 transistor S.No. Johnson counter By using 16 transistor Johnson counter By using 10 transistor 1 Total number of transistors: 16 8 PMOS 8 NMOS Total number of transistors: 10 4 PMOS 6 NMOS 2 Dynamic in nature Static in nautre 3 Maximum power consumption: e-001 at time e Minimum power consumption: e-006 at time e Average power consumption: e-005 watts Maximum power consumption: e-002 at time e-010 Minimum power consumption: e-007 at time e-007 Average power consumption: e-005 watts Above comparision Table 2 shows the comparision between Johnson counter by using 16 transistor and 10 transistor having the subsequent parameters Total number of transistors, Average, maximum and minimum power consumption. International Journal of Control Theory and Applications 68

11 5. CONCLUSION Design and Implementation of Johnson Counter using Set D-Flip Flop Area and power consumption by the device are the main technological aspects to prefer a design over the other contending designs in low power applications. The modified design of SET D flip-flop shows better performance in terms of power dissipation and area among designs presented in this work. By implementing this in the counter design we can able to get very low power counter design and a portable compact counter. Thus, the Johnson counter model is designed by using this SET D-flip flop model. Also, the negative edge triggered gives low power than the conventional positive edge triggered flip flop and Dual edge triggered flip flop. Hence, the Johnson counter implemented by using modified SET D-flip flop design of negative edge triggered static design is suitable for portable application, as it is more area and power efficient. References [1] Aristides Efthymiou and Garside, D.(2004) A CAM With Mixed Serial- Parallel Comparison for Use inlow Energy Caches, Vol. 12, No. 3,pp [2] [3] [4] [5] [6] [7] [8] [9] Chi-Sheng Lin and Jui-Chuan Chang(2003) A Low-Power Precomputation - Based Fully Parallel Content-Addressable Memory, Vol. 38, No. 4,pp Oleksiy Tyshchenko and Ali Sheikholeslami(2008) Match Sensing Using Match-Line Stability in Content-Addressable Memories (CAM), Vol. 43, No. 9,pp Oleksiy Tyshchenko and Ali Sheikholeslami (2008) A 1-V 128-kb Four-Way Set Associative CMOS Cache Memory Using Wordline- Oriented Tag-Compare (WLOTC) Structure with the Content-Addressable-Memory(CAM) 10-Transistor Tag Cell, Vol. 11, No. 3,pp Po-Tsang Huang and Wei Hwang(2011) A 65 nm fj/bit/search TCAMMacro Design for IPv6 Lookup Tables, Vol. 46, No. 2.pp Rajendra Katti, Joseph Brennan & Frago, H. (2003), Low Complexity Multiplication in a finite field using ring representation, Vol.52, No. 4,pp Dr. Anto Bennet, M, Sankar Babu G, Suresh R, Mohammed Sulaiman S, Sheriff M, Janakiraman G, Natarajan S, Design & Testing of Tcam Faults Using T H Algorithm, Middle-East Journal of Scientific Research 23(08): , August Dr. Anto Bennet, M Power Optimization Techniques for sequential elements using pulse triggered flipflops, International Journal of Computer & Modern Technology, Issue 01, Volume01, pp 29-40, June Dr. Anto Bennet, M, Manimaraboopathy M,P. Maragathavalli P, Dinesh Kumar T R, Low Complexity Multiplier For Gf(2m) Based All One Polynomial, Middle-East Journal of Scientific Research 21 (11): , October International Journal of Control Theory and Applications

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