Radiation Hardening By Design
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1 Radiation Hardening By Design Low Power, Radiation Tolerant Microelectronics Design Techniques Steven Redant IMEC Emmanuel Liégeon Alcatel Space
2 The foundry problem... Rad-Hard foundries are leaving the marketplace Reduced demand from military customers Too small volumes Only 1 supplier in Europe left (ATMEL) Solution: Hardening commercial CMOS technologies US independent more advanced, deep sub-micron technologies possible Higher speed Low power Low volume/mass Low cost => A lot of interest from the (European) space community 2
3 Design Against Radiation Effects Using layout techniques to minimize the radiation impact Free library for European Space Industry Technology: UMC.18 µm CMOS, 6 metal Available through EUROPRACTICE (MPW shuttle every month) Very smooth co-operation between IMEC and UMC Stable commercial technology DARE library includes 78 Core Cells Scan equivalents for all flip-flops SEU hardened flip-flops included (HIT cell) 23 In-line IO Pad Cells (+ P/G + Corners + Fillers) 3.3V & 2.5V I/O s Includes LVDS Cold spare & 5V tolerance additions are being investigated Single Port SRAM Compiler PLL 3
4 Libraries used UMC 350 comb cells 92 FF + 64 Scan FF COM 52 comb cells 10 FF + 8 Scan FF Red COM DARE 52 comb cells 10 FF + 8 Scan FF + 8 SEU free scan FF 4
5 Available EDA tool views Liberty (.lib) file for 6 process corners using accurate table lookup timing model Synopsys Design Compiler / PrimeTime Synplicity Synplify ASIC Verilog & VITAL simulation Models Avant! Apollo layout and timing views Any LVS tool using CDL input 5
6 Project Flow DARE design - Imec Test Chip design - Imec Telecom Chip Design Alcatel Space Place & Route + checks - Imec Parasitic information for CWL model generation and ECO s MPW Manufacturing - UMC Packaging - EdgeTek MPW Manufacturing - UMC Packaging - HCM Testing Microtest EUROPRACTICE Radiation test - Alcatel Space Functional & Radiation test - Alcatel Space funtional test Imec 6
7 Actual chip sizes Commercial Library Pad Limited Chip size : x mm 2 Core size: x mm 2 Commercial Library reduced sub-set DARE Same Pad Limited, in-line pads Chip size : x mm 2 Core size : x mm 2 => 2 times bigger 7
8 Layouts DARE DROM COM DROM (= Reduced COM) DIE HARD 8
9 What if Staggered IO? Commercial In-line IO 6540 x 6540 = 42.77mm 2 Commercial Staggered IO 6360 x 4860 = 30.91mm 2 DARE In-Line IO 9418 X 9418 = 88.7mm 2 DARE Staggered IO (estimated) 8200 x 8474 = mm 2 => 2.25 times bigger 9
10 DROM ASIC DROM : Digital Signal Processing ASIC for Bent Pipe Processor running at 105 MHz 114 SRAMs = 84 kbits 104 SRAMS used at MHz max 10 SRAMS used at 52.5 MHz max (~ TPRAM functionality) LVDS I/O Total number of equivalent gates 1.3 MGates Total number of bond pads : 403 pads Package : CPGA
11 DROM design flow RTL level Graphical Design Entry RTL Simulation SPW/HDS (Cadence) HdlDesigner (Mentor) Modelsim (Mentor) Logic Synthesis & Scan insertion Reoptimization Design Compiler, Floorplan Manager, Test compiler, Tetramax (Synopsys) Post synthesis level Generate Custom WLM Static Timing Analysis Formal Proof Simulation Velocity, Formal Pro (Mentor) Parasitic files Floorplanning & Layout Parasitic files Post layout level Static Timing Simulation Formal Proof Velocity,Formal Pro, Modelsim (Mentor) Timing & DRC OK? NO ASP Design YES ASP Verification ASP Logic Synthesis TOS references generation Manufacturer ASIC Manufacturing 11
12 Timing closure after layout Example on a critical path in 105MHz domain with CWLM : td = 5.24 ns After 3 layout iterations : td = 6.14 ns (+17%) important to take some frequency margin during the architecture phase (~15%) Hold violations have to be fixed at least after first layout convergence problem after layout of the logic inserted to correct violations 12
13 DROM 13
14 Library comparison Comparison on operators/ DROM area Reduced COM = COM DARE = 3 x Reduced COM DARE/MH1RT : units problem (SOG / Standard cell) speed (delay) Reduced COM = COM DARE # Red COM DARE 2 times faster than MH1RT Power consumption COM 0.18 µm: DARE 0.18 µm: MH1RT 0.35 µm: 50 nw/gate/mhz 180 nw/gate/mhz 400 nw/gate/mhz 14
15 Single Event Effect (SEE) Tests Two types of test have been performed : Heavy Ions Test : The European Heavy Ions Facility of Louvain La Neuve has been used for this evaluation. Ions used in the course of the present evaluation : Ion Specy Energy LET Range (MeV) (MeV/(mg/cm²)) µm 15-N Ne Ar Kr Xe Proton Test : The CPO (Centre Protonthérapie d Orsay) Facility of the University of Orsay (France) has been used for this evaluation. Energy : 150 MeV, 100 MeV, 70 MeV, 50 MeV and 30 MeV. 15
16 Single Event Effect (SEE) Tests Selftest Configuration (Autotest) : specific test to easily control the nominal functionality of the ASIC Autotest 1 with a 45.8 MHz carrier waveform Autotest 2 with a temporal ramp Bist Configuration : to evaluate SRAM cells Scan Configuration : to evaluate D flip-flops (implemented physically) placed in several regions on the die SCAN 0 is for «all 0» initial pattern SCAN 1 for «all 1» initial pattern. 16
17 Main SEE Results No Single Event Latchup (SEL) No Single Event Hard Errors (SHE): Stuck bits No Single Event Functional Interrupt (SEFI) Only Single Event Upset (SEU) observed on basic cells : SRAM, DFF => Impact on DROM functionality is a transient perturbation but the ASIC recovers after few clock cycles NB : More detailed evaluation of 0.18 µm CMOS basic structures will be performed on the Test Chip March
18 Main SEE Results SCAN 1 SCAN 2 BIST Autotest 1 Autotest 2 t (HI and p+) = SEU/cell.day (GEO) t (HI and p+) = SEU/cell.day (GEO) t (HI and p+) = SEU/cell.day (GEO) t (HI and p+) = SEU/ASIC.day (GEO) t (HI and p+) = SEU/ASIC.day (GEO) 18
19 Total Ionizing Dose (TID) Tests 6 Functional Tests (Same as the ones used for SEE Tests) Selftest Configuration (Autotest) : Autotest 1 with a 45.8 MHz carrier waveform Autotest 2 with a temporal ramp Bist Configuration Scan Configuration : SCAN 0 and SCAN 1 Parametric measurements : Icc (1.8V and 3.3V) Bias during Irradiation in Autotest Mode 10 samples + 1 control Irradiation Steps : 0, 50, 70, 100 krad(si) Low Dose Rate 200, 500, 700 and 1 Mrad(Si) High Dose Rate Tests initiated - In progress 19
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