Introducing the New VERSALINE The Photomask Future has Arrived with MASK ETCHER IV 10 BEST Award Fourth Year Running.

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1 August 2003 Issue Business & Technical News from Unaxis Semiconductors Introducing the New VERSALINE The Photomask Future has Arrived with MASK ETCHER IV 10 BEST Award Fourth Year Running

2 Unaxis Insights Unaxis on the Path to Business Excellence 2 Customer Complaint Management at Unaxis Semiconductors 3 Feature Let There be Light! An overview of one of the chip industry s fastest growing markets high brightness LEDs. 5 5High performance LED headlights from Osram Opto Semiconductors Advanced Silicon 65 nm Dry Etch: the Photomask Future has Arrived The Unaxis Semiconductors Photomask business unit has developed new etch technology focused on the 90 nm and 65 nm technology nodes. 10 Advanced Packaging 3D Integration The packaging technology for tomorrow s performance needs contents contents Compound Semi&Microtechnology AIN Films for Bulk Acoustic Wave Devices 18 Introducing the VERSALINE Low cost of ownership for high volume etching&depsition 22 RF MEMS Analysis, Forecasts and Technology Review 26 VCSELs to Revolutionize Fibre Optic Communications 30 Index The new VERSALINE operator interface Unaxis Sputter Tool CLUSTERLINE

3 Front Cover Close-up view of self-aligning buffer interface station on the MASK ETCHER IV Unaxis Insights Kenneth T. Barry President, Unaxis Semiconductors Editor in Chief Juerg Steinmann, Global Communications Manager Unaxis Semiconductors Executive Editor Marion Turner, U.S. Marketing Communications Manager Unaxis Semiconductors Managing Editor Veronika Schreyer, is design Design /Layout Cactus AG Photography Michael Reinhard and Unaxis, unless stated otherwise Published by Unaxis Semiconductors P.O. Box 1000 FL-9496 Balzers Liechtenstein Printed by Südostschweiz Print AG If you have any questions or comments, please contact us at or fax back the reply card provided in this magazine. Chip, the Business & Technical News from Unaxis Semiconductors, is also available online at: editorial editorial Welcome to Chip 9! Since joining Unaxis Semiconductors in April, we have been analyzing and evaluating the current market conditions, and how we need to reposition ourselves to become even more competitive. We have developed a comprehensive strategy to ensure our readiness with the right products and services for you, our customers. I am pleased to announce the VERSALINE TM, a new, leading edge deposition and etching tool dedicated to volume production for compound semiconductors, MEMS and thin film head applications (pages 22 25). Our new MASK ETCHER IV system gained strong acceptance at Semicon West in July. Please be sure to read about our ground-breaking concept in ICP dry etch technology enabling 65 nm photomask production (pages 10 13). Reinforcing our commitment to improve the quality of our products and services, our St.Petersburg technology center received ISO 9001 and ISO certifications in June of this year (page 2). I would like to extend my sincere appreciation to you for your positive feedback, which enabled our winning of the VLSI "10 Best award in the category of semiconductor equipment suppliers for the fourth consecutive year ("Unaxis Semiconductors around the Globe insert before page 5). At Unaxis Semiconductors, we continue to seek emerging and leading edge technology opportunities one being the solid state lighting market. This market shows great potential in the coming years and is featured on pages 5 9. Another new and promising development is 3D integration, the packaging technology for tomorrows performance needs (pages 14 17). I look forward to meeting you at future semiconductor shows and events. Meanwhile, if you have any specific requests, or would like more information on our technologies or Unaxis Semiconductors in general, please me at chip@unaxis.com or use the reader reply fax inserted after page 20. I hope you enjoy reading this new edition of Chip! Sincerely, Kenneth T. Barry Unaxis Chip

4 Unaxis Insights Unaxis Insights Customer Value Unaxis on Unaxis Insights the path to Business Excellence Markus Baerlocher Unaxis Semiconductors Unaxis USA, Inc., St.Petersburg has now received high honors from the Swiss Association for Quality and Management Systems SQS (Swiss Association for Quality and Management Systems), the recognized qualification body for ISO standards worldwide. Unaxis USA is the headquarters of the global Unaxis Semiconductor Division. Besides the production site located in Truebbach, Switzerland, where there has been an SQS-certified ISO 9001:2000 management system since March 2002, Unaxis USA is also a major production site employing a total of 199 employees. Both the Corporate Environment Manager, Martin Hollenstein and the Division Business Excellence Coach, Markus Baerlocher were instrumental in the successful definition, setup and implementation of the integrated ISO 9001:2000 and ISO 14001:1966 management system. Unaxis USA, Inc. is the first legal entity in the division to apply and maintain an environmental management system according to the ISO 14001:1996 standard. This outstanding step on the stairway to excellence was possible due to the fact that all personnel at Unaxis USA, Inc. participated as a team. Supported actively by their Operation Manager, Wayne Pasco, and lead through the specifics of standards by James Coughlin, Quality Manager, and Bill Strand, Environment, Health and Safety Manager, the organization has now implemented a powerful management system as the backbone for future success and innovation. The wide span of business processes from R&D, sales, engineering, supply chain, assembly, and customer service is well defined and also well supported with the relevant and necessary tools and instruments. One remarkable aspect in the total added value chain, from the basic development to the servicing of the product installation at the customer site, is the very high qualification level of all employees involved. To maintain or even enhance this strategic success factor, the present effort of skill management will be kept at all levels of the company. By unanimous decision of all parties involved, a routine inspection by the SQS auditor will be carried out again in April We are looking forward to the day when we will be able to present all the valuable improvements achieved by Creating outstanding customer value (Unaxis USA, Inc. mission statement). For more information please contact: markus.baerlocher@unaxis.com 2 Chip Unaxis

5 Customer Complaint Management at Unaxis Semiconductors Dave Abremski Unaxis Semiconductors Complaints Customer Customer loyalty develops through sustained satisfaction with the product or service of a company. This can include everything from sales commitments, technical support, product reliability to the delivery of spare parts. Should any part of the business process break down, the customer s loyalty is put to the test. Customer support experts tell us that, despite an occasional failure, customers will remain loyal if their problems are dealt with quickly and effectively. One key area, where customers are testing your commitment towards customer satisfaction and loyalty, is the management of customer complaints. It is not so much the fact that a complaint can arise, but rather the professionalism in how the complaint is handled that makes the difference. Robert van der Putten Vice President, Customer Support, Semiconductor Division Customer Complaints C1 Periodical Failure Analysis Improvements Complaint Mangement Process Service Notification S1 Periodical Failure Analysis Improvements Internal Complaints Q3 Periodical Failure Analysis Improvements Complaints to Suppliers Q2 Periodical Failure Analysis Improvements Customer Figure 1: Complaint Management overview Complaint Improvement Immediate/corrective/ preventive actions Evaluation of database Semiconductors Periodical problem analysis and improvement Our customer s opinion counts In 2002, an independent survey measured the level of satisfaction among Unaxis customers. The Customer Opinion Survey looked at performance areas such as spare parts, sales representation, customer relationship, service engineering and complaint management. The results show customers overall satisfaction level as satisfied, however, as always, there is room for improvement. The analysis of our weak points showed customers were concerned with the way Unaxis Semiconductors handles complaints. The whole process of complaint management needed to be reviewed from finding a competent person to submit the complaint to, the processing of a complaint, to the way in which the complaint is settled. Improving the process To improve the existing complaint management process and take corrective actions regarding the comments from the customer survey, we analyzed the process to address the handling of complaints. The effort to develop and improve this process involved the interaction of many departments within Unaxis Semiconductors and input from many colleagues around the globe. Driven by the ISO 9001: 2000 system, we looked for the right process with a closed loop for continuous improvement. To be effective in handling complaints we needed a way to categorize them to ensure the complaint resided with the proper owner. Customer complaints are now part of the overall Complaint Management Process (Figures 1 and 2). The Customer Complaint Management process is a 10-step process starting with Unaxis Insights Unaxis Chip 3

6 Figure 2: Customer Complaint process Customer Complaint Customer satisfied with resolution to complaint Unaxis Insights Key Account Management Engineering Logged into SAP Local Complaint Manager Customer Support Assign to Complaint Owner Supply Chain Management an easy access template located on the Unaxis Intranet (Figure 3). All Unaxis employees who interact with customers are trained on how to access and use this template. On completion of the template, a confirmation number for the complaint is generated. This confirmation number automatically triggers a notification to the appropriate customer complaint manager who is Sourcing Center Complaint Manager others Verify effectiveness of the process (KPI-B/W) 2nd level responsible for contacting and assigning a complaint owner. Once the complaint is entered into SAP, it can be processed, tracked, measured and managed to completion. Getting there wasn t easy. Coordinating many departments within Unaxis and input from colleagues around the globe made it happen. To keep a focus on any open complaints, scheduled review and status update meetings have been scheduled with senior management. During these reviews complaints can be escalated to provide the necessary resources in order to bring complaints to completion. The Customer Complaint process is already in place and utilized in the United States and Europe. The remainder of the Semiconductor Division is currently being trained, with a complete global rollout by the end of Measurements collected in SAP are used as key data for further improvements and are constantly being implemented. If customer satisfaction creates customer loyalty, then the Unaxis Customer Complaint process is a means to achieve that satisfaction. For more information please contact david.abremski@unaxis.com Customer complaint: Any verbal or written expression of dissatisfaction by a customer whether justified or not caused by Unaxis not meeting his/her expectations, specifications, needs, or requirements is defined as a customer complaint. Goals and principles of customer complaint management Any Unaxis employee can generate a customer complaint. Single point of contact by division, subsidiary, and sourcing center. Every complaint has an assigned problem owner. The customer is involved in defining an agreeable solution. Constant status overview is available. The process allows for escalation to apply the required resources. Response and resolution time are measured and recorded. The complaint data is analyzed and used for continuous improvement. Figure 3: Customer Complaint input template 4 Chip Unaxis

7 Feature An overview of one of the chip industry s fastest growing markets high brightness LEDs. Feature Behind the surprisingly low-profile headlights on a futuristic sports car are high-performance LEDs from Osram Opto Semiconductors. The study by top Italian designer Pininfarina was presented at the 73rd International Geneva Car Show. Valerie Thomson, Technical Journalist, Zurich High brightness (HB) LEDs show up in the most unexpected places these days sewn into ballet dancers costumes, spa pools and hotel lobbies. The burgeoning of applications and new uses for bright, cool light sources is an echo of the boom which occurred when transistors replaced vacuum tubes. Manufacturers have improved illumination power to the point that even machine vision equipment suppliers have adopted HB-LEDs as part of the systems used to inspect plastic cards, cell phones, semiconductors and surfaces for defects. Volpi AG, a global leader in the manufacture of cold light sources for machine vision, microscopy, and other specialized applications has been using expensive fiber optics for the illuminators it sells to Siemens, Nokia, Solistic, and Martin Marietta. By adopting HB-LED technology, it was able to introduce a new line of high margin products. Some of our new products are only possible thanks to HB- LEDs, says Michael Friedrich, marketing manager. It is easy to see why the 50 year old firm is an early adopter of the technology. We ve been able to develop new products and new applications. Their reliability gives our customers a tremendous advantage, with 35,000 to 70,000 hours of lifetime before the need for replacement, says Friedrich. A compelling market opportunity Longevity and low power consumption are just some of the drivers of the multicolour LED market, now worth about $2 billion a year. Machine vision and architectural lighting are the niche markets at the moment, representing about 5% of the market, according to market researchers. By far, the handheld device sector is the largest with 40% market share. It also has the greatest growth potential in the short run, according to the latest data from Intertech Corporation, a high tech consulting firm based in Portland, Maine. LEDs as backlights in LCD monitors are another large potential market. It grew by 105% to 32.2 million units in Sales growth rates are about 50% per year. Typical applications are traffic lights and signage, as well as the handheld electronic market, consisting of mobile phones (a market that grew from 400 million units shipped in 2001, to 420 million units in 2002), PDAs and cell phone/ camera combinations, as well as portable entertainment devices. Earlier market forecasts of a $3 billion market by 2006 may have been too cautious, according to Intertech. By 2005, LEDs will begin to make significant inroads into markets for indoor/outdoor lighting, automotive interior/exterior lighting, shipboard lighting, gaming machines, and toys, Dr. Robert Steele, Strategies Unlimited Unaxis Chip 5

8 Mobile phone cameras can be equipped with LED flash to replace conventional discharge lamps. With an LED the light flash is immediate, no need to wait for the bulb to charge up again. Feature Many are hoping the LED demand will get a big boost by the Kyoto agreement, which the European Union is expected to translate into a law requiring all lights to change from magnetic to electronic converters. US energy research has also demonstrated the HB-LED s environment efficiency. A short history of LEDs General Electric developed the first practical light-emitting diode. Steady evolution based on optimizing efficiency ensued. Over time, Hewlett-Packard developed the market for using HB-LEDs in red traffic lights and automobile brake lights. A breakthrough came in the early nineties when Nichia and the Japanese researcher, Shuji Nakamura, pioneered processes for reliable multi-coloured LEDs, eventually developing a low power, blue spectrum LED and laser diode which enabled the rapid replacement of traditional green, blue, violet, ultraviolet and white light sources. Blue LEDs proved remarkably popular in electronic devices around the world, as well as in automotive applications, led primarily by Osram Optical Semiconductor s efforts. The energy saving features of HB-LEDs has become a big attraction. Aixtron was named to the Dow Jones Sustainability Index and is now held in a number of professionally managed investment fund portfolios because of its environmentally friendly stance its equipment can be used to make solar cells and supports manufacturing energy saving lights, lasers and screens. The technology leading lights When it comes to materials, compound semiconductor processes such as GaN dominate, particularly for blue, green, and white LEDs. Since 1999, the market for GaN devices has grown by 221% to $1.35 billion. The main players today are Nichia, Toyoda Gosei, Cree, Lumileds and Osram. The industry is expanding as host of newcomers from Taiwan enter the market, adding Steele, including UEC, Epistar, Formosa Epitaxy, South Epitaxy and Highlink. There is a growing interest from Taiwan, agrees Notker Kling, Unaxis Semiconductor s VP of Compound Semi and Microsystems business unit. The manufacturing process that turns GaN-based materials into blue spectrum light is called MOCVD (metalorganic chemical vapor deposition). There are two main suppliers of these platforms, Emcore and Aixtron, says Ann McDonald, a veteran chip industry editor and founder of CompoundSemi News. Fierce competition between the two helped to accelerate the manufacturing of high brightness LEDs and blue laser diodes. Orange and red toned devices are made in InGaAlP. Lumileds and Toshiba, as well as Osram are leading the way, she says. 6 Chip Unaxis

9 The Unaxis Semiconductors SHUTTLELINE TM has become important for GaN LED structures Notker Kling, Unaxis Semiconductor s VP of Compound Semi and Microsystems business unit, St.Petersburg, Florida While companies such as Aixtron and Emcore have become industry standards for the epitaxial material growth required to make GaN LED structures, Unaxis SHUTTLELINE system has become important for device production involving dry etching and PECVD processes. Obtaining brighter LEDs at acceptable costs requires high performance fabrication processes. Although device geometries are not critical for the new HB-LEDs, the materials being dry etched do present significant challenges. As an emerging technology, there is a wide range of materials being included in devices which must be addressed. These materials range from various combinations of III-V compounds, to dielectrics, to indium oxide. All layers must be either etched or deposited with high quality, stable processes to obtain high brightness devices. The wrong systems or processes will affect performance and costs. To avoid the low yields in the manufacturing process it is important that processes be optimized. For example, the wrong etching process for GaN materials can result in surface morphologies which include pits and pillars or profiles with an undesired shape. The relatively small wafer size used in GaN production, 2" predominately and currently transitioning to 3", requires that dry etching systems support high throughput. Unaxis has developed an Inductively Coupled Plasma (ICP) technology which can handle sapphire and silicon carbide substrates used for GaN devices. The ICP technology is particularly adept at providing the process flexibility for the many materials requiring dry etching while maintaining the needed etching rates. Similarly, a PECVD batch system is available to support the throughput requirements necessary for deposition of high quality dielectrics such as SiN x and SiO 2. Unaxis has developed a tool which can provide effective etching and deposition processes, while maintaining high yield and satisfying capacity requirements. Fitting into the batch production environment with a small footprint and low demands on facilities was also an essential requirement. Feature Concept vehicles from the likes of Ford and Volkswagen, use white HB-LEDs in the headlamps. They consist of a cluster of dozens of LEDs controlled by software to produce various beam patterns. (Image courtesy of Barco) The art of making light The fabrication of HB-LEDs requires the understanding of optical properties of the materials used, how to manipulate thin films, substrates, as well as packaging, in order to achieve high efficiencies. It is still quite an art to manufacture the devices. It s a complex process, says Dr. Steele from Strategies Unlimited. In addition, the substrate size is still small. It is still all 2 inch wafers. Many have tried and failed. There s a lot of knowhow required, plus there are a lot of patents, which can prove to be a minefield for innovators, adds Steele. Unaxis Chip 7

10 Feature The future is bright The LED industry has its collective eye on the $15 billion general illumination market. Eventually, solid-state lighting will replace incandescent bulbs in most applications. So far an effective white light at the right price is still elusive. An LED can now exceed the luminous efficiencies of incandescent light bulbs, greater than 30 lumens per watt, according to Intertech, but the total light output and cost per lumen has to improve to be competitive with existing lighting technologies. The top LED applications Mobile appliances 40% Signs 23% Automotive 18% Valerie Thompson MSc., has been a freelance business and high-tech writer for more than 10 years. A Canadian based in Zurich, she tracks the trends and developments of Europe s purveyors of advanced technology. Advantages of LEDs over conventional lighting The best LEDs today are twice as efficient as incandescent bulbs, converting about 10 20% of the electrical energy to light. LEDs have no moving parts, no fragile glass encapsulation, no mercury, no toxic gasses, and no filament. Hence, there is nothing to break, rupture, shatter, leak, or contaminate. Illumination 5% Signals 2% Other 12% Unlike conventional light sources, LEDs are not subject to sudden failure or burnout. Surprising low profile headlights on a future FORD truck 8 Chip Unaxis

11 Advanced Silicon 65 nm Dry Etch: the Photomask Future has Arrived Michael D. Archuletta, Dr. Chris Constantine, Dr. Dave Johnson, Unaxis Semiconductors Wafer dimensions continue to accelerate downward towards ever smaller features and the legendary Moore s Law is still valid for current silicon devices. As wafer IC dimensions approach the physical limitations of silicon physics, the lithography techniques used to print these patterns on silicon become very difficult to perform. Advanced Silicon Current wafer scanners are able to print 90 nm technology node features with new 193 nm wavelength light sources. In fact, recent trends clearly show 65 nm technology node features will be possible, and some in our industry believe that novel optical adjustments to wafer scanners (i.e., water immersion lenses) will allow this technology to extend to 45 nm feature sizes! The photomask is expected to remain the primary transfer medium for mass producing integrated circuit patterns. Wafer lithography now requires the use of newer photomask techniques, such as phase shift masks, in order to achieve the very small features demanded by the current International Technology Roadmap for Semiconductors (ITRS). Now, more than ever before etching binary chromium (Cr) masks is the resolution-limiting step within the manufacturing process of advanced masks sets. Unaxis Semiconductors has brought the 65 nm technology node within reach more than one year earlier than predicted. We expect 90 nm node technology masks to be prototyped before the end of 2003 and 65 nm masks to be prototyped by the third quarter of months earlier than the most recent roadmap! Developing a solution For more than 2 years, the Unaxis Semiconductors Photomask business unit has been developing new etch technology focused on the 90 nm and 65 nm technology nodes. This fourth generation (Gen 4) ICP system is quite unique and will again allow our customers to push the limits of optical lithography. Gen 4 etch equipment will be mandatory for the photomask industry for a number of reasons discussed in the following pages. Mask error budget Three major manufacturing technologies are utilized in the production of photomasks: Pattern generation (writing or exposure of the circuit pattern information into a photo-sensitive resist on the mask blank), resist develop (wet chemical removal of resist in the exposed pattern areas on the mask blank) and absorber etch (wet chemical or ICP dry etch of the photo-absorber material Cr, MoSi, etc. using the developed resist as an etch mask). Each of these manufacturing processes contributes a portion of error to the formation of the actual vs. ideal pattern information. Any pattern deviation is typically known as the mean-to-target error, where target describes the various feature sizes and placement of the circuit pattern, as originally designed on the computer. The mean aspect describes how the manufacturing process(es) altered those features and their placement on the final mask. Obviously, as features sizes have continued to shrink, the allowable mean-to-target error budget has had to shrink proportionately. This has posed a significant problem in general for all mask manufacturing processes, but has posed a particularly difficult problem for the mask etch process as described in the following paragraphs. Pattern generation The accuracy of exposure tools has improved significantly over the past 5 to 10 years with smaller grid and beam sizes, enabling these tools to produce ever smaller features in the resist and place those features in more closely controlled proximity. However, resist systems have not evolved together with the beam placement accuracy of the pattern generators. In recent years, important advances in resist chemistry have been in the form of fast resists which can be exposed with low beam energy (e.g. chemically amplified resists). But, almost no advancement has occurred in resist materials as it pertains to final image formation, resist thickness, feature 10 Chip Unaxis

12 Mask dry etch key performance specifications Year Unaxis model no. CD uniformity CD linearity Etch bias (technology node) (3 sigma) (range) (average) 1995 MASK ETCHER I (0.18 µm) 35 nm - N/A - - N/A MASK ETCHER II (0.15 µm) 25 nm - N/A - 80 nm 2001 MASK ETCHER III (0.13 µm) 15 nm 20 nm 45 nm 2003 MASK ETCHER IV (90 nm) 8 nm 15 nm 30 nm 2004 MASK ETCHER IV (65 nm) 6 nm 8 nm 20 nm Figure 1: The evolution of dry etch error margins required for key performance parameters at the various technology nodes over the past eight years. sidewall angle, residue, and material stability. The net result is pattern generator accuracy has improved substantially with regard to placement and overlay accuracy, but for overall feature fidelity (CD uniformity, feature resolution, feature size linearity, etc.), the pattern generators cannot fully absorb their fair share of the smaller error margin needed for the 90 nm technology node. With no new resist systems foreseen, they cannot be expected to absorb any further error margin as we move into 65 nm technology node mask making. Resist develop The minimal evolution of resist systems equates literally to zero advancement in the method and accuracy of the resist develop. This process step has not and will not be able to absorb any additional reduction in error margin. once again to reduce the error tolerances in our equipment technology. Figure 1 illustrates the evolution of dry etch error margins required for key performance parameters at the various technology nodes over the past eight years (Gen1 3) and the error margin requirement today and in the near future (Gen 4). Dramatic performance improvements in dry etch system technology were required and achieved by Unaxis Semiconductors during the past eight years to keep the mask industry in step with the lithography demands of the device designers. So far, we are on track to continue this dry etch performance improvement trend. Feature size resolution Wafer IC dimensions are becoming so minute, they are literally smaller than the wavelength of the stepper light used to expose them on the wafer. As discussed earlier, one method of overcoming this problem is the use of special mask materials which provide half-wave attenuation or phase shifting of the stepper light. This produces exposures on the wafer even smaller than the exposure light wavelength. Another, more common method of resolving features on the wafer is to employ what are called optical proximity correction (OPC) features on the photomask. These are printed features on the mask which are too small to resolve at the wafer level, but they do add light to the edges and corners of very small features on the wafer. This light assist technique has been used effectively by pattern designers for many years. What has become problematic for mask makers is as average feature size dimensions decrease, OPC feature sizes on the mask are becoming too small to resolve. Figure 2 illustrates typical OPC features on an advanced photomask for a 0.13 µm technology node device. Some of the OPC features shown are less than 200 nm wide. As we move to the 65 nm technology node, OPC features will shrink to less than 100 nm. Very high resolution dry etch is the only answer. Advanced device patterning requires very high resolution imaging: e.g. optical proximity correction (OPC) Advanced Silicon Cr etch It should now be painfully clear that the only manufacturing step left to absorb the ever smaller error margin needed to meet the 90 nm and 65 nm mask making challenge is the etch process. One of the foremost advances in absorber etch technology came from Unaxis Semiconductors in 1995 with ICP dry etch technology. Since that time, Unaxis has introduced three successive generations of improved dry etch systems. Now, the collapsing ITRS roadmap has forced us Figure 2: OPC serifs on the photomask add light at the edges and corners of a feature when printed on the wafer. Unaxis Chip 11

13 Figure 4: Gen 3 dry etch process shows very large bright field/dark field etch signature disparity in the clear (window) vs. the dark (outer) area Ybor (1 window) test mask Gen 3 etch signature 1322 Unaxis Final Cr initial resist Iso clear 500 nm feature deviation from average Advanced Silicon Figure 3: A highly uneven pattern with > 99% Cr load in the window and < 1% Cr load on the remaining area Feature size linearity Another challenge facing the photomask industry as geometries diminish is the variety of small to large features on the same pattern level that must be precisely sized. For technology nodes 0.15 µm, the average mask level would typically have only one primary feature that needed to be sized as closely as possible to the original circuit design parameter. All other features on that mask level, smaller or larger than the primary feature, could be slightly under or over-sized because their dimensions were relatively inconsequential to the final device performance. This is no longer the case at 90 nm. For example, on a 90 nm mask, the primary design feature together with its various OPC features must all be carefully sized to their original design criteria because the margin for error on the wafer is so small. Figure 1 corroborates this new challenge. Note that in 1998, at the 0.15 µm technology node, CD linearity was not even a specified performance parameter. However, by 2001, CD linearity appears as a mask etcher performance requirement at less than half the total etch bias. This requirement continues to drop dramatically with each new technology node. Bright field/dark field linearity The MASK ETCHER III was an enormous breakthrough for the mask industry. This Gen 3 system was able to optimize the plasma etch of chromium films on glass so that the uniformity for high load Cr patterns and low load Cr patterns are the same. This was a major step forward for the industry providing a large yield improvement for most mask shops. This was during a time when most device pattern layers were fairly uniform across each mask, creating evenly distributed high or low chrome loads on different masks. However, as device geometries have grown smaller, device designs have grown more sophisticated. Logic devices now have large imbedded memory cells and memory devices have on-board logic circuits. The net result of this circuit integration are patterns with large open cells on the same layer, creating masks with large areas of unevenly loaded chrome. In other words, mask makers are now faced with high and low chrome loads on the same mask. Figure 3 is a picture of the Ybor Unaxis Semiconductors dry etch test mask used to emulate the high/low chrome load conditions of an advanced mask layer. The test features are written in FEP171 chemically amplified (E-Beam) resist Average: Sigma: Max: Min: Range: There are 64 measurement sites covering a 135 mm x 135 mm patterned area. Each site contains a variety of Iso/Dense and clear/dark features. This kind of pattern layer is aptly named a nightmare mask level by the industry in general. As device designs evolve, mask makers are seeing more and more of these advanced mask levels. The desired etch for this type of mask layer is to achieve a very low total etch bias in both the clear field (window) and the dark field (low Cr load area), while at the same time producing a very low critical dimension (CD) uniformity for the full range of feature sizes (feature size linearity). The Cr profile must be kept as close to 90 as possible. Why Gen 4? Until now, the required dry etch process improvement has not been forthcoming to support the performance level needed for 90 nm lithography. Over the past two years, the Unaxis Semiconductors Gen 3 ICP source has proven itself to be the most advanced dry etch reactor technology in the market; superior in all performance categories to any other competitive tool. However, as good as it is, even to our Gen 3 ICP reactor this asymmetrically loaded etch is a challenge. 12 Chip Unaxis

14 Ybor (1 window) test mask Gen 4 etch signature 1396 Unaxis Final Cr initial resist Iso clear 500 nm feature deviation from average Figure 5: Initial Gen 4 dry etch process shows almost no bright field/dark field etch signature disparity in the clear (window) vs. the dark (outer) area Average: Sigma: Max: Min: Range: Figure 4 is a box plot that gives a pictorial representation of the dry etch contribution across an Ybor (1 window) test mask (#1322) using a Unaxis Gen 3 ICP source. The various box sizes illustrate the relative CD uniformity (of 0.5 µm features) across the mask based on the amount of under or over etch of each feature from the average etch bias. The average etch bias appears quite good, (26.22 nm) but the global CD uniformity is quite high (23.14 nm, 3 σ). After more than two years of process development, the dramatic chrome load distribution on this type of mask level continues to pose a severe CD uniformity problem for Gen 3. Unaxis MASK ETCHER IV is the answer More than eighteen months ago, we understood some very fundamental concepts need to be realized and a new etcher, Gen 4, needed to be developed in order to achieve the necessary performance improvements for 65 nm mask making. Utilizing a unique and very advanced plasma ICP concept (patent pending), even early Gen 4 results demonstrated resist selectivity 2 3 times normal process conditions. Furthermore, Gen 4 incorporates a vastly improved Ybor (1 window test mask Gen 3 vs. Gen 4 dry etch data comparison summary Measurement Gen 3 Gen 4 feature size Etch results Etch results Ybor (1 window) Ybor (1 window) test mask # 1322 test mask # nm Iso Clear CD uniformity (3 σ) 23.1 nm 11.1 nm CD bias (average) 22.4 nm 29.6 nm 500 nm Iso Clear CD uniformity (3 σ) 23.1 nm 12.2 nm CD bias (average) 26.2 nm 31.8 nm 1500 nm Iso Clear CD uniformity (3 σ) 27.6 nm 16.6 nm CD bias (average) 34.5 nm 29.3 nm vacuum system and utilizes a radically new RF generator configuration which allows us to explore process areas which were not possible with Gen 3. The proof of course, is in the process performance results. Figure 5 is a box plot of the dry etch contribution across an Ybor (1 window) test mask (# 1396) using a Gen 4 ICP source. There is a notable absence of the etch disparity signature in the window area. The average etch bias is still quite good (31.78 nm) but the global CD uniformity is now almost half (12.19 nm, 3 σ), what was typical for Gen 3. Figure 6 is a more complete summary comparison of results for the two Ybor test masks #1322 and #1396. The summary includes measurement data for 300 nm, 500 nm and 1500 nm features across each mask. In each case, the C D uniformity from Gen 4 etch is vastly superior to the Gen 3 results. The total feature size linearity is in the 3 nm range across the various feature sizes for the Gen 4 etch results; this is a 4x improvement over the Gen 3 etch results. The high quality achieved with the MASK ETCHER IV (as depicted in Figure 5) represents a true breakthrough and literally marks a new era in dry etch technology for mask making. For more information please contact michael.archuletta@unaxis.com Figure 6: feature size linearity: Gen 3 = 12 nm Gen 4 = 3 nm Advanced Silicon Unaxis Chip 13

15 Advanced Packaging 3D Integration The packaging technology for tomorrow s performance needs Advanced Packaging Figure 1: Threedimensional integration concept Eric T. Eisenbraun, Ph.D., Albany Nanotech David Lishan, Ed Ostan, Hans Auer, Unaxis Semiconductors 3D integration represents a system level integration scheme wherein specific components (e.g. logic, memory, sensors, A/D converters, etc.) are fabricated on individual, separate wafer platforms, and then integrated onto a single chip-scaled package. This concept allows the integration of otherwise incompatible technologies, and offers significant advantages in performance, functionality, and form factor. That s why, from a technological perspective, this can be considered the merging of microsystems technology (MEMS), conventional packaging and wafer level packaging. Throughwafer Face-to-face bond Face-to-back bond A continuing demand exists for lower cost electronic products offering ever smaller size, higher performance and increased functionality. A significant portion of these improvements stem from the packaging and system-level integration of logic, memory, and other functional device ICs. Historically, advancements in electronic packaging have concentrated on reducing the package size. Given the high cost of board real estate and the progressive drive to system miniaturization and cost reduction, the demand to further reduce the effective area used in chip packaging requires novel approaches. 3D integration, also known as chip stacking and system-in-a-package (SiP), eliminates the need for extraneous package area while offering significant performance enhancements. The initial forays into 3D packaging were dominated by stacking of chips while inter-chip interconnects were Passivation Thinned substrate Device Layer 3 Interconnect layer 3 Bond Interconnect layer 2 Device Layer 2 Thinned substrate Bond Interconnect layer 1 Device Layer 1 Base substrate established by extra-chip wire bonding. Other methods of stacking were performed by using bumped wafers taking advantage of higher performance short lead interconnects to connect from chip to chip. This required that wafers be thinned to allow efficient through-wafer via processing to accommodate contact pads on both sides of the chip. Yet another method was used where connections were established over the edge of the die. The latest approach to 3D stacking technology involves processing of full wafers employing either wafer-to-wafer or die-to-wafer processing. These techniques involve the transfer of functional circuits from one wafer to another and connecting multiple layers to form the 3D package, as shown in Figure 1. The technique for building 3D packages or 3D IC s is based on wafer (or die) bonding and interconnect technology, while the interconnect is typically a vertical through wafer via interconnect. Wafer thinning is a prerequisite which facilitates through-wafer electrical connections and allows for sufficient heat dissipation; and also ensures that multi stack devices will yield thin packages. Companies ranging from IBM, Intel, Samsung, Micron, Infineon to startups like Ziptronix, Xanoptix and Tezzaron have recently presented detailed products and processes that involve interconnection of heterogeneous devices by stacking die on wafers or wafers to wafers. While dual level stacking will fulfill the majority of the short term needs, systems with up to four stacked functional levels have been demonstrated. The primary advantages of a stacked package approach involve reduced size, weight, and power consumption; as well 14 Chip Unaxis

16 Figure 2: SEM image of a feature 30 µm wide and 40 µm deep, etched at 12 µm/min. a b Figure 3: (a) SEM image of sidewall scallops using the conventional Bosch etching process. (b) Smoother sidewalls, using the Unaxis DSE fast gas switching technique with an etching rate twice that of (a). as improved performance enabled by the reduction of inter-chip power, ground, and signal distribution line lengths. This significantly reduces signal propagation delays associated with chip-to-chip electrical signals. Three-dimensional integration involves five key technologies: Wafer-to-Wafer Alignment Wafer Thinning Wafer Bonding Etching Metallization and Passivation In particular, etching and metallization as well as passivation of three-dimensional structures involve significant challenges related to the large features (compared to front end wafer processing), as well as the plurality of materials typically encountered in the stack during via formation. Etching for three-dimensional structures With respect to via etching, three dimensional integration structures typically present a combination of material systems, often including silicon, silicon oxide, nitride, and polymeric bonding layers. Moreover, these structures typically land on embedded metal structures. The presence of such a wide variety of material systems dictates the use of a flexible etching platform with dedicated clustered processing modules. In order to preserve lateral chip real estate, the etching must exhibit near vertical sidewalls with a minimum of taper through the bulk silicon layer(s), which represents the thickest portion of the stack in non-soi (Silicon-on-Insulator) approaches. Bosch etching employs a cyclical process of etching and passivation of polymeric material, has been successfully utilized in etching deep vertical vias through silicon, as shown in Figure 2. In addition, these applications demand excellent etch selectivity involving all layers in the stack in order to maintain etch depth control. This avoids significant overetch and the associated potential for lateral etching of structures. New deep silicon etching processes have been released which extended the original Bosch technology providing Si etch rates in excess of 18 µm/min for large vias of 100 µm, yet maintaining rates in excess of 7 µm/min for small, high aspect ratio features. Typical process results are shown in Table 1 and Figure 2. Feature dimension Depth etched Etching rate 2.5 µm trench 15 µm 8 µm/min 30 µm trench 40 µm 12 µm/min 100 µm trench 100 µm 18 µm/min Additional development in the process gas switching technology from the etch cycle to the passivation cycle have demonstrated the capability to produce sidewalls with virtually no scalloping. An example of the smooth sidewalls possible is shown in Figure 3. New processes are also available for highly productive etching of thick (>0.5 µm) SiN x and SiO 2 layers as well as multi-layer oxide/nitride stacks. Etch rates of >0.5 µm/min have been demonstrated. Non-photosensitive BCB (benzocyclobutene) resins are etched in standard fluorine-oxygen chemistries and with processing capability to achieve anisotropic straight sidewalls. Fluorine is used in the etching chemistry to cleanly Table 1: Typical etching rates for features of various dimensions Advanced Packaging Unaxis Chip 15

17 Figure 5: Smooth sidewall SiO 2 etching with hardmask or photoresist processes remove the silicon present in the BCB structure. Figure 5 shows etching of a thick SiO 2 layer. These etching processes are achieved using an ICP configuration with an RF bias electrode. A photograph of the chamber is provided in Figure 4. Advanced Packaging Figure 4: Open chamber on VERSALINE system Metallization of three-dimensional structures Sputtering is the deposition method of choice for liner and seeding base layer as well as barrier layer metallization. Sputtered films are either formed as complete metal systems for redistribution purposes or as plating bases, providing an adhesion/barrier layer plus a conducting layer. The conducting layer is then used as the conducting base during the electrochemical deposition while the plating process also provides the filling of the via holes. However, the ability of sputtering to provide a continuous, robust layer is strongly dependent on the aspect ratio of the structure. While today s interconnects used in wafer level packaging typically represent aspect ratios of up to 3:1, higher packing density designs will likely require higher aspect ratios in the future. These needs can potentially be met by metal chemical vapor deposition (CVD)-based VERSALINE process module shown with an electrostatic wafer chuck, provides etching capability for materials used in 3D integration. approaches, including atomic layer deposition (ALD) processes such as are currently used in the front end wafer level interconnect processes. Many metallization steps, especially those involving less challenging aspect ratios, are expected to continue to employ sputtering as the metal deposition method of choice. This is due to its maturity and compatibility to the majority of employed materials as well as the low cost of ownership. Typical parameters of sputtering include: High deposition rate, good physical and resistivity uniformity and tight control over temperature and film stress (see also the CLUSTERLINE specifications). In particular, the use of polymeric bonding/glue layers such as BCB present an effective thermal constraint for all postbond processing. In such cases the use of low temperature (i.e., < 300 C) deposition processes is dictated. Sometimes CVD and ALD processes cannot be carried out LLS EVO specification Batch sputtering system Wafer Size: 2" to 200mm Processes: Degas, Clean Etch and up to 5 PVD sources (DC, DC pulsed, RF) Typical film uniformities: <+/ 5% Typical clean etch uniformity: <+/ 15% Typical throughput: 4" 40 wph / 150mm 14 wph / 200mm 10 wph at such temperatures, and if they can, often yield films with less than optimal material properties. Accordingly, for these applications plasma-based CVD and ALD processes are under consideration, owing to their capacity to allow lower temperature processing. Plasma processes also offer the possibility of reaction pathways not accessible via thermal processing, and interruption of thermodynamically preferred growth routes. One example of this concept involves metalorganic ALD processing of ultra-thin tantalum-based films for copper barrier applications. While conventional thermally activated processing using, for example, tert-butylimido trisdiethylamidotantalum (TBTDET) and NH 3 as reactants yields highly conformal films at low processing temperatures (~250 C), the resistivity 16 Chip Unaxis

18 Unaxis Sputter Tool CLUSTERLINE of these films is prohibitively high (i.e. >1000 µω/cm). By comparison, use of the same tantalum chemistry with a pure hydrogen plasma counter cycle, instead of NH 3, yields films with much lower resistivity (~250 µω/cm), improved thermal stability, and more robust barrier performance. Isolation/Passivation In most applications of inter-wafer integration, electrical vias need to be fabricated through silicon layers. This presents integration difficulties in that the silicon layer is electrically active, leading to lateral wiring shorts. To prevent this, an insulating layer must be fabricated that separates the metal interconnect structure from the silicon layer. This is one of the most challenging passivation layers in the design, since it requires highly conformal films not just on the surface but also inside the vias. Accordingly, PECVD and ALD techniques are preferred for these c ritical applications. SiO 2 is the material of choice for this insulating layer; although silicon nitride, alternate metal oxides (such as Al 2O 3), and spun-on dielectrics (polymeric and inorganic) may also be considered. This decision is driven as much by integration-specific considerations, as well as the dielectric properties of the insulator. As with the interconnect formation, ensuring the integrity of the bonding process demands stringent control over the temperature of the isolation and passivation processing. This process also presents related challenges, for example the selective removal/cleaning of the dielectric from the via floor contacting to the underlying metal level. In addition, dielectric passivation layers are required on the functional layer surface to accommodate for the various required interconnect levels. For these CLUSTERLINE specifications Single wafer sputter tool Wafer Size: 150 to 300 mm Process modules: Degas, ICP Etch and up to 5 PVD modules (total of 6 modules) Typical film uniformities: <+/ 5% Typical clean etch uniformity: <+/ 10% Typical throughput: 40 wph applications, sputtering as well as PECVD are considered to form these layers. Summary Three-dimensional integration is a rapidly emerging technology that promises to provide substantial benefits in IC functionality and cost in a smaller, more efficient package. A wide variety of heterogeneous technologies can be integrated with this technique, including logic, memory, analog circuits, and sensor/detector technologies. This approach applies aspects of conventional packaging, on-chip interconnect, and MEMS technologies, and is expected to be applicable to a wide variety of commercial and military applications. For more information please contact hans.auer@unaxis.com Dr. Eric T. Eisenbraun is currently an Assistant Professor in the University at Albany (UAlbany) School of NanoSciences and NanoEngineering, and a Senior Research Scientist at Albany NanoTech (ANT). Since joining UAlbany in 1998, Dr. Eisenbraun has been involved in various areas of thin film research for microelectronic and hard coatings applications. Prior to his current position, he was Chief Scientist for Metal CVD at Tokyo Electron (TEL) Massachusetts, and prior to this, he was involved in the development of metal CVD processes at Lam Research Corporation. Dr. Eisenbraun received his Ph.D. in Physics from the University at Albany, and his B.S. in Physics at Rensselaer Polytechnic Institute. Dr. Eisenbraun has over thirteen years experience in thin film processing and integration. He has over 40 publications and one patent issued. Advanced Packaging Unaxis Chip 17

19 Compound Semi & Microtechnology AlN Films for Bulk Acoustic Wave Devices Stanislav Kadlec and Eduard Kügler, Unaxis Balzers Ltd., Christian Lambert, Unaxis SPTec Ltd. BAW (Bulk Acoustic Wave) devices, based on thin-film piezoelectric materials, represent a promising new technology for telecom applications and MEMS in the GHz range [1]. Compound Semi & Microtechnology Figure 1: Example of AlN thickness distribution mapping on a 8-inch wafer deposited using FlexiCath. Thickness of the AlN film on a Si wafer is 0.46 µm. It was measured with a spectral Ellipsometer M200F from Woolam. The edge exclusion is 10 mm. AlN thickness [nm] Average Min Max St. Dev sigma distribution 0.75% Min-Max range 0.88% Y [mm] The key to the emerging FBAR (Film Bulk Acoustic Resonators) and SMR (Solidly Mounted Resonators) technologies is piezoelectric thin film, such as AlN (Aluminum Nitride). Devices based on the thin film BAW technology promise very small sizes and better power handling capability than SAWs. This article presents some important process details regarding the AlN piezoelectric films especially results of film orientation, stress, roughness and uniformity X [mm] % 0.5% 0.1% 0.3% 0.1% 0.1% 0.3% 0.1% 0.5% 0.3% 0.7% 0.5% 0.9% 0.7% 1.1% 0.9% 1.3% 1.1% AlN deposition technology Unaxis Semiconductors addresses the BAW market with the development of a specific system enabling both excellent film uniformity and quality. The capability of the CLUSTERLINE 200 system, which already meets the high standards of the semiconductor industry regarding quality and impurity level, has been extended to include the deposition of AlN and other piezoelectric layers. The CLUSTERLINE 200 system is equipped with highly efficient gas conduction backside heating capabilities for precise temperature control up to 550 C. Other specification options are pulsed sputtering, RF sputtering and RF substrate bias. For the last few years Unaxis Semiconductors has been developing reactive magnetron sputtering of various piezoelectric layers, coming up with an ultra-high uniformity sputter source (Flexi-Cath) which enables a dynamic adjustment of the film thickness uniformity over the entire target lifetime. Excellent uniformity below 0.3% (1 σ) can be achieved (Figure1). This technology is also easily reproducible, as has been shown in a Unaxis application note [2]. 18 Chip Unaxis

20 Crystalline orientation It is well known for AlN as a hexagonal piezoelectric material, that the c-axis orientation perpendicular to the wafer surface is crucial. Highly oriented films are necessary for devices with the best electromechanical coupling. In BAW applications the process parameters as well as the quality of the bottom electrode are critical for obtaining the adequate orientation of AlN film as illustrated in Figure 2. It shows the rocking curve width of the AlN (002) peak in XRD as a function of the orientation of the bottom electrode (Pt), expressed also as width of the rocking curve. The platinum bottom electrode has been deposited on Unaxis Semiconductors equipment under various process conditions. The figure also shows the orientation remains almost constant across the wafer radius. AFM roughness AlN surface roughness is an additional important contributor to the device s functionality. Figure 3 shows an example of an AFM scan (1 x 1 µm) of a 2.3 µm thick film. In this case, the RMS roughness is just about 3.1 nm. With increasing temperature the Pt film gets smoother, thus improving the roughness of the upper AlN layer. Test resonator fabrication The BAW technology needs are of course much broader than the AlN deposition only. An example of a simple test resonator is shown in Figure 4. The acoustic mirror, all electrodes and the AIN layer itself have been deposited on the CLUSTERLINE 200 system, using 8-inch wafers. FWHM AIN (002) [ ] Process 1 Process 2, wafer center Process 2, r = 40 mm Process 2, r = 60 mm FWHM Pt (111) bottom electrode [ ] Top Electrode AIN A Resonator Bottom Electrode Acoustic Mirror 300µm 1.6µm 2GHz A Si wafer 100µm Ti/Pt AI AIN Figure 2: AlN orientation vs. Pt orientation, expressed as FWHM (full width at half maximum) of the XRD rocking curve measured with a Philips HRXRD instrument. Two AlN deposition processes are compared, process 1 for 1 µm and process 2 for 2.3 µm film thickness. Figure 3: An example of an AFM scan showing the AlN roughness, measured in tapping mode with a Digital Instruments Nanoscope. Figure 4: A test resonator built as a solidly mounted resonator Compound Semi & Microtechnology Unaxis Chip 19

21 Figure 5: A typical admittance curve of test resonators in the 2-GHz range Admittance [S] k eff % Q 434 Real (Y11) meas Real (Y11) sim Imag (Y11 meas Imag (Y11) sim Abs (Y11) meas Abs (Y11) sim *log (admittance) [S] Figure 5 presents typical measured admittance curves of the resonators in the 2-GHz range. The effective coupling factor k eff2 is 5.3 in this case, the quality factor is Q=434. Due to the highly uniform thickness of the AlN films on the wafer, the resonator frequency uniformity is excellent (Figure 6). Coupling and resonator quality factors also reach high values of 5.66% ±0.33% and 790 ±110, respectively. Compound Semi & Microtechnology ,000 Frequency [MHz] Average 2,106 Min 2,097 Max 2,126 St. Dev 6 3 sigma distribution 0.85% Min-Max range 0.68% 2,050 Y [mm] ,100 2,150 Frequency [MHz] 2,200 2, % 1.00% 0.60% 0.80% 0.40% 0.60% 0.20% 0.40% 0.00% 0.20% 0.20% 0.00% Summary Unaxis Semiconductors has developed an optimized AlN process, taking into consideration the Pt metal electrode and oxide sublayers seeding effects. Therefore, the CLUSTERLINE 200 system can be used for the deposition of extremely uniform, smooth piezoelectric AlN films, exhibiting a high degree of crystalline orientation and thus meeting the film specification requirements of BAW devices. The coupling factor of 5.66% ±0.33% and resonator quality of 790 ±110 have been achieved on test resonators. The reported thickness uniformity of AlN and frequency uniformity are both better than 0.3% 1σ on 6-inch as well as 8-inch wafers. Figure 6: Frequency uniformity of the resonators over an 8-inch wafer area X [mm] % 0.20% 0.60% 0.40% References 1 P. Jacot, C. Lambert, P. Krebs, S. Kadlec and S.Krassnitzer, Bulk Acoustic Wave Devices: A Promising Technology for Future Wireless Communications, Chip 7, P. Jacot, S. Kadlec, E. Kuegler and C.Lambert, Unaxis Application Note Aluminum Nitride Piezoelectric Thin Films for Bulk Acoustic Wave Applications Unaxis, September The MARTINA project IST , For more information please contact christian.lambert@unaxis.com 20 Chip Unaxis

22 Compound Semi & Microtechnology Introducing the VERSALINE Versatility combined with low cost of ownership Michael D. Archuletta, Vice President, Etch Business Unit, Unaxis Semiconductors The VERSALINE is the newest deposition and etching system for volume production from Unaxis Semiconductors. The tool is optimized to offer the lowest cost of ownership for single process module applications, including cassette-to-cassette loading. New benchmark setting processes are designed for etching and deposition on compound and silicon materials including MEMS and thin film head applications. Compound Semi & Microtechnology The VERSALINE was conceived to address a frequently encountered production scenario needed in today s compound semiconductor and microsystem fabrication facilities a single production oriented module. With a singlestep process module, customers are not burdened with the complexity and cost of cluster systems. A platform with a single module which performs a discreet process step, such as the VERSALINE, is a preferred solution when sequential or multiple process steps are nonessential. Unaxis uses this opportunity to present the advantages of providing etching and PECVD deposition processes on this new cost effective platform. Unified Platform Unifying platforms for automobiles, audio systems, as well as chip manufacturing systems reduces the number of parts, simplifies development, and most importantly, helps to lower costs overall. For this reason, two years ago Unaxis Semiconductors began reviewing its spectrum of systems designed for diverse markets and the corresponding wide range of deposition and etch process technologies, as well as wafer size requirements varying from 2 to 300-mm in diameter. The Unified Platform project plays a key role in substantially improving performance in the following three areas: Cost of ownership Time to market Benchmark setting processes For Unaxis, the Unified Platform is key to accelerating the development and launch of new solutions and thus speeding up innovation. It allows us to react faster to increased demand, shortens lead times and facilitates adaptation to the cyclical swings of the market. Customers benefit from this approach, making it much faster and easier to configure and ramp-up systems. Only a single, standardized training program is needed for operators, rather than training on many different platforms. Delivery times will be reduced considerably and finally, the benefits for service and maintenance are obvious. The Unaxis Unified Platform project now provides a clear path to upgrade with the following three systems, built around a standardized software and hardware set: Figure 1: Unified Platform basic systems SHUTTLELINE TM - Multi-process platform for R&D and pilot production VERSALINE TM - volume production for single Process Module applications CLUSTERLINE - high volume cluster tool 22 Chip Unaxis

23 The SHUTTLELINE Low volume and R&D multi-process platform The VERSALINE High volume cassette-to-cassette single process module system The CLUSTERLINE High volume cluster system (CLUSTERLINE 200 for wafer sizes 150 to 200 mm and the CLUSTERLINE 300 for wafer sizes 200 to 300 mm) Within the Unified Platform project compatible and standardized components, modules, handling platforms, software and graphical user interface (GUI) are utilized. The control system used in the VERSALINE is a flexible service-based program using Control Works -based software, with common core software modules. As a standardized system interface it controls the recipe management, scheduling, data collection/logging, etc., enabling functions such as e- diagnostics, data analysis and real-time fault detection. The VERSALINE system has a simple and reliable wafer-handling and user interface, yielding improved reliability and cost effectiveness not possible with larger cluster-type configurations. Process Module Options and Applications The process modules, covering a wide range of unique deposition and etch processes, are designed and built according to a standardized architecture to assure compatibility with the central handling unit where applicable, and simplifying system configuration. The process modules are engineered based on the experience of hundreds of systems operating in fabs worldwide. Figure 2: Graphical User Interface Figure 3: VERSALINE communication schematic with factory interface Compound Semi & Microtechnology Unaxis Chip 23

24 Compound Semi & Microtechnology Figure 4: Standard Temperature ICP PM Figure 5: High Temperature ICP PM Figure 6: Large area PECVD process module Etching Process Modules Inductively Coupled Plasma (ICP) Etching Standard Temperature (0 C 80 C) applications include GaAs via etch and MESA formation (Figure 4) High Temperature (100 C 180 C) applications include InP feature etching and any others where effluent control is important for low CoO (Figure 5) DSE III (Deep Silicon Etching) for MEMS production and wafer-scale packaging applications Pulsed High Frequency (PHF) RIE For etching very thin, damage-sensitive layers High Performance Oxide Etching (HiPOE) For deep oxide etch applications in AWGs, MEMS and Damascene structures Deposition Process Module Large Area Plasma Enhanced Chemical Vapor Deposition (PECVD) The large area PECVD process module is used for device encapsulation and many ILD (inter-layer dielectric) applications (Figure 6) Available processes for PECVD dielectric thin films include: SiO 2, Si 3N 4, SiO xn y. Process Technologies Improved benchmark setting processes for applications on compound and silicon materials including MEMS and thin film head applications have been developed for the VERSALINE. The etching and deposition processes are designed to support a broad variety of volume manufacturing applications. Etching Processes Unaxis boasts of a large library of starting-point etching processes for a variety of materials including: Dielectrics SiO 2, Si 3N 4, Al 2O 3, Photo Resist, Polyimide, Metals Al, Cr, Mo, Ti, W, Ta, Semiconductors Si, SiC, TaSi, Compound Semiconductors GaAs, InP, AlGaAs, InGaP, InSb, GaN The following are examples of guaranteed, state-of-the-art process specifications for applications which have become standard in our served markets: GaAs Via III 3 rd generation GaAs via etching for HBT (heterobipolar transistor) manufacturing (Figure 7) GaAs Etch Rate 8.3 µm/min 40 µm via 10.1 µm/min 100 µm via GaAs:PR Selectivity 15:1 Via Profile Sloped * GaAs Rate Uniformity < 5% Morphology Pillar Free * using sloped PR mask Figure 7: Optical cross section of 40 µm diameter via 24 Chip Unaxis

25 DSE III Third generation deep silicon etching for volume manufacturing of MEMS devices (Figure 8) Figure 8a: High load etching Figure 8b: Comb structure Figure 8c: High aspect-ratio etching with excellent profile control Mask Etch Mask Selectivity Profile Etch Rate Sidewall Undercut Rate Resist SiO 2 Uniformity Scalloping Rate Optimized 0.3 µm 20+ µm/min > 150:1 > 250:1 90 ± 2 3.5% length = 0.5 µm 100 µm feature AR 2:1 depth = 0.1 µm Rate Optimized 0.3 µm 7.0 µm/min > 100:1 > 200:1 90 ± 2 3.5% length = 0.5 µm 5 µm feature AR 20:1 depth = 0.1 µm Sidewall Optimized 0.1 µm 6.0 µm/min > 75:1 > 150:1 90 ± 1 3.0% length = 03 µm 100 µm feature AR 2:1 depth = 0.05 µm Sidewall Optimized 0.1 µm 5.0 µm/min > 60:1 > 150:1 90 ± 1 2.0% length = 0.3 µm 5 µm feature AR 20:1 depth = 0.05 µm SiO 2 Si 3N 4 SiO xn y Film stress MPa 300 MPa to +300 MPa 300 MPa to +300 MPa H 2 content NA < 300 C NA N f 1.46 to to to 1.9 Film uniformity ±2% ±2% ±2% Deposition rate 400 to 2500 Å/min. 80 to 500 Å/min. 100 to 500 Å/min. E b up to 5 MV/cm up to 5 MV/cm up to 5 MV/cm BOE (ref. TOX) 10:1 to 3:1 1:1 to 0.1:1 composition dependent Deposition temp. 100 C to 350 C 100 C to 350 C 100 C to 350 C Table 3: Controllable ranges of film characteristics using the VERSALINE Large-Area PECVD system. Specifications shown are selection guidelines. Actual film performance will be optimized for user-specific applications. Deposition Processes Unaxis offers guaranteed PECVD solutions for dielectric films including SiO 2, Si 3N 4 and SiO xn y. Features of Unaxis PECVD processes include controllable film stress, controllable refractive index and low hydrogen content. Table 2: DSE performance specifications (Table 2) & examples of typical microstructures created in Si using DSE processes (Figure 8) The VERSALINE is introduced to provide fabrication facilities with a platform which accommodates the most advanced technologies for etching and deposition. The platform consists of a reliable cassetteto-cassette handling system with easy to learn, field-proven control software while the modules utilize application specific features. Purposefully designing modules for processes and using easy maintenance hardware leads to undeniably reduced operational costs with increased uptime. These same concepts are applied to all Unaxis systems, resulting in a complete portfolio of leading-edge production solutions. For more information please contact jim.pollock@unaxis.com. Compound Semi & Microtechnology Unaxis Chip 25

26 Compound Semi & Microtechnology RF MEMS Analysis, Forecasts and Technology Review Jérémie Bouchaud, Dr. Henning Wicht, WTC Wicht Technologie Consulting Microsystems for Radio Frequency applications, known as RF MEMS, are expected to be the next breakthrough in micro-machined devices after accelerometers. Recognizing the significance of this exciting and important market, WTC carried out an in-depth investigation of applications, technical challenges and opportunities for RF MEMS. Compound Semi & Microtechnology Figure 1: RF MEMS industrial chain main bodies, companies and services Academic R&D Michigan Uni (USA) HRL (USA) Pennsylv. Uni (USA) IMEC (B) CEA-LETI (F) FhG ISIT (D) Tokyo Uni. (J) KAIST (Kr) GPSC (SGP) National and International Bodies DARPA (USA), 5th and 6th European FP, MST (D) RF-MEMS Start-ups Discera (USA) Xcom (USA) Magfusion (USA) MEMS Solution (Kr) Radant MEMS (USA) Teravicta (USA) MEMS Start-ups Memscap (F) PHS MEMS (F) RF MEMS manufacturers Large IC and MEMS manufacturers Motorola (USA) Intel (USA) Agilent (USA) JDS-Uniphase (USA) STMicroelectronics (F) Infineon (D) Philips (NI) Samsung (Kr) NEC (J) What are RF MEMS? RF MEMS are micro systems for radio frequency and millimeter wave applications. Examples of devices are micro-switches, tunable capacitors, micro-machined inductors, micromachined antennas, micro-transmission lines and resonators including micromechanical resonators, BAW (Bulk Acoustic Wave) resonators and cavity resonators. RF MEMS are manufactured Integrators with own MEMS development Defense & aerospace Raytheon (USA) Thales (F) DaimlerChrysler (D) Automotive Robert Bosch (D) RF devices manuf. Epcos (D) Murata (J) Integrators & users Wireless telecom terminals and infrastructure Automotive Space & Defence using conventional 3D structuring technologies, such as bulk micro machining, surface micro machining, fusion bonding or LIGA (X-ray Lithography). The materials used include Si, GaAs, SiC or SOI substrates. In addition to their potential for integration and miniaturization, RF MEMS offer lower power consumption, lower losses, higher linearity and higher Q factors than conventional communications components. RF MEMS also enable new architectures for the next generations of telecommunication systems, easily and rapidly reconfigurable and operating over a wide frequency range. The serial products commercially available now include inductors at Memscap (F), Bulk Acoustic Wave resonators already manufactured in millions of units at Agilent (USA) and Infineon (D). Furthermore, the first MEMS switches amongst the most challenging RF MEMS products to manufacture are available in evaluation kits at Teravicta (US) and Magfusion (USA). MEMS CAD & IP Coventor (USA) CorningIntellisense (USA) Memscap (F) MEMS Foundries DALSA (CA) Tronic's (F) Services MEMS Packaging Shellcase (IL) RF CAD & EDA Modelithicss (USA) Sonnet. (USA) Agilent (USA) RF MEMS market participants The RF MEMS industrial chain is shown in Figure 1. More than 120 industrial and research organizations work on RF MEMS 26 Chip Unaxis

27 Figure 2: RF MEMS market forecast Turnover (US $ million) worldwide. The RF MEMS market participants can be divided in five groups: Academic research institutions: more than 60 universities and institutes worldwide are involved in RF MEMS research. RF MEMS manufacturers including: RF MEMS start-ups that focus on developing RF MEMS MEMS start-up companies that specialize in MEMS development and RF MEMS Large IC and MEMS manufacturers and integrators who develop RF MEMS for their own specific needs Manufacturers of RF devices who are not traditionally involved in MEMS development Companies that offer a diverse range of services to the RF MEMS industrial chain including MEMS CAD and IP, foundry services, packaging and RF CAD and EDA (Electronic Design Automation) Integrators and users who cooperate with academic research organizations, RF MEMS manufacturers and service providers developing device specifications and integrating RF MEMS in their future products National and international authorities who are involved in promoting and financing research and development programs on RF MEMS An immense market potential The market potential is tremendous. Significant applications are identified as: Micro-switches to build impedance networks in front of power amplifiers and decrease the number of components in multi-standard mobile phones BAW resonators to replace bulky ceramic duplexers in 3G mobile phones MEMS inductors and tunable capacitors for integrated VCOs in GPS Switches, tunable capacitors and tunable inductors to build multi-standard and base stations which can be reconfigured Dense networks of micro-antennas for military radars We estimate the total market for RF MEMS to exceed US$ 1 billion in 2007, as featured in Figure 2. From 2002 to 2004, the market for RF MEMS will begin to grow, with activities focusing on prototypes and qualification processes. Full scale production is anticipated to start in In order to identify the most interesting market segments, we compared all potential applications with user benefits, Compound Semi & Microtechnology Unaxis Chip 27

28 Figure 3: Implementation potential for RF MEMS by application Compound Semi & Microtechnology Low Price acceptance High Out of reach Bluetooth No advantages High end applications expressed by technical advantages and price acceptance as shown in Figure 3. As a result, we distinguished three types of market segments: High End Applications: military, space and instrumentation applications are ready to use RF MEMS. The main drivers are the significantly better technical performances and reliability compared to existing techniques. Market volumes are small in comparison with mobile telephony, however, companies are prepared to pay higher prices for components if technical performances are proven. Volume Drivers: The second group includes industrial and consumer applications, interested in performance and functionality. Mobile telephony, GPS and WLAN plan to use RF MEMS. However, price targets have to be reached, as MEMS are in competition with existing techniques. These applications provide the large volume markets needed for efficient MEMS production. Base station Anti collision radars GPS WLAN Mobile phones RFID Technical advantages through RF MEMS Test equipment Satellites Military radars Missile systems Volume drivers Decisive advantages Out of reach: In some cases MEMS could be used from a technical point of view. However, the use of MEMS is out of reach, as prices are very low and there is no need for increased performance. This is the case for personal area networks, such as Bluetooth, where RF MEMS do not offer any particular advantages. Challenges and key factors for success RF MEMS devices offer a number of advantages over conventional components, however, certain issues must be resolved prior to their acceptance as viable alternatives to the traditional components currently in use. Challenges which need to be resolved include the following: Proven reliability: this is a major issue. Some MEMS switches stand 20 billion cycles, however, very little is known on ageing of materials in the micron range. Thus, it is difficult to carry out accelerated aging test. Unresolved technical problems include stiction of movable parts in tunable capacitors and switches. Packaging: a key issue, as it impacts long time reliability, performance and price of RF MEMS. For mass production, wafer level packaging emerges as the most promising solution, as compared to discrete packaging indicating the price of RF MEMS can be halved. Increased activity in organizations such as APiA and its members, including Unaxis Semiconductors, will help to drive completion. Pricing: producing RF MEMS at an acceptable price is the most significant challenge for manufacturers. First, the market prices have to be known. While switches for mobile phones may be priced between 30 and 40 cents, and between US$ 15 to 30 for instrumentation. Second, future manufacturing costs have to be calculated. It may happen that target prices cannot be met. WTC has investigated the price acceptance by application and future retail prices. Business opportunities in RF MEMS The market potential of RF MEMS is extensive. Subsequently to micromachined accelerometers for airbags, it is the first time components which offer improved performance, miniaturization and integration are required in hundreds of millions of units. We anticipate, by 2007, communications applications, including mobile telephony, GPS and WLAN will hold the major part of the market. These markets will mainly be served by large IC and MEMS manufacturers. 28 Chip Unaxis

29 Hybrid versus monolithic integration Two approaches are being developed for the integration of RF MEMS components with ICs into RF functional modules: hybrid integration and monolithic integration. Which one will dominate the market? Hybrid integration is rather straightforward. It uses wire bonding or flip-chip and is well suited to small to medium volumes. Hybrid integration makes it possible to optimize the design and manufacturing of the MEMS independently of the IC. This is important because even if MEMS and ICs are similar with regards to batch fabrication or use of silicon, the processes are very different. For example: IC manufacturers are not familiar with sacrificial layers and the chemicals used to remove them in MEMS processes; while 12" wafers are coming for ICs, most MEMS are still manufactured on 4" or 6" wafers; some poly-silicon RF MEMS switches are manufactured at 1100 C whereas CMOS processes usually do not exceed 350 C. Monolithic integration reduces the number of interconnects. This results in smaller losses, increased reliability, and last but not least lower chip prices. As monolithic integration is much more complex than hybrid integration, it only makes sense for mass-produced products, where price pressure and high volumes justify the development of more complex processes. Above-IC integration of inductors and BAW resonators is a first step towards monolithic integration. However, the objective and the real challenge is the In-IC manufacturing, i.e., the manufacturing of MEMS in 100% CMOS-compatible lines. While BAW resonators are already manufactured in 90% CMOS-compatible lines, RF MEMS with a higher number of mask-like switches or tunable capacitors still need dedicated lines. The full manufacturing compatibility of MEMS and ICs is a tough challenge for MEMS manufacturers as well as for equipment and materials suppliers, but it is key to meeting the extremely low price requirements from the RF MEMS killer application mobile phones. Major RF MEMS players such as STMicroelectronics, the IMEC and several Taiwanese foundries are actively working at finding a solution. Dr. Henning Wicht is founder and president of WTC-Wicht Technology Consulting. Henning has been working in marketing of microsystem technology since He started working at Leti Grenoble and in 1996 he set up the CEA German Office. In 2000, WTC-Wicht Technologie Consulting was created, specializing in services for companies with high tech products in microsystems and electronics. He is co-author of the NEXUS Market report and coordinator of the NEXUS User-Supplier Club MEMS packaging. Within SEMI he is member of the SEMI International MEMS Industry Forum and guides the technical program. Henning Wicht received a Diploma in Industrial Engineering at TH Darmstadt in The subject of his PhD work was the evolution of the microsystems industry. It was published as a book in Jérémie Bouchaud is a senior analyst at WTC for microsystems products and markets. He graduated from the Technical University of Applied Sciences in Munich and received a diploma as Marketing Engineer at the Business School of Grenoble. He has analyzed markets for high technology products since 1997 at the German Office of CEA-Leti and joined WTC as founding member in Compound Semi & Microtechnology However, medium-volume, higherpriced applications, such as automotive radars, base stations and instrumentation are very promising for smaller size companies and start-ups. Again, development and procurement programs for space and military applications provide interesting niches for small and medium size companies. Indeed, the market for RF MEMS is not only one of the most significant emerging MEMS markets in terms of size, it is also open to all MEMS players from the small start-up to the international IC manufacturer. For more information please contact notker.kling@unaxis.com Unaxis Chip 29

30 Compound Semi & Microtechnology VCSELs to Revolutionize Fibre Optic Communications Characterization of GaAs/AlGaAs non-selective ICP etch process for VCSEL (Vertical Cavity Surface Emitting Laser) applications Compound Semi & Microtechnology Figure 1: Simplified VCSEL cross section Surface-emitted beam in a circular narrow cone Isolation M. W. DeVre, Y. S. Lee, B. H. Reelfs, R. J. Westerman, Unaxis Semiconductors Introduction A VCSEL is a specialized laser diode that promises to revolutionize fiber optic communications by improving device efficiency and increasing data speed. Representing some of the latest technology in laser design, VCSELs have gained much attention in the photonic devices field due to their high power conversion efficiency at low operating currents [1]. While similar in operating principle to conventional diode lasers, where the light emerges from the edges of the device through mechanically cleaved surfaces, VCSELs are unique in that the P-type multilayer DBR (Distributed Bragg Reflector) Active region N-type multilayer DBR reflecting mirror surfaces (called DBR Distributed Bragg Reflectors) are stacked vertically, with the light emerging normal to the substrate surface. The light emission is in the shape of a circular beam, much more efficient for coupling to fiber optics than the elliptically shaped beam of the edge emitting lasers. A simplified schematic of a VCSEL is illustrated in Figure 1. Typically, the mirror stacks consist of alternating layers of doped III-V compound semiconductor materials such as GaAs and Al xga 1 xas. VCSEL device fabrication requires a process which nonselectively etches through these epitaxial layers with smooth feature walls stopping on the specific layer in the active region. Controllable etch rates near 1 µm/min and vertical feature profiles are necessary to meet these requirements. GaAs/Al xga 1 xas non-selective etching using RIE, ICP and ECR reactors has been studied in the past; SiCl 4, BCl 3, SiCl 4/Cl 2 and BCl 3/Cl 2/Ar plasmas have historically been the choices for achieving equal-rate or near equal-rate etch for GaAs/Al xga 1 xas layers [2]. However, very few papers have reported the utilization of high density plasma for VCSEL applications. In addition, implementation of an etch process monitoring technique is becoming increasingly important in the manufacturing environment [3]. In the following pages, we describe an ICPbased non-selective GaAs/Al xga 1 xas etch process for the fabrication of VCSEL micro-laser devices. The process space is characterized using designed experiments (DOE). Endpoint detection techniques including laser reflectance and Optical Emission Spectroscopy (OES) were also evaluated in this work. Experimental All experimental work was performed with Unaxis Semiconductors inductively coupled high-density plasma technology on a platform equipped with electrostatic clamping and He backside cooling. On this system, a high-density plasma is generated by a 2 MHz coil while the ion energy is controlled by a MHz RF biased cathode. Gas flow rates are controlled by mass flow controllers. The substrate was set at room temperature and controlled by backside He cooling. The Unaxis ICP system was also equipped with two endpoint systems including laser reflectance and Unaxis Spectraworks optical emission spectrometer. The (SOFIE Instruments S.A. Inc.) laser reflectance system consists of a polarized nm He-Ne laser head, CCD detector and video camera for laser spot positioning. The Unaxis Spectraworks OES system has a spectral range of nm with a resolution of 1 nm. The plasma emission is coupled to the spectrometer through a sapphire reactor viewport and a silica optical fiber. Results and discussion Prior to the DOE, a number of preliminary experiments were conducted to independently examine the GaAs and AlGaAs etch rates. Figure 2 shows similar etch rates for GaAs and AlGaAs over a 0 50% Cl 2 in a BCl 3/Cl 2 mixture. Later experiments confirmed the etch rates of the alternating layers in the 30 Chip Unaxis

31 Figure 2: The etch rates of GaAs and AIGaAs as the function of the %CI 2 in BCI 3/CI 2 Figure 3: Contour plot of the GaAs/AIGaAs etch rate response surface as a function of pressure and CI 2% GaAs AIGaAs Etch Rate [µm/min] Etch rate [µm/min] % CI2 [relative] % CI2 VCSEL devices were in good agreement with the etch rates of the individual films. Based on these results a series of designed experiments were performed on VCSEL device structures. DOE results The analyzed DOE response for the composite GaAs/AlGaAs stack etch rate is illustrated in Figure 3. Consistent with a chemically driven etch mechanism, the GaAs/AlGaAs composite etch rate increases with increased chamber pressure and Cl 2 percentage. This suggests that the generation of Cl radicals is the key factor determining the etch rate of GaAs/AlGaAs. Furthermore, since the GaAs/AlGaAs etch rate is independent of both the RF bias and ICP powers over the range of parameters tested, this suggests the process is reactant-limited. Based on the DOE analysis, the mask (silicon nitride) etch rates were mainly controlled by Cl 2% and weakly affected by RF bias power. High Cl 2% and RF bias powers tended to increase SiN x etch rates. The GaAs/AlGaAs:SiN x etch selectivity was found to be a function of both Cl 2% and pressure with high Cl 2 percentages significantly improving the etch selectivity due to a strongly enhanced GaAs/AlGaAs etch rate. The DOE analysis also showed that Cl 2% is the only parameter having a significant effect on the profile. High Cl 2% tends to result in re-entrant (undercut) feature profiles, while high BCl 3% lead to positively tapered (sloped) profiles. The DOE results did not show a significant parameter dependence on the non-uniformity over the range of parameters tested. All cells within the Pressure [relative] designed experiment showed etch rate uniformities well below ± 3% (Range /(2 Mean method)). Mask effect The initial mask properties such as profile and edge roughness had a profound effect on the etched feature profiles and sidewall morphology. The magnitude of the effect depends primarily on the etch selectivity, which in turn is a function of the process conditions. A positively sloped etched profile can be achieved through the use of a sloped mask profile and lowering selectivity of the stack material to the mask (driving the mask profile into the etched feature through mask erosion). For applications requiring vertical feature profiles, it is preferable to utilize a hard mask such as silicon nitride or silicon dioxide. Selectivities to these materials Compound Semi & Microtechnology Unaxis Chip 31

32 can be up to 4 times higher compared to photoresist mask materials. Figure 4 demonstrates the etched results of applying the optimized process on a nitride masked AlGaAs based VCSEL stack structure. As is apparent from Figure 4, a highly anisotropic profile was obtained through the use of nearly vertical mask combined with highly selective process conditions. Figure 6: OES intensity as a function of etch time Compound Semi & Microtechnology Figure 4: SEM photograph of VCSELs structure after etching with the optimized process; a vertical profile is observed. Figure 5: Laser reflectivity as a function of etch time Endpoint detection In this work, two primary types of endpoint systems were employed to examine the feasibility of monitoring the process: laser reflectance and optical emission spectroscopy (OES). Figure 5 shows an example of a laser reflectance trace of a VCSEL etch process. The etch depth is monitored by counting the reflectance peaks. Each peak represents etching through a GaAs/AlGaAs mirror pair. The OES was used to monitor the progress of the etch in the stack by looking at the Ga emission line from the plasma. An OES signature for the VCSEL etch process is shown in Figure 6. The emission signal alternates between maxima and minima, with the maximum corresponding to etching a GaAs layer and the minimum corresponding to etching the AlGaAs layer. The peaks in the OES signature match the peaks observed using the laser CCD system. Once the base region is reached, no more variation in the signal is seen, and end-point is easily detected. Conclusions A systematic investigation of a dry etch process for GaAs/Al xga 1 xas using a BCl 3/Cl 2 chemistry in a high density plasma has been performed. GaAs/AlGaAs etch rates ranged from approximately 0.25 to 2.5 µm/min. The DOE results show the composite GaAs/AlGaAs etch rate is a strong function of Cl 2/BCl 3 ratio and pressure. The etch rates of GaAs and AlGaAs obtained with Cl 2% varying from 20% to 50% were nearly identical. The mask (SiN x) etch rate was mainly controlled by Cl 2% and weakly affected by RF bias power. Cl 2/BCl 3 percentage and pressure were factors which influenced the stack:mask etch selectivity. Etch rate uniformity well under ± 3% (Range / (2 Mean)) was obtained over all etch conditions. High Cl 2% tended to result in re-entrant etched profiles; while high BCl 3% lead to positively tapered profiles. We are able to etch the stack GaAs/AlGaAs with equal etch rate and excellent uniformity. Laser reflectance has been demonstrated as a powerful tool to determine the etch depth during processing, while the success of utilizing OES as an endpoint technique was found to be a function of exposed area and will strongly depend on the individual application. References 1 Choquette K. D. and Hou H. Q Proc. IEEE Agarwala S., King O., Horst S., Wilson R., Stone D. and Dagenais M. 1999, J. Vac. Sci. Technol. A 17(1) Johnson D., Westerman R., DeVre M., Lee Y. and Sasserath J. 2000/2001, Compound Semiconductor 6(9) For more information please contact mike.devre@unaxis.com 32 Chip Unaxis

33 Unaxis Semiconductors Unaxis Insights Around the Globe Served Market Segments Advanced Silicon - Silicon Processes (CMOS and BICMOS Multilevel Metallization, Ultra-Thin Wafer Backside Metallization) - SiGe Applications - Photomask Process Technologies Deposition PVD PECVD UHV-CVD LEPECVD Semiconductors Advanced Packaging - Flip Chip UBM (Underbump Metallization) - Wafer Level CSP (Chip Scale Package) - Re-Routing - Integrated Passives Customer Support &Training Etching RIE HDP ICP Compound Semi & Microtechnology - GaAs, InP, InGaAs - Photonic Devices (Planar Optics) - MEMS, MOEMS & Nanotechnology - SAW, BAW - GMR (Magnetic Sensors) Supporting Processes RTP LEPC Good, Better, 10 BEST Marion Turner, U.S. Marketing Communications Manager Unaxis Semiconductors For the fourth consecutive year, Unaxis Semiconductors has been awarded a place among the 10 BEST semiconductor equipment suppliers. Lynn Ochs, Sales and Market Manager North America, (left) and Ralf Kuhlmann, International Sales and Marketing Manager, are proud of the achievement and look forward to an even better position next year. Wafer processing equipment (Small suppliers based on revenue) Rank Company Overall rating 1 Tegal Corporation SUSS Micro Tec Matrix Integrated Systems AIXTRON AG SEZ Group Unaxis Semiconductors Ultratech Stepper, Inc EV Group Hitachi Kokusai Electric Inc Mattson Technology, Inc Awards do matter! Rather than just gathering dust on the wall they identify a company s position among peers, encourage positive competition, provide a benchmark for prospective customers and are a major motivation for everyone on the team. We are especially proud to receive the VSLI 10 BEST award, because it is awarded by our customers. It honors all our employees, their hard work and commitment to excellence. This year, Unaxis Semiconductors received particularly high scores in the areas of Quality of results Field engineering support Product performance Commitment to meeting customers needs The survey was carried out by VLSI, who was among decision makers in the semiconductor industry ranking Unaxis in 6 th place in the category of Small What is the VLSI 10 BEST Award? The VLSI 10 BEST Award is presented annually by VLSI Research Inc to chip making equipment suppliers. It is the industry s principal indicator of how well equipment manufacturers perform in meeting their customers needs. The VLSI Research Customer Satisfaction Survey is not just about customer service, but about the level of technical support and product quality provided. Seven different categories are tested: Small Suppliers of Wafer Processing Equipment; Large Suppliers of Wafer Processing Equipment; Assembly Equipment; Process Diagnostics Equipment; Test and Material Handling Equipment; Large Suppliers of Chip Making Equipment; and Focused Suppliers of Chip Making Equipment. In 2003, VLSI Research received over 2,100 completed surveys returned from semiconductor equipment users around the world to determine the rankings. Survey respondents are asked to rate suppliers in thirteen categories on a 10-point scale. These thirteen categories include seven measures of equipment performance and six measures of customer service. The performance measures are cost of ownership, uptime, software, build quality, usable throughput, quality of results and product performance. The six customer service categories are process support, field engineering support, spares support, support after sales, technical leadership, and vendor s overall commitment. Suppliers of Wafer Processing Equipment moving up two places since last year. When we last reported on the 10 BEST Award in Chip 7, we wrote about our plans for ISO certification at the St.Petersburg site. This major goal has now been achieved (see article page 2), as well as a new Customer Complaint Management System (see page 3). We are looking forward to next year s challenge, and hope to improve on our current position. We are honored and proud to see the effects of our global account management already starting to pay off. This award is an incentive for us to proceed on this path. Ralf Kuhlmann, International Sales and Marketing Manager September 2003

34 North America Lynn Ochs Sales and Market Manager North America Greater China Benjamin Loh President Unaxis Greater China Korea In-Chul Cheon President Unaxis Korea Ltd. Worldwide Europe Kenneth T. Barry President,Unaxis Semiconductors David Hartel Customer Support Manager Mark Hashemi Sales and Market Manager Europe Dr. Gordon Shyu Sales and Market Manager Greater China Ha-Yong Kwak Sales & Service Manager Ralf Kuhlmann International Sales and Marketing Manager Jürg Steinmann Global Communications Manager Eastern North America Dan Pace Sales Engineer Sylvester Sebold Customer Support Manager Europe Tom Beens Sales and Service Manager North Europe* Taiwan Julien Wu Sales and Service Manager China William Zhu Sales and Service Manager Jason Park Sales Manager Kibom Kim Customer Support Manager Robert Van der Putten Global Customer Support Manager Peter Potter Sales Engineer Ralf Eichert Sales and Service Manager Central Europe** Daven Hsu Customer Support Manager Wingo Lu Customer Support Manager Daniel Kim Project Manager Asia Wolfgang Radloff Sales and Market Manager Asia Western North America Michael Helmes Sales and Service Manager Fiorenzo Slaviero Sales and Service Manager South Europe*** Jean Pierre Vercelletto Customer Support South Europe Jimmy Chen Sales Engineer Aidan Huang Sales Engineer David Wu Sales Engineer Sunday Huang Sales Assistant Pearl Kim Sales Assistant Marcel Kessler System Sales Support Greater China and Photomask Hermann Obermoser Customer Support Manager Dr. Gotthard Kudlek Sales Engineer Central Europe Bruce Lee Sales Engineer Japan Dr. Susumu Sawada President Unaxis Japan Co. Ltd. Peter Ignacio Sales Engineer Jean-Claude Le Vely Sales Manager France Joanne Teng Sales Assistant Hirohide Fujii Sales & Service Manager Singapore Todd Smith Sales Engineer Klaus Petersen Sales Engineer Central Europe Chih Heng Han President Unaxis Singapore Yukihide Kajimoto Customer Support Manager Osaka Jim Greenwell Sales Engineer Claude Dupuy Sales Engineer South Europe Swee Teck Ong Customer Support Manager Masatoshi Nakamura Customer Support Manager Tokyo * Benelux, Ireland, UK, Scandinavia ** Austria, Germany, Liechtenstein, Switzerland *** Israel, Spain and Portugal Boon Kwong Tan Sales Engineer Toshihide Haruki Sales Manager Our experienced team of R&D, sales and systems support specialists are there for you, wherever and whenever you may need them anywhere in the world. For updates please check Elaine Ng Sales Assistant Wataru Momose Sales Engineer Taeko Matsui Sales Assistant Digital Imagery copyright 2001 PhotoDisc, Inc.

35 North America Unaxis USA Inc., St.Petersburg Tel Fax Europe Unaxis Deutschland GmbH, Munich Tel Fax China Unaxis (Shanghai) Co., Ltd. Tel Fax Singapore Unaxis IT Pte. Ltd. Tel Fax Korea Unaxis Korea Ltd., Seoul Tel Fax Taiwan Unaxis Taiwan Ltd., Hsin Chu Tel Fax Japan Unaxis Japan Co. Ltd., Tokyo Tel Fax Other Markets Unaxis Balzers Ltd. sales.semi.tr@unaxis.com Tel Fax