Because Innovation Matters

Transcription

1 Because Innovation Matters Silicon Systems Group Toru Watanabe President, Applied Materials, Japan Semicon Japan November 30, 2010

2 Safe Harbor This presentation contains forward-looking statements, including those regarding the Applied Silicon Systems Group s performance, strategic positions, products and opportunities. These statements are subject to known and unknown risks and uncertainties that could cause actual results to differ materially from those expressed or implied by such statements, including but not limited to: the level of demand for Applied s products, which is subject to many factors, including: uncertain global economic and industry conditions, business and consumer spending, demand for electronic products and semiconductors, and customers utilization rates and new technology and capacity requirements; Applied s ability to (i) develop, deliver and support a broad range of products, expand its markets and develop new markets, (ii) align its cost structure with business conditions, (iii) plan and manage its resources and production capability, (iv) implement initiatives that enhance global operations and efficiencies, (v) maintain effective internal controls and procedures, (vi) obtain and protect intellectual property rights in key technologies, and (vii) attract, motivate and retain key employees; risks related to legal proceedings and claims; and other risks described in Applied s SEC filings. All forward-looking statements are based on management s estimates, projections and assumptions as of November 30, 2010, and Applied undertakes no obligation to update any forward-looking statements..

3 Silicon Systems Group Overview #1 in the WFE and advanced packaging markets In 2010, expect increased market share in each SSG business In 2011, expect to grow WFE market share for the 3 rd consecutive year Growth fueled by new product innovations aligned to technology inflections Source: Gartner, April

4 Innovations Enable Inflections ADVANCED PATTERNING WAFER-LEVEL PACKAGING TRANSISTOR INTERCONNECT Centris Etch Tetra X Silvia Etch Eterna FCVD Aera3 Avila CVD Avenir PVD/ALD Mesa Etch InVia CVD Siconi for Epi Centinel PVD UVision 4 Brightfield Raider-S ECD Astra DSA Anneal Reflexion GT CMP Accelerating innovations 15 new products in 15 months 4

5 Applied Materials Conductor Etch Innovations Ellie Yieh VP and GM, Etch Business Unit Semicon Japan November 30, 2010

6 Conductor Etch is Fastest Growing Etch Segment Conductor etch ~ $1.6B market in 2010 New steps in advanced transistors, double patterning and advanced packaging driving growth Applied already leads in advanced DRAM transistor critical etch Source: Gartner, Sept

7 Innovations Enable Inflections ADVANCED PATTERNING WAFER-LEVEL PACKAGING TRANSISTOR INTERCONNECT Centris Etch Tetra X Silvia Etch Eterna FCVD Aera3 Avila CVD Avenir PVD/ALD Mesa Etch InVia CVD Siconi for Epi Centinel PVD UVision 4 Brightfield Raider-S ECD Astra DSA Anneal Reflexion GT CMP Accelerating innovations 15 new products in 15 months 7

8 Applied s Conductor Etch Competitive Position VERTICAL SCALING Leading in Advanced DRAM (BBL/BWL architectures) HORIZONTAL SCALING Expanding Positions in Double Patterning NAND, Foundry, Logic and DRAM Requires <1 % Depth Non-Uniformity Requires <1 nm, 3σ CD Non-Uniformity 8

9 Gap in Litho Roadmap is Etch Opportunity 10 Above Wavelength Near Wavelength Below Wavelength Double Patterning Resolution (µm) g-line λ=436nm i-line λ=365nm DUV λ=248nm Hard Mask Insertion 193 (dry) λ=193nm (immersion) λ=193nm F Year of Production Lithography Gap Hard masks and double patterning enable below-wavelength patterning Sources: 2010 ITRS Roadmap, Applied Materials 9

10 Adding up the CD Variation Logic / Foundry Double Patterning Scheme L 1 = First litho CD variation E 2 = First hard mask etch CD variation L 3 + L 4 = Second litho CD + overlay variation E 5 = Second hard mask etch CD variation Yield impacted by CD variation: (L 1, E 2, L 3, L 4, E 5 ) Tighter etch CD uniformity can give wider process window for litho 10

11 How Precise is the Etched Critical Dimension? Red Blood Cells Etched CD variation range of 0.8 nm: 10,000X smaller than a red blood cell diameter, matched over thousands of wafers 11

12 Patterning Etch Steps Growing +6 steps NAND 4X nm NAND 2X nm +10 steps Logic 45 nm Logic 22 nm +10 steps DRAM 4X nm DRAM 2X nm Source: Applied Materials estimate Added steps increase process cost for customers 12

13 Relentless Cost-per-Bit Reduction $ / MB F F Source: Gartner, Applied Materials Cost reduction is key for customers 13

14 Applied s Etch Leadership in Productivity and Technology Improved CD Control Traditional Platform Centris Platform Lower Cost-Per-Wafer (normalized) 30% lower cost-per-wafer with leading critical etch performance 14

15 Applied s Centris Platform: Performance Worth Repeating Combines industry-leading Mesa chambers with high-productivity Centris platform 15

16 Building a Productivity Powerhouse with Centris 6 Mesa Chambers Dual- Blade Robot En-Route Abatement Four- FOUP Interface Optimized Gas Panel

17 Seijo En-Route Abatement Doubles the Number of Etch Chambers 3 Etch Chambers Traditional Platform Centris Platform 6 Etch Chambers Abatement Chamber 4 process chambers total 2 Seijo Abatement Chambers 8 process chambers total

18 AdvantEdge Mesa Chamber: Angstrom-level Precise Etch Mesa Source <1nm CD Uniformity <1% Etch Depth Uniformity Pulsync Extending Silicon Etch Memory leadership 1 st ultra-flat uniformity ICP* etcher enabling 3xnm node Rapid adoption with >200 chambers in 9 months Source Bias Pulse Pulse * Inductively Coupled Plasma Advanced plasma control Microloading benefit 18

19 Mesa Source: Breakthrough Etch Rate Uniformity Traditional Mesa Limited Electrical Field Tunability Electrical Field Decoupled and Tunable Limited Uniformity Improved Uniformity Breakthrough Mesa source delivers ultra-flat etch rate map 19

20 Mesa Pulsync Mitigates Microloading Challenge: Bi-Modal Trench Depth Distribution with Spacer Double Patterning SEVERE LOADING No Pulsing MINIMAL LOADING With Pulsync Mesa s Pulsync technology minimizes micro-loading in etch depth SEM image used with customer permission 20

21 Centris Enables the Same CD Every Time 6 Mesa Chambers, Auto- Calibrated to Same Standard Central Reference Standards Auto- Calibration Management Software E3 software identifies excursions

22 Improved Process Parameter Repeatability via Auto-Calibration OLD CONTROL LIMIT Base Pressure NEW CONTROL LIMIT Ch A Ch B Ch C Ch D Ch E Ch F Autocalibration off Autocalibration on Time (days) 22 Patent Applied For

23 Centris Etch Matching of 4,000 Wafers 43.0 Post-Process CD (nm) Upper Spec Limit Lower Spec Limit Number of wafers Chamber matching demonstrated at 0.8nm range across 4,000 wafers 23

24 Device Yield Benefit from Tighter Controls Traditional Platform Centris Platform PRODUCT PERFORMANCE PROCESS PERFORMANCE Device Yield Device Yield 24

25 Capital Productivity Benefit for Customers NAND 2Xnm at 250K WSPM, One Etch Application 3 ETCH, 1 ABATEMENT PLATFORM 6 ETCH, 2 EN-ROUTE ABATEMENT PLATFORM Unique 8-chamber architecture enables best-in-class productivity

26 Green Benefits of Lower Facilitization Costs ~35% improvement in energy savings from standard etchers One Platform saves an Olympicsize swimming pool of water per year Lower CO 2 emissions per Platform: equivalent to taking 50 cars per year off the road Green benefits contribute one-third of cost-per-wafer savings Assumes SEMI S23 standard calculations 26

27 Applied s Conductor Etch Platforms are Well Positioned at Leading Customers AdvantEdge Chamber AdvantEdge Mesa Chamber Centris Platform >1500 chambers >200 chambers in first 9 months 5 customers; includes entry into 2 new customers 27

28 Applied s Centris Platform: Performance Worth Repeating Precise Intelligent Productive Tightest CD uniformity Tightest depth uniformity on each wafer Auto-calibrating Industry-leading at 30% lower cost-per-wafer 28

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