ON REMOVING REDUNDANCY IN SEQUENTIAL CIRCUITS

Transcription

1 ON REMOVING REDUNDANCY IN SEQUENTIAL CIRCUITS Kwang-Ting Cheng AT&T Bell Laboratories, Murray Hill,NJ 07Q74 ABSTRACT - A procedure of removing redundancy in large sequential circuits Is proposed. In this procedure, no global reset state is required and no state transition information is needed. A definition of sequential redundancy is first given. We show that if a fault is potentially undetectable (pundetectable), it is sequentially redundant. An algorithm of identifying p-undetectable faults is then described. For large circuits, we propose a practical procedure to identify a subset, called feedback-free sequential redundant faults, of redundant faults. In this procedure, a minimal set of signals is selected and assumed fully controllable and observable to convert the given circuit into a feedback-free model. Redundancies in the feedback-free circuit model are then identified and removed. This procedure could also eliminate redundant flip-flops. Experimental results show that our method SUCcessfully minimizes the signal count by about 8.4%, in average, on six large MCNC benchmark sequential circuits with up to 20K gates and 700 flip-flops. In some examples, up to 7.8% of the flip-flops is removed without changing the circuit s input/output behavior.. Introduction It is known that, in a combinational circuit, the undetectability of single-stuck-at faults is associated with redundancy in the logic network. The redundancy can be eliminated by simple rules after the undetectable fault is identified by a combinational circuit test generator. However. Abramovici and Breuer [l] have shown that redundancy and undetectability of stuck-at faults are no longer equivalent in sequential circuits. This is mainly due to the fact that some hedundant faults in sequential circuits that prevent the initialization of the circuit may be undetectable. Therefore, the redundancy in sequential circuits can not be identify by a sequential circuit test generator. It is pointed out in [2] that if a sequential circuit has a global reset state for both fault-free and faulty circuits, the absence of a test is equivalent to the existence of redundancy in the sequential network. However, in most large sequential circuits that consist of both datapath and control logic, the registers in datapath typically do not have a reset state. Besides, the approach of eliminating sequential redundancy proposed in [2] requires the knowledge of the state transition graph and, thus, can only be applied to finite state machines with limited number of flip-flops. There has been some previous work in the area of sequential logic optimization. A new kind of re-timing, called peripheral re-timing is proposed in [3] which allows logic optimization across latch boundaries. This technique is restricted to pure pipeline circuits which have equal number of flip-flops among all pathes between any input-output pair. Sequential don t cares are used in [4] to simplify the network and to remove redundancies. Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct commercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice is given that copying is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific permission. However, the complexity of computing the don t care conditions are considered very high. In this paper, we fist investigate the connection between redundancy and undetectability for sequential circuits without a global reset state. We show that if an undetectable fault is not potentidly detectable. it is a redundant fault. An algorithm for identifying potentially undetectable faults is then described. This algorithm is modified from a conventional sequential circuit test generation algorithm that is based on the time-frame expansion technique. A new logic value, U (unknown), is added to the commonly used 3-valued logic, 0. and X (don t cares), for identifying the potentially undetectable faults. Based on the modified test generator, an efficient redundancy removal procedure is also proped. Since the complexity of test generation for large sequential circuits is typically very high, it may not be possible to identify and remove all redundancies using the proposed algorithm due to the run time or/and memory limitation. It has been shown in [5] that the complexity of test generation for a feedback-free sequential circuit is similar to that for a combinational circuit. Therefore, the complexity of identifying sequential redundancy using our method in a feedback-free sequential circuit would be comparable to that of identifying combinational redundancy using a combinational circuit test generator. For a given sequential circuit having complex feedback structure, we select and cut a minimal set of signals to covert the given circuit into a feedback-free model by assuming these cut signals fully controllable and observable. Redundancy identification and removal is then performed on the feedback-free model. The cut signals are then connected back to obtain a more area-efficient as well as more testable version of the given circuit. This procedure can identify and remove more redundancies than the known combinational redundancy identification/removal method where every flip-flop is made fully controllable and observable. This is because the number of cut signals for constructing a feedback-free circuit model is usually much smaller than the total number of flip-flops in the circuits. Experiment results on six large MCNC benchmark sequential circuits [6] with up to 20K gate and 700 flip-flops show that our method can reduce the gate count and signal count, in average, by 6.7% and 8.4%. respectively. More interestingly, our procedure eliminates up to 7.8% of the flip-flops without changing their terminal behaviors. In the next section. the definition of sequential redundancy is given. In Sec. 3. we investigate the relationship between redundancy and undetectability in sequential circuits. A method of identifying potentially undetectable faults is given in Section 4. Section 5 deals with feedback-free sequential circuits. The redundancy identification and removal procedure for large circuits is described in Section 6. Preliminary experimental results are presented in Section Sequential Redundancy Definition: A fault is called sequentially redundant (sredundant) if the presence of the fault does not change the input/output behavior of the sequential circuits. We have to be very careful here about what inputloutput 64 28th ACM/IEEE Design Automation Conference@ 99 ACM /9/0006/064 $.50

2 behavior means. Since we don t assume a reset state, the circuits used in practice is fist applied by an initialization sequence that brings the circuit into a known state. The operation is then started from the known state. The output responses are ignored during the initialization phase since they are not predictable. Therefore, we say the presence of a fault does not change the /0 behavior of the circuit if, for any input sequence, the output responses of the faulty circuit are identical to that of the good circuit at those primary outputs whose expected responses are not unknown (U). If the expected response at a primary output is unknown, we do not care whether or not the fault-free and faulty machines responses are identical. 3. Identifying Sequentially Redundant Faults If no reset state is given, no method can identify the sequential redundancy by now. Some sequential circuit test generators were developed assuming a global reset state for both fault-free and faulty circuits is provided [7,8]. This class of test generators typically works well for controldominated circuits. However, most flip-flops in datapath do not have a reset line and, thus, have to assume an unknown (U) value before the application of vectors. There are two classes of sequential circuit test generation methods that deal with circuits without a reset state: timeframe expansion method and simulation-based method. The time-frame expansion approach [9,0 can identify the sequentially undetectable faults (defined below) while can not determine whether or not an identified undetectable fault is a redundant fault. The simulation-based approach Ill] can not identify the sequentially undetectable faults. Definition: A fault is called sequentially undetectable (sundetectable) if. assuming every flip-flop is in an unknown (U) value before the application of vectorsathere is no input sequence that can produce a fault effect (D or D) at any primary output in the presence of the fault. It has been shown in [l] that a s-undetectable fault is not necessary a s-redundant fault. In Fig., an example of s- undetectable but irredundant fault is given. Line C stuck-at- fault prevents the flip-flop from initialization. Since no input sequence can set the flip-flop in a binary value in the faulty machine, no input sequence can produce a D (i.e. the value in fault-free circuit is and in faulty circuit is 0, denoted as /0) or D (0/) at the primary output. This fault is not redundant. Fixing line C to constant completely changes the terminal behavior of the circuit. called potentially undetectable (p-undetectable) if it is s- undetectable and is not pdetectable. Theorem : If a fault is p-undetectable, it is s-redundant. Proof: With three possible values (0, and unknown U) at any signal, there will be nine possible combinations of fault-free and faulty circuits output responses. If a fault is s-undetectable. there will be no input sequence that can produce a 0/ or /0 combination of the fault-free and faulty responses at any primary output. The possible combinations of the fault-free and faulty output responses are U/U, U/O. U/l, O/U, l/u, 0/0 and /. If it isnot pdetectable either, the remaining possible combinations are U/ U, U/O, U/l, 0/0 and /. Since we would ignore the output response when expecting an unknown U at the output of the fault-ffee circuit, the combinations U0 and U/ are not wnsidered changing the terminal behavior. Thus, by definition, the fault is s-redundant. Q.E.D. This theorem gives the sufficient condition of sequential redundancy. In the next section, we will explain why this is not a necessary condition. 4. Identifying Potentially Undetectable Faults Most sequential test generation techniques use a 3-valued logic,, 0, X (don t cares). To handle circuits with busses or tristate gates, a 2 (high impedance) value is sometimes used to avoid generating vectors that cause bus conflicts. Since the 2 value is not related to the problem addressed in this section, it is excluded from the following discussion. Most test generators that can identify s-undetectable faults employ the time-frame expansion and reverse time processing techniques [2,3. These test generators start from the last time-frame and justify the required state in the flip-flops backwards. They completely avoid the forward fault propagation process. The backward justification process stops until the required values in the flip-flops are all don t cares (X). We can improve these technique to identify p-undetectable faults by introducing a new logic value, U (unknown) [4]. This would result in a 4-valued logic. 0,, X (don t care), and U (unknown). For a two-input AND gate, the singular cover in the 4-valued logic is given in Table. Table - Singular cover of a 2-input AND gate A s.al c 4 Fig. : An irredundant, but undetectable fault The undetectability of a sequentially irredundant fault is mainly due to the uninitializability of the faulty-circuit. These faults are typically potentially detectable. Definition: A fault is called potentially detectable (p detectable) if the fault is s-undetectable and, assuming every flip flop starts in an unknown (U) value, there exists an input sequence that produces the combination of the good and faulty output responses O/U or /U at some primary output. A fault is U U U U U U U To potentially detect a given fault, it requires a 0 or value in the good circuit and a U value in the faulty circuit at some prhary output We can apply the standard backward justification technique to justify the required values in both good and faulty circuits using the extended singular covers similar to the one given in Table. In this 4-valued logic algebra, the primary inputs only allow values of 0, and X while the flip-flops allow all 4 values. Therefore, if the backward justification process specifies a U value at a primary input, it would cause a conflict and should be backtracked. A U value specified in a pseudo primary input (flipflop) is allowed and should be further justified backwards. A test that potentially detects the given fault is found when the required value in all flip-flops are either X or U. A fault is reported p- undetectable if all choices are tried and failed. This is similar to Paper.I 65

3 determining a s-undetectable fault using a conventional test generator that employs a 3-valued logic. Logic Fig. 2: Limitation of 3-valued logic. Even with this modification, it may still not be possible to identify all s-redundant faults due to the following two reasons: () A s-redundant fault may be classified as a p-detectable one due to the limitation of the 3-valued (0,, x) or 4-valued (0., X, U) logic [5,6. Fig. 2 shows a simple example to illustrate this limitation. If the value in the flip-flop is U (or X). the output calculated by the 3-valued or 4-valued logic will be U (or x) while its real value is a constant 0 and is independent of the contents of the flip-flop. If this situation occurs in the faulty circuit, the test generator may report that there exists a sequence that produces a O/U (/U) at the primary output while the reality is that the response is 0/0 (/) all the time and the fault is redundant. This limitation of 3-valued (or 4-valued) logic in simulation can be resolved by symbolic simulation by assigning a symbolic variable to each flip-flop. However, for test generation, no simple solution can resolve this problem. This explains the reason why the condition given in Theorem is a sufficient but not necessary condition. Fig. 3 shows the set relationship of the s-undetectable, p detectable and s-redundant faults. As explained above, the intersection of s-redundant fault set and p-detectable fault set may not be empty. (2) The complexity of sequential test generation is. in general, very high. The complexity of determining the detectability is even higher. Theorem 2: For a feedback-free circuit, the fault-free circuit and the faulty circuit of any single-stuck-at fault are always initializable. Proof: We can levelize the flip-flops according to their distances to the primary inputs. The flip-flops connected from primary inputs either directly or through combinational logic are designated level. The flip-flops that are only fed by level flip-flops but not from primary inputs are level 2. And so on. The maximum level is the sequential depth of the circuits. For a feedback-free circuit, the sequential depth is finite. Level i flipflops can be initialized by any sequence of length i. Therefore, any feedback-free circuit of depth D can be fully initialized by any sequence of length D. The presence of a single-stuck-at fault in a feedback-free circuit will neither introduces feedbacks nor increases the depth (may decrease though) of the circuit. Thus, the faulty circuit can also be initialized by any sequences of length D. Q.E.D. Most p-undetectable faults are those faults that prevent the faulty circuit from initialization. Therefore. in a feedback-free circuit, most s-undetectable faults are s-redundant. We must caution the reader, however, that the fault-free and faulty circuits may be initialized by different sequences. A sequence, with length shorter than D where D is the sequential depth, that initializes the fault-free circuit may fail to initialize the faulty circuit. Therefore, the occurrence of O/U or /U at primary output is still possible for feedback-free circuits. Almost all sequential circuits contains cycles. A cyclic circuit is composed of a feedback-free subcircuit and a set of feedback lines as shown in Fig. 4. We can identify and remove redundancies in the feedback-free model by assuming these feedback lines fully controllable and observable during test generation. Notice that, different from the partial scan technique proposed in [7]. the selected lines can be the output signals of both logic gates and flip-flops. It is not necessary to be restricted to the input or output signals of the flip-flops. By selecting different sets of feedback signals. different feedback-free models can be constructed. The faults which are redundant with respect to the feedback-free model is called feedback-free redundant faults. Notice that a feedback-free redundant fault is a s-redundant fault. SR: s-redundant faults PD: p-detectable faults SR U PD: s-undetectable faults SR n PD: s-redundant but classified as p-detectable Fig. 3: s-undetectable. p-detectable and s-redundant faults. It is found recently [7] that the cycles (or feedbacks) in the sequential circuits are mainly responsible for the test generation complexity. In the absence of feedbacks, even large sequential depth causes no serious problem to the test generator. Therefore, to handle large circuits, we convert a given circuit into a feedback-free model and use ow modified test generator to identify and remove redundancy in its feedback-free model. 5. Feedback-free Sequential Circuits A feedback-free synchronous sequential circuit is defined as a circuit that contains no cycles in its circuit graph. The circuit graph is a directed graph (V, E) where vertices represent logic gates or flip-flops and an edge between vertex U and v means gate/flip-flop U fanouts to gate/flip-flop v. In addition to the low test generation complexity, the feedback-free circuits have another nice property: both good and faulty circuits are guaranteed initializable. Feedback lines Fig. 4: Feedback-free circuit model. Fig. 5 shows the relationship of s-undetectable. s- redundant, feedback-free redundant, and combinationally redundant (c-redundant) faults. As mentioned earlier, a s-redundant fault is s-undetectable but not vice versa. Thus, the s- undetectable fault set is a superset of the s-redundant fault set. A c-redundant fault is a fault that is redundant even assuming all flip-flops are fully controllable and observable. If a fault is c- redundant, it is redundant with respect to the original sequential circuit. Therefore, the s-redundant fault set is a superset of the c- redundant fault set. Similarly. it is a superset of the feedback-free redundant fault set. The number of signals that are assumed fully controllable and observable for the feedback-free model is I 66

4 typically much smaller than the total number of flip-flops in the circuit (this is the number of signals assumed fully accessable for identifying c-redundant faults), the size of the feedback-free redundant fault set is, in general, larger than that of the c- redundant fault set. However, depending on the selection of the feedback cut set, a c-redundant fault may not be a feedback-free redundant fault. If the assumed accessable signals are restricted to the flip-flops data input or data output signals, the feedbackfree redundant fault set will be a superset of the c-redundant fault set. For different selections of the feedback cut set, the set of the feedback-free redundant faults may be different as shown in the figure. Fig. 5: Set relationship of s-undetectable (SU), s-redundant (SR), feedback-free redundant w.r.t. two different selections of feedback cut set (FFR and FFR2) and c-redundant (CR) faults. 6. Redundancy Removal Based on the concept described in the previous sections. we proposed a procedure to identify and remove feedback-free redundancies in large circuits. This procedure consists of three major steps: () Cutting a set of signals and adding these signals in the primary input and primary output lists to construct a feedback-free circuit model. (2) Identifying and removing redundancies in the feedback-free circuit model. (3) Connecting the cut signals back. 6.. Identifying a Feedback Vertex Set We fiid a minimal set of signals for cutting. We model the circuit as a directed graph G = (VJ). A vertex vi represents a gate or a flip-flop and an edge (v;.vi ) exists from vertex vi to vertex vi when the output of gate/flip-flop i is connected to the input of gate/flip-flop j. The problem of removing a minimal set of vertices and their associated fanin and fanout edges to reduce the given graph to an acyclic one is known as thefeedback vertex set problem [8]. This problem is NP-complete and many heuristics have been proposed 9,20. We used the algorithm and program given in [20] to fiid the minimal feedback vertex set. Once the set is found, we convert the given circuit into a feedback-free one by making the following modification in the circuit: For each vertex i (corresponding to gate/flipflop gi) in the feedback vertex set, (I) specify gi s output as a primary output and disconnect it from its fanouts. (2) create a new signal as a primary input. This signal fanouts to gi s original fanouts. We would like to point out that the feedback-free model is different from the circuit model required for peripheral re-timing [3]. A circuit, to be processed for peripheral retiming, not only is feedback-free but also has equal number of flip-flops among all paths between any input-output pair. This type of circuit structure is also called ballonced Structure [2]. 6.2 Removing Redundancy in the Feedback-Free Model We first generate all collapsed single-stuck-at faults in the feedback-free model. A target fault is selected from the fault list and test generation is followed. If the test sequence is found, fault simulation is followed and the detected faults ike removed from the fault list. In fault simulation, the potential detection option is used. In other words, the faults that are potentially detected by the sequence are also removed from the fault list. If the fault is reported undetectable, we further examine whether it is p- undetectable. If it is p-undetectable. we simplify the network by fixing the signal to its stuck-at value and recursively eliminating the redundant lines, gates and flip-flops using the rules given is Table 2. Since this step may remove many signals in the network, the faults on those deleted signals are removed from the fault list. This procedure continues until the fault list becomes empty. A subset of the rules given in Table 2 has been given in 5. It is worth noting that one of the new rules is capable of elimiiating redundant flip-flops. The effect of applying these rules to remove the flip-flops is that it may change the responses at certain primary outputs from unknown (U) to a known (0 or ) value before the fault-free circuit is fully initialized. Since we ignore the output responses when expecting an unknown value, The modified network is considered having the same terminal behavior as the original circuit. Consider the redundant network given in Fig. 6(a). The output responses to any input sequence are U0 OOO... According to the simplification rule, the flip-flop is eliminated. The circuit becomes a trivial circuit with the output grounded. Its output responses become as shown in Fig. 6(b). Since we ignore the output response before the first vector is applied. their terminal behaviors are considered identical. Table 2 - Circuit sin case AND( ) input is constant OR(N0R) input is constant 0 AND(NAND) input is constant 0 OR(N0R) input is constant NOT input is constant O() Flip-flop input is constant 0() Gate has no fanout ification rules operation remove input. remove input. remove gate and its inputs. propagate constant O( ) to each of gate s fanout. remove gate and its inputs. propagate constant l(0) to each of gate s fanout. remove gate and its input. propagate constant l(0) to each of gate s fanout. remove flip-flop and its inputs. propagate constant l(0) to each of flip-flop s fanout. remove eate and its inwts. (8) (b) Fig. 6: Removing a redundant flip-flop. New redundant faults may be introduced after some redundancies have been removed. Consider two single-stuck-at faultfi and fz where fi is detectable and fz is redundant. If the double faultfifz is redundant, after removing the redundant single fault fi. faultf, will become redundant. Iffz is processed beforefi in the procedure described above, both redundancies will be 67

5 removed. However, Iff2 is processed afterfi, the final network will still be redundant. Therefore, to produce an irredundant feedback-free network, the above procedure has to be repeated until all redundant faults are removed. Our experiences shows that, in general, 2 to 4 iterations are needed. To avoid unnecessary test generation effort, we keep the test vectors generated in the previous iteration and use them for fault simulation at the beginning of each iteration to quickly remove most detectable faults from the fault list. This procedure, named MIRACLE-FFS, is summarized in Fig. 7. The algorithm for removing feedback-free redundancy*/ MIRACLE-FFS [ Identifying a feedback vertex set; Convert the circuit into a feedback-free one, called target-neflisc Modified-netlist = MIRACLE-SP(target-netlist); I while (modified-netlist!= target-netlist) [ target-netlist = modified-netlist; modified-netlist = Miracle-SP(target-netlist); Output the modified-netlist; * The single-pass redundancy removal subroutine */ vliracle_sp(target-netlist) r Generate single stuck-at fault list; Run fault simulation in potential detection mode using the vectors generated in the previous iteration, if exists; Remove detected and potentially detected faults from fault list; while(faut-list is not empty) [ Pick up a target fault from the fault list; Run test generation in solid detection mode; if (test is found) ( run fault simulation in potential detection mode; remove the detected and potentially detected faults from fault list; continue. else if (target fault is identified as an s-undetectable fault) ( run test generation in potential detection mode; if (target fault is identified as a p-undetectable fault) ( fix the corresponding signal to its stuck-at value; recursively modifying the circuit using the rules in Table 2; remove faults on the disappeared lies from the fault list; continue; ) /*else the fault is aborted*/ output the modified netlit. Fig. 7: The algorithm of MIRACLE-FFS. 7. Experimental Results We have implemented the MIRACLE-FFS algorithm in C language. The sequential circuit test generator STG3 3 has been modified and used for the identification faults. The system also relies on the program greedyll 20 for the selection the feedback vertex set. In our first experiment we compare the size of combinational redundant fault set and feedback-free redundant fault set on six large ISCAS benchmark examples. No redundancy removal is conducted in this experiment. Table 3 gives the number of gates, interconnect lines and flip-flops of these circuits. There exist many long inverter chains, which contribute a significant percentage of gate count, in these benchmark circuits. The gate count and line count after removing unnecessary inverters are also listed (under the column marked "rm-i"). The last column (#cut) shows the size of the feedback vertex set found by the program greedyll. Circuit s96 itself is a feedback-free circuit. Thus, its cut size is 0. no. of gates circuit orig.? rm io s I 529 circuit s96 s5378 s9234 s3207 ~5850 s35932 #redund. faults comb. feedback-free no. of lines #flip- #cut orig. I rm i flops 96 I t : Original benchmark circuits. o : After removing unnecessary inverters in long inverter chains. Table 4 shows the numbers of redundant faults in the combinational logic and in the feedback-free sequential model identified by the modified STG3. The CPU time on SUN4/260 for identifying these redundancies is also listed. It has been reported [22] that, in circuits s9234, s3207 and ~5850, over 87% of faults are undetectable. This is mainly due to the uninitializability of these machines. Most of the undetectable faults are not redundant. Their corresponding feedback-free circuit models are guamteed initializable for both fault-free and faulty circuits. For four of the six circuits, the size of the feedback-free redundant fault set is larger than that of the c-redundant fault set. They are exactly identical for circuit ~ redundant faults P sec. ( 4 6 ) Table 5 lists the percentage of reduction in gate count, line count and flip-flop count after running MIRACLE-C and MIRACLE-FFS. The input netlists to these programs are the ones that unnecessary inverters have been removed. MIRACLE-C is a combinational redundancy removal program which follows the MIRACLE-FFS procedure given in Fig. 7 except that all flip-flops are assumed fully accessable during test generation and redundancy identification. The average gate count and line count is reduced by 6.7% and 8.4% respectively after processed by MIRACLE-FFS. while is redunced only by 4.8% and 6.% after processed by MIRACLE-C. More interestingly, 4 out of 79 flip-flops in circuit s5378 are eliminated after 68

6 running MIRACLE-FFS. We verify the output netlist of MIRACLE-FFS by simulation. The sequence that detects all detectable stuck-at faults is used as the verification vectors. I circuit s96 s5378 s9234 ~3207 ~5850 ~35932 average t : MIRACLE-C o : MIRACLE-FFS Table 5 - Area reduction by MIRACLE II #G ate I #L me I #F id-flod reduced (%) reduced (%) reduied (%) Ct FFSo C FFS C FFS If the the size of the feedback vertex set is much smaller than the total number of flip-flops, as is the case of ~5378. removing redundancy in the feedback-free portion can usually achieve much more area reduction than only removing redundancy in the combinational logic. However, it is not guaranteed true, as is the case of ~5850. because it also depends on the circuit structure and which set of feedback signals are selected. These two techniques can be combined in practical application for optimization sequential circuits. All combinational redundancies are first removed by MIRACLE-C. Starting from the combinationally irredundant circuit, the MIRACLE-FFS procedure is followed. This combination may achieve a better logic optimization. 8. Conclusion The connection between logic minimization and test generation for sequential circuits without a global reset state is investigated. Redundancy and undetectability of a stuck-at fault are not equivalent in sequential circuits. We show that a potentially undetectable fault is a redundant fault. This result validates the use of an enhanced test generator, that is capable of determining potential undetectability, for identifying sequential redundancy. We have shown a practical procedure for removing redundancy in the feedback-free portion of large sequential circuits for minimizing logic as well as for improving testability. Results on six large MCNC benchmark sequential circuits show that our procedure can identify and remove more redundancies than the known combinational redundancy removal method. Besides, our method can also eliminate redundant flip-flops. Acknowledgements - The interesting discussions with Vishwani Agrawal, Wu-Tung Cheng, and Kurt Keutzer on sequential circuit testing are acknowledge. The author also wish to thank Dong H. Lee and Sudhakar Reddy for providing the greedyll program. REFERENCES. M. Abramovici and M. A. Breuer. On Redundancy and Fault Detection in Sequential Circuits, IEEE Trans. on Computers C-28, pp (November 979). 2. S. Devadas, H.-K. T. Ma, and A. R. Newton! Redundancies and Don t Cares in Sequential Logic Synthesis, J. Electronic Testing: Theory and Application (JEITA) -, pp (Feb. 990). 3. S. Malik, E. M. Sentovich, R. K. Brayton. and A. Sangiovanni-Vincentelli. Retiming and Resynthesis: Optimizing Sequential Networks with Combinational Techniques, Proc. Int l Workshop on Logic Synthesis (May 989). M. Damiani and G. De Micheli. Synchronous Logic Synthesis: Circuit Specifications and Optimization Algorithms, Proc. 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