A Design Language Based Approach

Transcription

1 A Design Language Based Approach to Test Sequence Generation Fredrick J. Hill University of Arizona Ben Huey University of Oklahoma Introduction There are two important advantages inherent in test sequence generation based on a design language description: () A design language description naturally partitions a digital network into a control section and a data section. These two sections need not be treated the same by search and simulation techniques. (2) The compact design language description can be analyzed to generate heuristic information to be used in guiding test generation searches. The first listed advantage means that the control state diagram can be searched exhaustively, while exercising only a small portion of the much larger number of data states. Those data states searched will be dependent on user-supplied heuristic information. This observation provided the basis for the program SCIRTSS (Sequential Circuit Test Search System), which will be discussed in the following sections of this paper. The second natural advantage of the design language description is of value to the user who must supply heuristic information to SCIRTSS. This feature is more difficult to incorporate directly in the SCIRTSS program itself. A first approach to doing this, together with some initial results, will be discussed in the latter portion of the paper. There have traditionally been three approaches to the determination of test sequences for clock mode sequential circuits. The first of these maps the circuit onto an analogous iterative combinational logic network'-3 to which test determination methods for such a network, typically the D-algorithm, are applied. The D-algorithm is in effect a tree search procedure, but it is a breadth-first search, and the depth of the tree is limited by the need to store a complete circuit description for each level of the tree. A second method relies on verification that the state table of the circuit under test is indeed the state table of the good circuit 4-8. Although this method makes use of what has been defined as the uncertainty tree, it has not been formulated as a heuristic tree search procedure. The first step of this method finds a sequence which will indicate whether or not the circuit under test has as many states as the good circuit and validates a transfer sequence to each of these states. The second step is to find a sequence which will verify that every transition in the state table is executed correctly. Because of the large number of transitions which must be checked and the very long test sequences which would necessarily result, this method has not been applied to the large sequential circuits usually encountered in practice. The third test generation method, which has been relied on heavily in practice, is based on simultaneous simulation of all single fault versions of the circuit for trial input sequences suggested by the user. To this, SCIRTSS adds two heuristic tree search procedures for automatically determining these trial sequences. By partitioning a circuit into its control and data portions as would be done in a design language formulation the amount of storage and computation within SCIRTSS is reduced considerably. The reader may observe that the overall organization of SCIRTSS quite closely resembles the transition checking portion of the state table verification method. The distinction is that SCIRTSS enunerates faulty networks rather than input-present state combinations. 28 COM PUTER

2 SCIRTSS The SCIRTSS program developed at the University of Arizona9l2 incorporates the single permanent fault assumnption and assumes that both the faulty network and the good network operate in the clock mode. A simplified block diagram of the SCIRTSS test generation system is given in Figure. Central to the system are the two directed search routines represented by blocks 2 and 3 of the block diagram. The sensitization search has the task of finding an input sequence which will cause a particular network fault to be driven into a flip-flop or to some circuit output. The propagation search must find an input sequence which will propagate a stored fault from its original position to a point where its effect is observable at the network output. The search techniques used are adaptations of those described by Nilsson in Reference 3. With the goal of reducing the search cost, the searches are conducted over control and user-specified data inputs only, and consider only one fault at a time. A number of heuristics have been developed for both sensitization and propagation. All are based on the simple expression Hn = Gn + w. Fn where Hn is the heuristic value of node n. The function F,, may be a function of any information available about node n as defined by the user. Gn is an integer equal to the length of the sequence from the starting node to node n, while co is a constant that determines the extent to which the search is to be directed by Fn. Also incorporated into SCIRTSS are a modified D-algorithm and an elemental simulator, which are necessary because an AHPL circuit has many potential realizations in hardware and the existence of faults may have different implications in the various implementations. These are depicted as blocks and 4 in Figure. If a fault is ever to cause malfunction, there must be some state of the machine for which either the outputs are in error or the next states of the good and faulty machine differ (i.e., the error moves into a register). If the set Qf untested faults and a circuit interconnecting list are given, a modified D-algorithm can find states for which the faults will cause erroneous next states or outputs. This D-algorithm treats the circuit as if it were combinational by considering its behavior for only one clock period. The test vectors returned by the D-algorithm are then easily converted into primary inputs and "present" states. At this point the test generation problem becomes one of finding an input sequence to move the machine to one of these present states. This is the fault sensitization mode of operation. The AHPL register transfer simulator can be used to simulate the behavior of the circuit when test vectors are applied. Inputs are selected heuristically and the response of the machine simulated with the AHPL simulator until the search for a sequence of input vectors to move the machine to one of the goal states is successful. In the process of suggesting input vectors and weighting the states being searched, the AHPL description again is quite useful. As a manageable example for demonstration of a fault sensitization search, let us consider a 3-bit processor with an embedded 8-word RAM. The processor whose data paths are depicted in Figure 2 is capable of responding to eight separate instructions depending on the contents of an instruction register IR. Faults which can only be driven into the memory are particularly d,ifficult to test, since output leads from the memory are not network or primary outputs. Only the accumulator and three control lines are primary outputs. -: June977 Figure. SCIRTSS flow diagram. Figure 2. Embedded RAM. 29

3 The following is an AHPL description of the processor (introductions to AHPL are available elsewhere.4,5) which conforms to the version given in Reference 5. One of four operations - input data, AND, complement, or swap with MD - will be performed on AC at step 2, depending on the two least significant bits of the instruction register IR, and IR2. The operations at the remaining steps are described by comments in quotation marks. Step 6 is a conditional transfer with MD clocked into only the word of, memory specified by the decoded address register. In step 4, BUSFN (M ;DCD (AR)) is a combinational logic function representing the static memory output as determined by the contents of AR. R3EGISTERS: AR(3), IR(3), MD(3), AC(3), M (8;3) INPUTS: IN(3), A(3), Z(3) OUTPUTS: AC(3), accept, input, out. AR A; IR - IN; accept = 'accept instruction and address" 2. - Ro A IR,,IARoiAR A A IR2, IRo AIR,AIR2) /(4, 5, 6) 3. AC - AC A (IR, A IR2) V "accumulator operation" (ACA MD) A (IR, ATR2) V MD A (IR, A IR2)V Z A (IR, AIR2); MD * (IR, A R2) -AC; input = IR, AIR2 4. MD -(MDI 2, MDo) A IR2 V "read or shift" BUSFN (M; DCD (AR)) A IR2 5. out = "output accumulator" 6. M DCD (AR) " - MD "write in memory" END Altogether there are six control flip-flops and 36 data flip-flops. SCIRTSS numbers the control flip-flops first as FF's -6. The data flip-flops are numbered next by the user as he supplies data for the elemental simulator in block 4 of Figure. Gate numbers are also assigned by the user beginning with n+ if the circuit contains n flip-flops. In this case flip-flop AR, is assigned number 7 with the remaining flip-flops of AR, IR, MD, and AC numbered in this order followed by the memory array. Suppose the fault to be detected is input 2 to OR gate 26 SAO. The circuit interconnection list is given to the D-algorithm with this fault specified. The D-algorithm returns the information that this fault causes FF 4 (which is MD2) to be erroneously at the next step if FF 32 =, FF 7-9 -, FF 2 =, and FF 4 =. This translates to M =, AR, IR =, and being at control state #4. If the initial state of the machine (or some current state) is known, the search begins. Suppose initially the circuit is in control state. SCIRTSS will search an expanding tree of control states until the above memory elements are driven to the indicated states. One sequence which might be determined by the SCIRTSS sensitization search is given in Table. (In the interest of space only the one element M4 of the memory array is shown in the table.) 3 Table. Sensitization sequence. CONTROL STATE A X IN AR IR MD AC MEMORY M2 Now the next state will show MD = 6 where 6 indicates a when a should occur and the effect of the fault is apparent in a register. Note that this was not a homing (or state initialization) process, since the initial state was specified. If the first state above had been completely unknown ( a circumstance which SCIRTSS permits), the homing sequence and sensitization sequence would have been the same. Register transfer simulation requires that a fault has caused the circuit contents of a register to be in error before one can begin to simulate the faulty behavior. This is equivalent to requiring that the good and- faulty machines be in different states. If this requirement is satisfied, SCIRTSS enters fault propagation mode. In this mode, the objective is to extend the effect of the fault (i.e., the error) to a primary output. Again, inputs are selected heuristically and the machine is simulated in a search of the control state graph until a sequence of input vectors which will move the error to the output is found (or a user-specified number of unsuccessful attempts is reached). One such propagation sequence which might be found by SCIRTSS is given in Table 2. C. S. 2 3 Table 2. Propagation sequence. A X IN AR IR MD AC After such a sequence is found, it must be verified using an elemental simulator. This differs from the AHPL search simulator in several respects: () The effect of using the faulty gate to perform register transfers in propagating the fault is only approximated in the AHPL simulator. (2) The AHPL simulator uses a single machine and each element (variable) may be,, 6 ( should be ), 6 ( should be ), or X (unknown). The elemental simulator permits each variable to be only or or X for a given machine, but simultaneously simulates the good machine M, and, for each undetected fault fi, a faulty machine Mfi. (3) The AHPL simulator is about 25 times faster. Otherwise the trial and error searching required to generate test sequences would be prohibitively expensive. For the sample shown above, the sequence is good, since the fault did not affect the transfer AC *- MD, and this is verified by the elemental simulator. The elemental simulator is useful for more than just verification. SCIRTSS is designed to attempt to find tests simultaneously only for small sets of -5 faults. In the example only one fault was being considered. However, the elemental simulator compares the outputs for all Mf. in the total fault set with M at every step, as the test sequence is verified. Whenever the outputs differ from the good, the faults associated with those machines are listed as being tested at that step and are deleted from the set of faults for future consideration. Next, SCIRTSS checks the states of the good and faulty machines remaining for faults now stored in flipflops as a result of the input sequences just applied. If new faults are stored, the program continues in fault propagation mode. Eventually, there is a point at which the set of untested faults is still not empty, but none of the remaining faults have resulted in an error occurring in a register. (That is, with the input vector sequence thus far the good and remaining faulty machines exhibit identical present states and the outputs have always been the same.) The register transfer simulator at this point is not useful for propagating faults to an output,- and SCIRTSS must reenter sensitization mode. COMPUTER

4 Input vector generation using branching expressions No mention has been made up to this point about how the input vectors themselves are generated. This procedure is aided by the design language description in two separate ways. The first procedure is based on the partition between control and data portions of a circuit. This partition is implicit in AHPL. In SCIRTSS the inputs required to make every possible branch from the present control state to all the next control states partially dictate the input vector at each step of the search process.'6 For example, if I is a 4-bit input vector, the AHPL control branch statement 2. --, (Io /\ I,, IO A I,) I (4,6) will cause the input vectors OOXX and XX to be applied wherever the present state of the machine includes being in control state 2. Where the XX's occur the input values may be randomly generated. The control state branching functions may be Booleai functions both of register bits and inputs, and thest functions may be systematically converted to sum-of products form. The minterms are checked to see if the machine present state is correct for satisfying the brancd condition imposed by the minterm. If so, the remaining conditions are input values to be used in forming the input vector. Suppose the AHPL control state branching function is 2. -Io A/Ro V AR5 Application to seven circuits One trial circuit was deliberately designed so that only a small number of faults were likely to be detected by a random sequence. This bias was effected by using two chains of control states. In each chain, control must remain in one pair of states for nine clock periods before it can proceed to the next pair in the chain. The only alternative would be a return to the initial state. The average number of faults not tested as a function of the inputs applied for four -input random sequences is shown in Figure 3. Also shown in this figure is data for an input sequence found by SCIRTSS which tests for every fault after 635 inputs. This circuit was submitted to SCIRTSS a second time after a special heuristic function was added which could override the calculation of Eq. 8. The resulting sequence was similar, but the average time consumed by the sensitization search for each subsequence was reduced from 5.94 seconds to.59 seconds. RANDOM SEQUENCE and the register Ro, R =,. The branch to control state 3 can occur only if input, I, is set to. A branch to step 5 will occur if I, =. Because the control partition of large circuits is usually a small fraction of the total circuit, and because the input vector set needs to be generated only once for the entire circuit and stored, employing the nearly exhaustive approach on the control branch information is useful. Moreover, the input vectors thus suggested seem usually to be sufficient to successfully form fault propagation input sequences. Figure 3. Trial circuit. SCIRTSS SEQUENCE SEQUENCE LENGTH User inputs The user can influence the functioning of SCIRTSS in any or all of several ways as he chooses. He may assign a value to co, fixing the relative breadth and depth of the search procedure. He can weight four separate heuristic functions which are used in computing Fn. These include a predecessor node bias, a Boolean distance to goal node function, a value which increases as a given fault propagates into additional flip-flops, and a function which biases Hn in favor of previously unvisited control nodes. He can supply heuristic vectors which serve as intermediate goal nodes during the propagation search. The search may be further controlled through the specification -of a number of parameters such as time limits and node limits. When the program reaches certain of these limits the user can interact by changing parameters or supplying input subsequences. Perhaps the most powerful tool available to the user is the heuristic subroutine. This user-supplied Fortran subroutine will compute the heuristic functions at each node expansion and override the standard values of Fn. June 977 SCIRTSS has thus far been used to generate tests for several additional circuits of varying complexity. The characteristics of five of these circuits are briefly summarized in Table 3. Circuit 8 contains an embedded shift file. Circuits 6,, 4, and 5 are all buffers with a variety of control complexities. CIRCUIT NUMBER OF GATES NUMBER OF FLIP-FLOPS NUMBER OF INPUTS NUMBER OF OUTPUTS NUMBER OF FAULTS FAULTS FOUND SEQUENCE LENGTH CPU TIME IN SECONDS MEMORY WORDS (6 BIT) Table 3. Circuit characteristics % 99.6% % 99.% % K 77K 57K 55K 2K Circuit 4 contains a 4-bit counter, the 4 bits of which are ANDed together and used as a branch function in the control unit. Circuit 5 is similar with additional control states and a larger counter output interval. None of these 3

5 four circuits featured the extensive parallelism found in circuit 8. For all five circuits the number of network outputs is small relative to the overall circuit size. The tests find all detectable (because of built-in redundancies there are a few undetectable faults in each circuit) faults except one in circuit 8 and two in circuit 4. The untested fault in circuit 8 is associated with a gate whose fan out is so large that the D-Algorithm as then implemented could not sensitize a path to a flip-flop. The CPU time and the memory required by SCIRTSS to find a test for each circuit are also given in Table 3. Two circuits whose function and complexity closely approximate currently produced LSI products have also been submitted to SCIRTSS. One of these is a 4-bit processor which might be fabricated on a single LSI chip. Three such circuits together with an external memory could be connected together to form a 2-bit computer. Each individual 4-bit processor consists of 24 gates and 36 flip-flops. SCIRTSS was successful in finding a test for 99.4% of all single faults for this circuit. A second highly complex circuit for which SCIRTSS was able to find a test for 98.4% of the faults is a teaching machine controller. This circuit would be used in conjunction with a semi-random access memory"4 and a display unit to provide an interactive learning system. The controller design requires 54 flip-flops and 75 gates. Input vectors for sensitization search As the number of untested faults becomes small, the likelihood that an untested fault will be stored in a flip-flop following a propagation search decreases. Heuristic information to guide the sensitization search to these faults is difficult to obtain. Further there is usually some property of the circuit which has precluded visiting any of those states in propagation mode. Table 4 shows this clearly. Therefore, a good deal of attention has focused on using the design language description and the goal states together to give additional information to use in forming input vectors for sensitization mode. frequently use AND/OR graphs to show relationships between problems. The structure of sequential machines is logical, and the problem relationships defined by goal states and design language descriptions resolve into the AND and OR nodes of problem reduction graphs rather nicely. The AHPL syntax can be analyzed to indicate what these relationships are. Beginning with the problem of reaching the goal state(s), the problem reduction graph grows quickly. The process ends either when the problem nodes do not generate new successor nodes or the graph exceeds some arbitrarily specified size. If the inputs are considered in the same way the registers are, the problem reduction graph soon leads to cases where the sub-problem is to transfer specified values into an input vector. Recall the AHPL example problem in Figure 2. The D-algorithm returned as the goal state M =, AR =, IR2 =, and CS.4 To get M4 =, we must first get AR = and MD2 =. AR = requires getting to CS. first and setting the input vector A =. The probability of reaching CS. is very high, so we need not be concerned with how to get there. To set IR2 = also requires being in CS. and applying input IN2 =. Reaching CS.4 requires IR = OOX and CS.2, which is highly probable, and IR = OOX is formed by setting IN = OOX at CS.. The full problem reduction graph is shown in Figure 4. The input vectors suggested for use in forming the sensitization sequence do, not constitute the formation of the test sequence, but they do provide useful guidance for the sensitization search process. Table 4. Disparity between effectiveness of propagation mode and sensitization mode searches. CIRCUIT PERCENT OF SEARCH NODES USED IN FINAL SEQUENCE TIME USED SEARCHING PROP SENS PROP. 4.7 SEC SENS. 53 SEC Figure 4. Problem reduction graph for input generation. A goal state may be considered a composite of a control state and several register states. One goal state might be (CS.3, A:, X:), where CS.3 means control state #3, A is a 4-bit register containing and X is a 3-bit register with. The problem of reaching the goal state then can be resolved into the three simpler problems of transferring control into CS.3 and transferring the appropriate values into the registers. By referring to the register transfer expressions in the design language, the conditions necessary for loading the registers can be identified and other necessary register transfers can be added to the set of sub-problems. Problem-solving techniques 32 The complete set of inputs suggested for this example are all to be applied when in control state ; they are A:, IN:OOX, and IN:XX. Input vectors for the other control states may be randomly generated. SCIRTSS found a suboptimal but good 7-step sequence after 69 trial steps in the search for the fault above. Without the guidance derived from the AHPL description and using one randomly generated input at each state, the same search ran for 63 iterations and found a test sequence 63 steps long - clearly an unacceptable length. A breadthonly search would have required expanding 29 x nodes to find any good sequence. COMPUTER

6 Conclusion A design language circuit description can be a valuable source of information in automatic test generation. It provides a fast way to simulate circuit behavior in the input sequence formation and permits long test sequences to be formed. It also provides a great deal of significant information for use in generating the input vectors themselves. Research is continuing on finding the best ways to merge partially defined input vectors and weighting the problem reduction graphs to help in the search process that orders the input vectors into sequences. N Acknowledgment The authors are grateful to the National Science Foundation for support of this project under grant GK-29239K. References. H. Kubo, "A Procedure for Generating Test Sequences to Detect SequentialCircuit Failures," NEC Journal of Research and Development, Vol. 2, Oct. 968, pp W. G. Bouricius, E. P. Heish, G. R. Putsolu, J. P. Roth, P. R. Schneider, and C. J. Tan, "Algorithms for Detection of Faults in Logic Circuits," IEEE-TEC, Vol. C-2, Nov. 97, pp M. A. Breuer, "A Random and Algorithmic Technique for Fault Detection Test Generation for Sequential Circuits," IEEE-TEC, Vol. C-2, November 97, pp D. E. Farmer, "Algorithms for Designing Fault Detection Experiments for Sequential Machines," IEEE-TC, Vol. C-22, Feb. 973, pp F. C. Hennie, "Fault Detection Experiments for Sequential Circuits," Proc. 5th Symposium on Switching Theory and 3. N. J. Nilsson, Problem-Solving Methods in Artificial Intelligence, McGraw-Hill, New York, 97, pp F. J. Hill and G. R. Peterson, Digital Systems: Hardware Organization and Design, Wiley, New York, 973, pp F. J. Hill, "Introducing AHPL," Computer, December 974, pp Fredrick J. Hill is professor of electrical engineering at the University of Arizona. He is a co-author (with G. R. Peterson) of Introduction to Switching Theory and Logical Design and of Digital Systems: Hardware Organization and Design. A member of IEEE, he received his BS, MS, and PhD degrees in electrical engineering from the University of Utah. Huey is an assistant professor of electrical engineering at the University of Oklahoma, where his current research interests are in fault diagnosis, simulation of noisy channels, and computer design languages. A member of Eta Kappa Nu and the ACM, : he received the BS in mathematics from Harding College, and the MS and PhD degrees from the University of Arizona. Ben M. Logical Design, 964, pp Z. Kohavi and P. Lavalle, "Design of Diagnosable Sequential Machines," AFIPS Conf. Proc., 967 Spring Joint Comput. Conf., Vol. 3, pp Z. Kohavi and I. Kohavi, "Variable-Length Distinguishing Sequences and Their Application to the Design of FaultDetection Experiments," IEEE-TEC, Vol. C-7, Aug. 968, pp C. R. Kime, "An Organization for Checking Experiments on Sequential Circuits," IEEE-TEC, Vol. EC-5, Feb. 966, pp F. J. Hill, J. E. Belt, E. A. Carter, and B. M. Huey, "A Graph Search Approach to The Determination of Test Sequences for LSI Sequential Circuits," Proc. Seventh Asilomar Conf., 973, pp E. A. Carter, Fault Test Generation for Sequential Circuits Described in AHPL, PhD dissertation, University of Arizona, J. E. Belt, An Heuristic Approach to Test Sequence Generation for AHPL Described Synchronous Sequential Circuits, PhD dissertation, University of Arizona, B. M. Huey, Search Directing Heuristics for Sequential Circuit Test Search System (SCIRTSS), PhD dissertation, University of Arizona, 975. June 977 Reader Service Number 8 33