Chip-Level DFT: Some New, And Not So New, Challenges

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1 2004 Southwest DFT Symposium B A DFT Open Day Chip-Level DFT: Some New, And Not So New, Challenges Ben Bennetts, DFT Consultant Bennetts Associates, UK Tel: ben@dft.co.uk Slide 1 Agenda Functional versus Structural or or Functional plus Structural test Scan tests fail, but is is it it a reject? Internal scan protocols Testable core-based design: IEEE (P) Designing testable asynchronous sequential circuits Analog Mixed-Signal BIST techniques. Slide 2 Bennetts Associates,2004 Page 1

2 2004 Southwest DFT Symposium Defects In, Fault Models Out Defects that do not map to fault models D F E A Defects that F U map to E L fault models C T T S S Fault models that do not map to defects There are some defects that do not map to a simple fault model There are some fault models that do not map to a physical defect Determining these two sets is difficult!! Slide 3 B A Review of Test Objectives: Digital Functional Test Objective Conformance to Design Spec? Does it it do do what is is designed to to do, at at the right time? Functional versus Structural test? See ITC01, P16.1 (Motorola) ITC02, P16.3 (Intel) Did I I build it it correctly? Structural Test Objective Conformance to Build Spec? Slide 4 Bennetts Associates,2004 Page 2

3 2004 Southwest DFT Symposium Using Functional Patterns (ITC01, P16.1*) Functional patterns were drawn from the designer s knowledge of the device and then passed through a fault simulator (to assess stuck-at and at-speed coverage) and finally translated to a target tester. Technique was based on RTL code coverage plus formal verification patterns Motorola s conclusion: scan can replace functional if the stuck-at coverage is >98% and transition and path delay coverage is >80% * Ken Tumin et al., MMC2107 Microcontroller) Slide 5 Question 1 Will we ever figure out the right balance of structural and functional tests? Slide 6 Bennetts Associates,2004 Page 3

4 2004 Southwest DFT Symposium Agenda Functional versus Structural or or Functional plus Structural test Scan tests fail, but is is it it a reject? Internal scan protocols Testable core-based design: IEEE (P) Designing testable asynchronous sequential circuits Analog Mixed-Signal BIST techniques. Slide 7 Scan Chains: Unnatural Paths Open Open the the door door if if closed closed Open Open the the door door if if closing closing Do Do not not close close the the door door if if opening Close Close the the door. door. Ref: Rearick, ITC 2001, P Slide 8 Bennetts Associates,2004 Page 4

5 2004 Southwest DFT Symposium B A Garage Door Controller B = 0 B = L = 0 B = 1 or L = 1 Open 00 Opening 11 B = 1 B = 1 Not Allowed B = 1 Closing 01 Closed 10 L = 1 B = L = 0 Garage door open/close B (Button) starts a change L (Limit) stops the door movement B = 0 XY Slide 9 Garage Door: Circuit Implementation Scan Chain Lower D Y Clk Q Q Limit Button Slow-To-Fall fault D X Q N G Raise Clk Q Slide 10 Bennetts Associates,2004 Page 5

6 2004 Southwest DFT Symposium Nonsensical Test A Slow-To-Fall transition fault on node N requires the following sequence: {1,1} to {0,1} on {X, Y} This sequence never occurs naturally. Question: if this test fails, should the device be rejected? Functional false path B = 0 Up B = 1 Closing B = L = B = L = 0 B = 1 or L = 1 Opening 11 B = 1 Not Allowed B = 1 Down 10 L = 1 B = 0 Slide 11 Question 2 If If the chip does what it s supposed to do, do we care about non-functional defects? Slide 12 Bennetts Associates,2004 Page 6

7 2004 Southwest DFT Symposium Agenda Functional versus Structural or or Functional plus Structural test Scan tests fail, but is is it it a reject? Internal scan protocols Testable core-based design: IEEE (P) Designing testable asynchronous sequential circuits Analog Mixed-Signal BIST techniques. Slide 13 B A General Scenario for Applying Delay Tests PPIs PIs PPOs S T I M U L U S Circuit-Under-Test (Combinational Circuit) R E S P O N S E Load stimulus into input scan chain and update to the CUT POs Capture response from CUT into output scan chain and scan out Slide 14 Bennetts Associates,2004 Page 7

8 2004 Southwest DFT Symposium Applying Deterministic At-Speed Tests There are three major techniques but they have many different names Launch-On-Shift (aka Launch From Shift, Launch-Off-Last-Shift, Shift- Based Testing, Transition Shifting, Scan Shifting, Last-Shift Launch, System Clock launch, and Skewed Load Test) Enhanced Scan, aka Buffering The Flip-Flops Launch-On-Capture (aka Launch From Capture, Launch-Off-Capture, Double Capture Clock, Testing through the Functional Path, Two Sample, Functional Justification, Broad-Side Test, Clock Launch, Last Shift Launch, and System Launch) Help!! aka = also known as Slide 15 Launch-On-Shift Timing Diagram Launch Initialise Pattern, T1 Launch Propagate Pattern, T2 Timed Capture Response Clock Launch - 1 Launch Capture Scan Enable Scan Mode Functional Mode Beware: Timing Timing of of the the Scan_Enable signal signal relative relative to to the the timing timing of of the the capture capture clock clock and and the the set-up set-up and and hold hold times times for for the the capturing and and transmitting FFs, FFs, and and Timing Timing of of any any value value changes on on the the PIs PIs relative relative to to the the scan scan clock, clock, especially if if the the scan scan clock clock is is internally derived derived via via a (programmable) PLL PLL Slide 16 Bennetts Associates,2004 Page 8

9 2004 Southwest DFT Symposium Launch-On-Capture Solution (1) PIs Testing C1 for propagation delay faults. Assume Parallel Load (PL) into Reg1 T2 on PL Clock R e g 1 T1 T2 C1 POs R1 R2 R e g 2 Serial load T1 into Reg1/PIs Set PL values to T2 First capture pulse: Capture R1 into Reg2, Capture T2 into Reg1 Second capture pulse: Capture R2 (response to T2) into Reg2 and scan out T1 to C1 to R1 Set PIs to T2 values R1 into Reg2 T2 into Reg1 Clock Launch Capture1 Capture2 R2 into Reg2 Scan out R2 Scan Enable Scan Mode Functional Mode Slide 17 Launch-On-Capture Solution (2) PIs PIs Testing C1 for propagation delay faults PL R e g 0 T2* T2 R R T1 R1 e e S3 g g 1 T2 R2 2 C0 C1 Serial load T1 into Reg1 Serial load T2* into Reg0 (T2* becomes T2 at C0 output) First capture pulse: Capture R1 into Reg2, Capture T2 into Reg1 Clock POs POs Second capture pulse: Capture R2 (response to T2) into Reg2 and scan out. Clock T1 to C1 to R1 T2* to C0 to T2 R1 into Reg2 T2 into Reg1 Launch Capture1 Capture2 R2 into Reg2 Scan out Reg2 Scan Enable Scan Mode Functional Mode Slide 18 Bennetts Associates,2004 Page 9

10 2004 Southwest DFT Symposium Question 3 Is it it time to nail the definitions of protocols to support at-speed tests through scan chain? Slide 19 Agenda Functional versus Structural or or Functional plus Structural test Scan tests fail, but is is it it a reject? Internal scan protocols Testable core-based design: IEEE (P) Designing testable asynchronous sequential circuits Analog Mixed-Signal BIST techniques. Slide 20 Bennetts Associates,2004 Page 10

11 2004 Southwest DFT Symposium B A P1500 Scalable Architecture Source/Sink (Stimulus/Expected Response) On-chip User-Defined Test Test Access Access Mechanism (TAM) (TAM) (e.g. (e.g. Direct, Direct, Indirect Indirect via via mux, mux, System System Bus, Bus, Test Test Bus, Bus, etc) etc) TAM in TAM out TAM in TAM out TAM in TAM out F in WBR WBR WBR Core F in Core F in Core 1 2 n F out F out WIR WIR WSI WSO WSI WSO WSI Standard P1500 P1500 Wrapper Serial Serial Port Port Wrapper Controls WIR F out WSO SOC Slide 21 WBR Operating Modes: Normal TAM in TAM out CFI CFO WSI WBYPASS WIR WSO Control Normal Slide 22 Bennetts Associates,2004 Page 11

12 2004 Southwest DFT Symposium WBR Operating Modes: Inward Facing TAM in TAM out WSI WBYPASS WIR WSO Control Inward facing Slide 23 WBR Operating Modes: Outward Facing TAM in TAM out WSI WBYPASS WIR WSO Control Outward facing Slide 24 Bennetts Associates,2004 Page 12

13 2004 Southwest DFT Symposium WBR Operating Modes: Safe Mode TAM in TAM out WSI WBYPASS WIR WSO Control Safe (Non-Hazardous) Slide 25 P1500: Status Draft 0.8, ballot passed, mid-february Now responding to reviewer's comments Aim: to submit to IEEE SA end-q2 for final approval Slide 26 Bennetts Associates,2004 Page 13

14 2004 Southwest DFT Symposium Question 4 Who will be the first to (a) support IEEE 1500 and (b) implement IEEE 1500? Slide 27 Agenda Functional versus Structural or or Functional plus Structural test Scan tests fail, but is is it it a reject? Internal scan protocols Testable core-based design: IEEE (P) Designing testable asynchronous sequential circuits Analog Mixed-Signal BIST techniques. Slide 28 Bennetts Associates,2004 Page 14

15 2004 Southwest DFT Symposium Testing Asynchronous Logic Circuits - 1 Asynchronous logic, also known as clockless logic is notoriously difficult to test DFT guideline: Don t design asynchronous logic!! XXX device was not asynchronous but was similar from the point of view of test and testability issues. Domino logic with 200 micro-clock domains Therefore, useful to see if there have been any significant breakthroughs Short answer: no!! Slide 29 Testing Asynchronous Logic Circuits - 2 Three special issues of D&TC on asynchronous logic design Summer, 1994, six articles Two article comment briefly on test issues Spring, 1995, three articles No comment Nov-Dec, 2003, six articles No comment, and no response to my !! Conclusion: no significant breakthroughs Slide 30 Bennetts Associates,2004 Page 15

16 2004 Southwest DFT Symposium Question 5 Is testable asynchronous logic an unattainable goal? Slide 31 Agenda Functional versus Structural or or Functional plus Structural test Scan tests fail, but is is it it a reject? Internal scan protocols Testable core-based design: IEEE (P) Designing testable asynchronous sequential circuits Analog Mixed-Signal BIST techniques. Slide 32 Bennetts Associates,2004 Page 16

17 2004 Southwest DFT Symposium B A The Objectives of AMS-BIST Functional Test Objective Conformance to Design Spec? Does it it do do what is is designed to to do, at at the right time? Did I I build it it correctly? Structural Test Objective Conformance to Build Spec? Slide 33 Purpose of AMS-BIST The fundamental purpose of AMS-BIST is to perform a functional checkout (i.e. measurement of circuit specifications), not a structural checkout (i.e. targeted on specific manufacturing defects). Example: a PLL check will measure characteristics such as loop gain, lock range, lock time and jitter. Slide 34 Bennetts Associates,2004 Page 17

18 2004 Southwest DFT Symposium AMS-BIST Elements Stimulus Source Analog Analog waveform Σ- Σ- bit bit stream stream ** DSP-based Response Capture And And Compare DSP-based Histogram Histogram Processing RMS RMS calculation Self-Test Controller Mode Control Initialisation Response Sampling Response Analysis Pass/Fail Output * See D&TC, July-August 2002, p25 Slide 35 Summary of AMS-BIST Techniques - 1 Voltage-BIST (V-BIST): voltage-based analog scan register based on sample-and-hold tap-off points Wey, IEEE Trans Instrum & Meas, 1990, pp Current-BIST (I-BIST): current-based analog scan register based on current storage cells Wey, IEEE Trans Instrum & Meas, 1992, pp Mixed-Signal BIST (MS-BIST): similar to VBIST but uses a bus for signal I/O to digiatl scan chain, not sample-and-hold Wurtz, IEEE Trans Instrum & Meas, 1993, pp Shieh at al., IEEE Trans Computers, 1998, pp DC-BIST: matrix checksum approach based on summing a number of internal DC values which should produce a 0-volt output Chatterjee etal., IEEE D&TC, 1996, pp Slide 36 Bennetts Associates,2004 Page 18

19 2004 Southwest DFT Symposium Summary of AMS-BIST Techniques - 2 Analog Unified BIST (AU-BIST): BIST circuitry monitors the balance of common-mode signals, defect oriented Mir et al., JETTA, 1996, pp Hybrid BIST (H-BIST): digital BIST circuitry to test analog circuitry thru ADC/DAC conversion Ohletz, ETC, 1991, P12.2 Mixed Analog-Digital BIST (MAD-BIST): digital stimulus generator/response analyser using Σ- techniques Toner and Roberts, ITRC 1993, pp adc-bist (LogicVision): ramp stimulus with polynomial fitting to output to determine DC offset, gain, harmonic distortion from the coefficients Sunter & Nagi, ITC, 1997 Slide 37 Summary of AMS-BIST Techniques - 3 Histogram-based Analog BIST (HA-BIST) : collection of a number of samples and comparison with the histogram generated from a KGD Frisch & Almy, ITC, 1997 Partial BIST: reduced sampling technique, LSBs recorded for low-frequency stimulus De Vries et al., ETW, 1997 BISTmaxx (Opmaxx): based on deliberately causing oscillation in the CUT Arabi & Kaminska, ITC, 1997, pp With Acknowledgment to Andrew Richardson, Lancaster Univ. UK Slide 38 Bennetts Associates,2004 Page 19

20 2004 Southwest DFT Symposium AMS DFT: Conclusions AMS DFT has suffered because there is no simple fault model equivalent to the stuck-at model in digital DFT but is finally receiving attention AMS DFT cost justification is even more difficult than digital DFT: lack of metrics We now have low-cost PC-based tester solutions for digital DFT-enabled devices, but not yet for analog DFT-enabled devices As in any BIST environment, key questions are: Is Is there Who tests the tester? any any hope? If the tester fails, is the chip bad? Slide 39 Question 6 Will AMS BIST ever achieve the commercial status of digital BIST? Slide 40 Bennetts Associates,2004 Page 20

21 2004 Southwest DFT Symposium Summary Will Will we we ever ever figure figure out out the the right right balance balance of of structural structural and and functional functional tests? tests? If If the the chip chip does does what what it s it s supposed supposed to to do, do, do do we we care care about about non-functional non-functional defects? defects? Who Who will will be be the the first first to to (a) (a) support support IEEE IEEE and and (b) (b) implement implement IEEE IEEE 1500? 1500? And And there s there s more more but but I I only only had had minutes!! minutes!! Thanks Thanks Is Is it it time time to to nail nail the the definitions definitions of of protocols protocols to to support support at-speed at-speed tests tests through through scan scan chain? chain? Is Is testable testable asynchronous asynchronous logic logic an an unattainable unattainable goal? goal? Will Will AMS AMS BIST BIST ever ever achieve achieve the the commercial commercial status status of of digital digital BIST? BIST? Slide 41 Bennetts Associates,2004 Page 21

for Digital IC's Design-for-Test and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ

for Digital IC's Design-for-Test and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ Design-for-Test for Digital IC's and Embedded Core Systems Alfred L. Crouch Prentice Hall PTR Upper Saddle River, NJ 07458 www.phptr.com ISBN D-13-DflMfla7-l : Ml H Contents Preface Acknowledgments Introduction