SCIENTIFIC DATA SYSTEMS. Reference Manual

Transcription

1 SCENTFC DATA SYSTEMS Reference Manual

2 SOS 92 BASC NSTRUCTONS (CENTRAL PROCESSOR) Mnemnic Octal Cde Name Mnemnic Octal Cde Name LOAD/STORE BRANCH LDA A, T 64 Lad A BRU A, T 73 Branch Uncnditinally LDB A, T 24 Lad B BRC A, T 32 Branch, Clear nterrupt, and Lad Flag STA A, T 44 Stre A BRL A, T 33 Branch and Lad Flag STB A, T 04 Stre B BFF A, T 31 Branch n Flag False XMA A, T 74 Exchange Memry and A BFT A, T 71 Branch n Flag True XMB A, T 34 Exchange Memry and B BDA A, T 70 Branch n Decrementing A BAX A, T 30 Branch and Exchange A and B FLAG BRM A, T 77 Branch and Mark Place BMC A, T 37 Branch, Mark Place, and Clear Flag XMF A, T 17 Exchange Memry and F LDF A, T 57 Lad F SHFT SFT 0044 Set Flag True SFF 0042 Set Flag False CYA A, T 42 Cycle A NF 0046 nvert Flag CYB A, T 02 Cycle B CFA A, T 43 Cyc e Flag and A ARTHMETC CFB A, T 03 Cycle Flag and B CYD A, T 02 r 42 Cycle Duble ADA A, T 62 Add t A CFD A, T 43 Cycle Flag and Duble ADB A, T 22 Add t B CF A, T 03 Cycle Flag and Duble nverse ACA A, T 63 Add with Carry t A ACB A, T 23 Add with Carry t B CONTROL SUA A, T 60 Subtract t A SUB A, T 20 S ubtrac t t B EXU A, T 72 Execute SCA A, T 61 Subtract with Carry t A HLT 0041 r Halt SCB A, T 21 Subtract with Carry t B MPA A, T 76 Memry Plus A t Memry MPB A, T 36 Memry Plus B t Memry TRAP MPO A, T 16 Memry Plus One t Memry MPF A, T 56 Memry Plus Flag t Memry SCT 0061 Set Prgram-cntrlled Trap MUA A, T 13 Multiply A (Optinal) RCT 0060 Reset Prgram-cntrlled Trap MUB A, T 53 Multiply B (Optinal) TCT 0160 Test Prgram-cntrlled Trap DVA A, T 52 Divide AB (Optinal) DVB A, T 12 Divide BA (Optinal) BREAKPONT TESTS LOGCAL BPT Breakpint N. 1 Test BPT Breakpint N. 2 Test ANA A, T 65 AND t A BPT Breakpint N. 3 Test ANB A, T 25 AND t B BPT Breakpint N. 4 Test ORA A, T 67 OR t A ORB A, T 27 OR t B NTERRUPTS EOA A, T 66 Exclusive OR t A EOB A, T 26 Exclusive OR t B ER 0051 Enab e nterrupt MAA A, T 75 Memry AND A t Memry DR 0050 D i sab e nterrupt MAB A, T 35 Memry AND B t Memry let 0150 nterrupt Enabled Test AR Arm nterrupts COMPARSON COA A, T 45 Cmpare Ones with A COB A, T 05 Cmpare Ones with B CMA A, T 47 Cmpare Magnitude f Memry with A CMB A, T 07 Cmpare Magnitude f Memry with B CEA A, T 46 Cmpare Memry Equa t A CEB A, T 06 Cmpare Memry Equal t B Legend: A = address; * A = indirect address; =A = immediate address; T = index tag

3 SOS 92 COMPUTER REFERENCE MANUAL June 1965 Ell' -\!J SCENTFC DATA SYSTEMS/1649 Seventeenth Street/Santa Mnica, Cal Scientific Dt Systems, nc. Printed in U.S.A.

4 REVSONS Th is pu bl icatin, C, supersedes the SDS 92 Cmputer Reference Manual, B. Revisins, crrectins, and clarificatins t the previus editin are indicated by a vertical ine in the left r right marg in f the page. ii

5 CONTENTS GENERAL DESCRPTON APPENDXES ntrductin.... SDS 92 Registers.... SDS 9.2 Memry.... Memry Wrd Frmats.... Addressing Facil ities.... Trapping Facil ity.... MACHNE NSTRUCTONS Lad;Stre nstructins.... Flag nstructins.... Lgical nstructins.... Cmparisn nstructins.... Branch nstructins.... Shift nstructins.... Cntrl nstructins Trapping nstructins.... Breakp i nt Tests.... NPUT/OUTPUT SYSTEM APPENDX A APPENDX B SDS Character Cdes Table f Pwers f Tw.... Octal-Decimal nteger Cnversin Table.. Octal-Decimal Fractin Cnversin Table. Tw's Cmplement Arithmetic.... Optinal Equipment Real-Time Clck Autmatic Pwer Fail-Safe.... Data Mu tiplexing System.... Memry Parity nterrupts.... Trapping Return Subrutine Example.... SDS 92 Memry Allcatin nstructin List - Functinal Categries. 92 nstructin List - Numerical Order nstructin List - Alphabetical Order A-1 A-2 A-3 A-7 A-lO B-1 B-1 B-1 B-1 B-4 B-5 B-6 B-7 B-11 B-15 ntrdu ct in.... Data Transfer nstructins.... /O Channel Operatin.... EOM nstructins.... SES nstructins.... nterlace.... POT/BPO, PN/BP nstructins Single Bit nput/output.... /O Terminatin Prgramming Ntes.. Pririty nterrupt System (Optinal).. Cntrl Cnsle.... Peripheral Equ ipment Descriptin.... nput/output Typewriter.... Paper Tape nput/output.... Card nput/output.... Magnetic Tape nput/output Line Printer FGURES SDS 92 Cmputer (Frntispiece).... SDS 92 Cmputer Cnfiguratin.... Basic Register Flw Diagram.... ROT/RN Data Transmissin.... SDS 92 Channel Buffer.... nterrupt Arm-Enable Respnse.... SDS 92 Cmputer Cntrl Panel.... Card Read int Memry in Hllerith.... Printer Cntrl ndicatrs and Switches TABLES Unit Address Cdes nterrupt Lcatin Assig nments.... Frmat Cntrl Characters.... iv iii

6 J liin, ~" SDS 92 Cmputer iv

7 . GENERAL DESCRPTON NTRODUCTON The SDS 92 is a small, high-speed, very lw-cst, generalpurpse cmputer designed especially t include applicatin in the fllwing areas: High-speed cmputer-based systems featuring speed and flexibility Frmat cnversin featuring cmplete versatility in frmats and equipment invlved Small, general-purpse applicatins featuring repetitive, high-speed cmputatin The SDS 92 has the fllwing characteristics: The first cmmercia cmputer using mnlithic integrated circuits; all fl ip-flps are integrated 12-bit wrd plus parity bit 1.75 jjsec memry cyc e Binary, integer arithmetic 12- and 24-bit instructins mmediate, direct and indirect addressing 2048-wrd basic memry Memry expandable t 4096, 8192, 16,384 r 32,768 wrds, all directly addressable Tw independent arithmetic registers, either f which may be an accumulatr True ndex Register; adds n time t executin nstructin set cmparable t medium-scale cmputer; includes shift instructins 4096 single-bit cntrl utputs; 4096 single-bit sense inputs ndependent /O buffer with autmatic assembly/ disassemblyf 6-bit characters t/frm wrds (standard) /O blck transfer standard Three standard /O mdes: 6-bit characters, 286,000 characters/secnd, parity checked and packed 1 per wrd 6-bit characters, 286,000 characters/secnd, parity checked and packed 2 per wrd 12-bit parallel wrds, 572,000 wrds/secnd, parity checked /O transfer f 12-bit characters, 286,000 characters/ secnd, parity checked, ptinal Fur cnsle sense switches Optinal features nterlace feature fr standard /O buffer High-speed multiply and divide instructins, 5 and 13 cycles, respectively Many-channel Data Multiplexing System using a secnd, independent path t memry 24-bit parallel /O Up t 256 levels f true pririty interrupt Autmatic pwer fai -safe Memry parity checking Real-time clck Peripheral equipment fr the SDS 92 Sftware Keybard/printer (teletype) with r withut paper tape reader and punch, 10 cps Paper tape reader and punch, 300 and 60 cps, respectively MAGPAK Magnetic Tape System All equipment in SDS standard peripheral line Basic uti lity package Symblic assembler /O packages fr ptinal peripheral equipment Mathematical subrutines, including flatingpint arithmetic, fixed-pint multiply and divide, and elementary mathematical functins All silicn semicnductrs O perating temperature range: 100 t 40 0 C Dimensins: 65 in. x 30 in. x 25-1/2 in. Pwer: 1 kva 1-1

8 EOM SES 12-bit Wrd POT/PN Para e, Single Wrd BPO/BP r Blc k (24-bit Single Wrd 0 ptinal).--_.. 12 bits Optinal L 6 bits (plus parity) {} Pririty nterrupt up t 256 Levels J t t t SDS 92 Cmputer Basic /O Channel ~ External Devices ~ 12 bits WOT;WN ROT/RN t t f t t Cre Memry 2048 Wrds Expandable t : 4K 8K 16K 32K t Secn d Memry Path Data Multiplex System! 4 f t f Subchannels (6-bit, 12-bit, r 24-bit) tems with dtted lines (---) are ptinal. Figure 1-1. SDS 92 Cmputer Cnfiguratin 1-2

9 SDS 92 REGSTERS The 92 Central Prcessr cntains the fllwing arithmetic and cntrl registers. They are full-wrd, 12-bit registers except as nted. AVALABLE TO THE PROGRAMMER (dark lines) The A Register and the B Register are tw independent, 12-bit accumulatrs. The A Register is als the index register. The P Register is a 15-bit register that cntains the memry address f the current instructin. Unless mdified by the prgram, the cntents f P increase by ne during ne-wrd instructins and increase by tw during tw-wrd instructins. The Flag Bit Register is a ne-bit register used fr arithmetic carry, strage and testing. NOT AVALABLE TO THE PROGRAMMER (light lines) The S Register is a 15-bit register that cntains the address f the memry lcatin being accessed fr instructins r data. The C Register, is a 12-bit register that is used in arithmetic and cntrl peratins. The 0 Register is a 6-bit register that cntains the peratin cde f the instructin being executed. The M Register is a 13-bit register that hlds each wrd as it cmes frm memry. Recpying f a wrd int memry takes place frm the M Register. 1 Flag B;, F j B (Accumu latr) A (Accumulatr and/ r ndex) j Adder,, -- S (Memry Address) - C (Arithmetic and Cntrl) P (Prgram Cunter) -- M (Memry Access) (Opcde) ~ Memry Figure 1-2. Basic Register Flw Diagram 1-3

10 SDS 92 MEMORY The basic 92 memry cntains 2048 wrds, cnsisting f 12{,its plus parity. Memry is available in 4096-, 8192-, 16,384- and 32,768-wrd sizes. The central prcessr can directly address all memry. Addresses fr memry wrds extend frm lcatins t (ctal). f the address f the next instructin t be executed is utside f available memry (fr less than 32,768-wrd memries), the 92 executes a halt instructin ( ); the P Register wi cntain the requested address + 2. Fr example, assume a 3777-wrd memry and ffers great versatility bth in addressing and indexing capabilities. n mst cases, the instructin can select either the A r B fr use as the accumulatr. Bit Psitin Meaning Register Selectin: 1 = A Register r = B Register nstructin Cde Scratch Pad Bit 1. the instructin "Branch-t" 4000, r 2. the instructin "Lad A" whse lcatin is ndirect Address Bit ndex Register Bit n bth cases, a halt ccurs after executin f the instructin and the P Register cntains 4002 which is utside f available memry. Nte that the P Register respnds as if there were always 32,768 wrds f memry. With a 32,768-wrd memry, the memry is a "wrap-arund" r circular memry where the next lcatin after is An attempt t read frm a lcatin whse address is nt avai lable causes zers t be read. An attempt t stre int such a lcatin essentially results in a "n-p" peratin, with the next instructin in sequence being executed. A prgram can use th is prperty t determine the cre size avai lable in the machine. A pwer fai -safe ptin is avai lable such that: befre accessing each memry wrd, the c;"puter checks the pwer t ensure that it can cmplete the entire read/write cycle. f it detects a pwer lss, the cmputer halts. With the memry parity ptin, the cmputer autmatically generates even parity r checks fr it during each read/write cycle (ptinal). Setting a cntrl panel pa~ity switch causes the cmputer t halt autmatically in case f parity errr detectin. MEMORY WORD FORMATS A cmputer wrd is 12 binary digits (bits) lng: " The wrd frmat numbers the bits frm the left, r mst significant end f the wrd, t the right, r least significant end f the wrd. This numbering frmat serves as a basis f reference t bit psitins r bit numbers. Octal ntatin mst easi y describes the cntents f the 12 bits f a wrd. Thus, ne ctal digit, 0 thrugh 7, represents three binary digits. Fr example, the ctal number, 0123, represents its binary equivalent, The 92 instructin wrd: Opcde y Part f the Address Field The flexibility f addressing in the 92 allws bits 7, 8, and 9 thrugh 11 t be used in mre than ne way as explained belw. ADDRESSNG FACLTES The 92 has ne-wrd r tw-wrd instructins with the length depending n the addressing mde being used. The addressing mdes are: Direct, Tw Wrds ndirect, One Wrd ndirect, Tw Wrds Direct, One Wrd mmediate, One Wrd Addressing Area Full Memry ndirect Thrugh Scratch Pad ndirect Thrugh Full Memry Scratch Pad Next Lcatin ndirect addressing can be cascaded indefinitely. The standard assembler frms fr instructins are: Frm Type Label Opcde n Direct, One and Tw Wrds Label Opcde n, 1 Direct, Tw Wrds, ndex Label Opcde *n ndirect, One and Tw Wrds Label Qpcde =c mmediate where n is a label r a 1- t 5-digit number, c is a 1- t 4-digit number «4096). The fllwing sectin describes the bit cnfiguratins that the ctal prgrammer r the symblic assembler must prvide t select the varius addressing mdes. Direct Addressing The prgrammer selects direct addressing by setting bth bits 6 and 7 t zer. Bits 9 thrugh 11 f the first wrd cmbine with the entire secnd wrd t frm a 15-bit address t directly address up t 32,768 wrds. Bit 8 f the first wrd can specify indexing. r The multiply instructins are exceptins. 1-4

11 nstructin Frm: LOW H Direct Addressing With N ndexing The cmputer cnstructs the 15-bit direct address frm bits 9, 10, 11 f the instructin wrd and bits 0 thrugh 11 f the next lcatin. Example 1: R 0 Opcde M M ' Assembler Frm: LDB Machine Language Frm: Nte: n the standard assembler, a 0 precedes any ctal number; nth i ng precedes a dec i ma number written as a literal (i. e., immediate). Direct Addressing With ndexing When the prgrammer sets the ndex Bit (number 8) t 1, the cmputer subtracts the cntents f the A Register frm the direct address t btain the effective address. Example 2: Assume (A)=OOOl MMMMM NNNN Effective Address Assembler Frm: LDB , Machine Language Frm: M M This instructin lads the cntents f lcatin int the B Register. Nte: Althugh the A Register is nly 12 bits lng, the tp three bits f the address will be mdified by indexing if a "brrw" ccurs. Scratch Pad Addressing Memry lcatins t are referred t as the "scratch pad" memry and are special nly in that they can be addressed mre si mply. When the prgrammer sets the Scratch Pad ndicatr (bit 6) t 1, the instructin addresses ne f the 31 scratch pad lcatins. This allws a cmplete instructin in a single wrd. The frm f the instructin is: Opcde 1 Scratch Pad., Address The value f n must be in the range 1 ~ n ~ 31 10, Example: Assume. --- lcatin 34 Then the instructin: LDB yields (8) = 2333 mmediate Addressing 7 Cntents When the prgrammer sets the Scratch Pad ndicatr t 1 and sets bits 7 thrugh 11 t 00, the instructin acquires its address by adding ne t the current cntents f the $ Register. That is, the next lcatin cntains the perand. The cmputer autmatically increments the Prgram Cunter by an additinal ne t take the next instructin frm the wrd fllwing the immediate perand wrd. The frm f the instructin is: 1 Opcde 0 0 OPERAND t The standard assembler frm is: LDA =, where "=" means "take the fllwing number literally". Example: -- LDA = n the standard assembler, a 0 precedes any ctal number; nthing precedes a decimal number written as a literal (i. e., immediate). 1-5

12 ndirect Addressing Take LDB * which is! The indirect addressing facility prvides tw ways f specifying the pinting address. ndirect Frm Scratch Pad First, the single-wrd instructin specifies that the pinting address is within the secnd 16 lcatins f the Scratch Pad area (lcatins 208 thrugh 378). The specified pinting address used in the standard assembler frm must be in the range: 20.::; n ::; 36, n even. n this mde, the instructin bits have the frm: Opcde where bit 6 is 0 and bits 7 and 8 are l. Bits and C frm a five-bit address that selects the fi;st ~f t~ c~ntiguus address wrds. The cmputer always supplies a least significant fifth bit (C) that is zer, making all such Scratch Pad addresses even. When the addressing lgic selects the even address, it reinitiates addressing and interprets that lcatin and the next ne as an instructin wrd-pair withut an instructin cde. These tw (r ne) wrds can specify all frms f addressing. Bit 8 f the instructin des nt effect indexing in this perating mde. Example: Then, LDB *034 Lcatin Cnte~ts yields reinitialized addressing n lcatins 34, Since the 0 in bits 6,7,8 f lcatin 34 indicates direct addressing, the instructin des the fllwing: ndirect Full Addressing (20010) = 0004~B The secnd frm f indirect addressing is: OP:Ode! : ~ :! where the 0 in bit 8 specifies that the pinting address cnsists f a 15-bit address cnstructed as in Direct Addressing. Example: Assume Lcatin H Cntents This yields: : : 6 7 (32000) = 0001 (32001) = : 9 The lgic reinitializes addressing and ( 14020) :r: B The tw Pinter wrds can specify all frms f addressing. TRAPPNG FACLTY Prgram-Cntrl ed The prgram-cntrlled trapping facility permits the calling f subrutines with a single instructin f the same frm as builtin, machine instructins. The trapping is cntrlled by the status f the Prgram-Cntrlled Trap (PCT) bit. When PCT is a 0, the cmputer decdes the eight trapping Opcdes as special instructins and executes the Opcde in the unique trapping lcatin determined by the Opcde. When PCT is a 1, the cmputer decdes the eight Opcdes as nrmal instructins. The Opcdes, their nrmal names, and their respective trapping lcatins fllw. Opcde Trapping Lcatin Nrmal Mnemnic POT BPO WOT ROT PN BP WN RN One f the "branch and mark place" instructins BRM r BMC placed in the trapping lcatin (and lcatin plus ne) by the prgrammer branches t the assciated subrutine. The mark infrmatin prvides the subrutine inkage back t the main prgram, i. e., the address stred in the mark is the address f the instructin that caused the trap. The prgram sets, resets, and tests the PCT bit via the instructin: SET PROGRAM-CONTROLLED TRAP (SCT) RESET PROGRAM-CONTROLLED TRAP (RCT) TEST PROGRAM-CONTROLLED TRAP (TCT) Multiply and Divide When the high-speed multiply/divide ptin is nt prese~t in a system, an attempt t execute the assciated instructin cde causes a transfer t a special trap lcatin. These lcatins are: Mnemnic Opcde Lcatin MUA MUB DVA DVB When the ptin is absent, the trapping prcess is always active and cannt be inhibited by the prgrammer. 1-6

13 Trapp i ng Ntes When a trap ccurs, the P cunter is nt incremented. t is therefre mandatry that nly branch instructins be placed in the trap instructins; therwise, the prgram ges int an unrecverable lp: Assume there is n multiply ptin. 124 L~A MUA 5000 f MUA is executed, the executin sequence is: 1200 MUA 124 LDA 1200 MUA 124 LDA Appendix-B-5 cntains a cmplete trap-subrutine example. that is useful as a guide t writing subrutine return cde. Nmenclature Thrughut the fllwing discussins, the term "next lcati~n" refers t the lcatin immediately fllwing the lcatin f the instructin under discussin. The simi lar term "next address" is als used. The term "effective memry lcatin" describ~s the lcatin in memry frm which the cmputer takes the final perand at the cnclusin f all indirect addressing and indexing. The effective memry lcatin is the lcatin whse address is the effective address. 1-7

14

15 . MACHNE NSTRUCTONS This sectin describes SDS 92 instructins; they are presented in functinal grups. Lists f instructins in functinal, numerical and alphabetical rder are in Appendices B-7 thrugh B-17. The fllwing statements apply t the instructin descriptins. All instructin times are in memry cycles, where each cycle is 1.75 micrsecnds. All timings assume that the instructin addresses perands in scratch-pad memry (even thugh the instructin may, in fact, preclude this mde f addressing). Fr mre cmprehensive addressing, add cycles t the given executin times as fllws: mmediate Direct Full Addressing Direct Full with ndexing ndirect Addressing One-Wrd, even scratch-pad address ndirect Addressing Tw-Wrd, Fu add ress Cycles a P 1 + P where P is the number f cyc les required t prcess the indirect address pair. Parentheses dente cntents f ", as, fr example, (A) represents the cntents f the A Register. The interrupt system (ptinal) can interrupt the prgram sequence at the end f any instructin except as nted. STA (STB) a 44(04) STORE A (STORE B) Y STA stres the cntents f the A Register in the effective memry lcatin. Registers Affected: M Timing: 2 XMA (XMB) EXCHANGE M AND A (EXCHANGE M AND B) a 74(34) XMA lads the cntents f the effective memry lcatin int the A Register and stres the cntents f the A Register in the effective memry lcatin. Registers Affected: A(B), M FLAG NSTRUCTONS XMF a 17 EXCHANGE M AND FLAG Timing: 3 XMF lads the cntent f the Flag Bit int bit a f the effective memry lcatin and lads the cntent f bit a int the Flag Bit; it leaves bit psitins 1 thrugh 11 f the effective memry lcatin the same as they were. Thse instructins that apply t the A and the B Registers appear with the B Register peratin cde and mnemnic in parentheses. Registers Affected: F, M LDF LOAD FLAG Timing: 3 With each instructin descriptin is a diagram depicting the instructin frmat. Preceding this diagram is the mnemnic cde and the instructin name. n the diagram, S stands fr Scratch Pad Bit, stands fr ndirect Address Bit, X stands fr ndex Bit, and Y stands fr part f the address. The letter M depicts a general memry lcatin. a LDF lads the cntent f bit a f the effective memry lcatin int the Flag Bit. LOAD /STORE NSTRUCTONS LDA (LDB) a 64(24) LOAD A (LOAD B) LDA lads the cntents f the effective memry lcatin int the A Register. Registers Affected: A(B) Timing: 2 Registers Affected: F SFT a SET FLAG TRUE SFT uncnditinally sets the Flag Bit t a ne. SFT cannt be interrupted. Registers Affected: F 11 Timing: 3 Timing: 3,4 2-1

16 SFF SET FLAG FALSE SUA (SUB) SUBTRACT TO A (SUBTRACT TO B) SFF uncnditinally resets the Flag Bit t a zer. SFF cannt be interrupted Registers Affected: F Timing: 3, (20) SUA subtracts the cntents f the effective memry lcatin frm the cntents f A and places the result in Ai it stres the carry frm bit 0 in the Flag (F) bit. [(M) > (A) sets Fi (A) ~ (M) resets F.J NF NVERT FLAG Registers Affected: A(B), F Timing: NF uncnditinally inverts the Flag Bit. it t a Oi if it is a 0, NF sets it t a 1. NF cannt be interrupted. Registers Affected: F ARTHMETC NSTRUCTONS 11 f it is a 1, NF sets Timing: 3,4 Example: Assume (A) = 3003 (10) = 4010 (F) = 0 SCA (SCB) Perfrming SUB 010 yields (A) = 6773 (F) = 1 SUBTRACT WTH CARRY TO A (SUBTRACT WTH CARRY TO B) ADA (ADB) 62(22) ADD TO A (ADD TO B) ADA adds the cntents f the effective memry lcatin t the cntents f A and stres the result in Ai it stres the carry frm bit 0 f the additin in the Flag Bit. Registers Affected: A(B), F Example: Assume (A) = 4300 (1000) 3700 (F) = 0, Flag Bit ACA (ACB) Perfrming ADA (A) 0200 (F) = 1 yields Timing: 2 ADD WTH CARRY TO A (ADD WTH CARRY TO B) 61(21) ]] SCA subtracts the cntent f the effective memry lcatin frm the cntents f the A Register, then subtracts the cntent f F frm the least significant end f the difference and places the result in A. t places the carry frm bit 0 in the Flag (F) bit. [(M) +F > (A) sets Fi (A)~(M)+FresetsF.] Registers Affected: A(B), F Timing: 2 MPA (MPB) 76(36) MEMORY PLUS A TO MEMORY (MEMORY PLUS B TO MEMORY) MPA adds the cntents f the effective memry lcatin t the cntents f A and places the result in the effective memry lcatin; it stres the carry frm bit 0 in the Flag Bit. Registers Affected: M, F Timing: 3 63(23) MPO MEMORY PLUS ONE TO MEMORY ACA adds the cntents f the effective memry lcatin t the cntents f Ai it als adds the cntent f the Flag Bit t bit psitin 11 f the result. ACA places the final result in Aand recrds the carry frm bit 0 in the Flag Bit. Registers Affected: A(B), F Timing: MPO increments the cntents f the effective memry lcatin by ne and places the result back int the same lcatin; it places the carry bit frm bit 0 in the Flag Bit. Registers Affected: M, F Timing: 3 2-2

17 MPF MEMORY PLUS FLAG TO MEMORY Exampl e: Assume (A) = 0027 (B) = 4335 (1000) = MPF adds the cntent f the Flag Bit t the cntents f the effective memry lcatin at bit psitin 11 and places the result back int the effective lcatin. The carry frm bit f the additin ges int the Flag Bit. Registers Affected: M, F Timing: 3 PerfrmingDVA01000 (B) = 6217 (A) = 0033 yields The div is in is perfrmed as fllws: B A MUA MULTPLY A (Optinal) 13 Y / MUA multiplies the cntents f A by the cntents f the effective memry lcatin and places the prduct in A and B with the mre significant prtin in A. Registers Affected:. A, B Example: Assume (A) = 3411 (1000) = 0220 Timing: J H * 151 LOGCAL NSTRUCTONS ANA (ANB) AND TO A (AND TO B) 65(25) A B ANA perfrms a lgical AND with the cntents f the A Register and the cntents f the effective memry lcatin; it places the result in A. The previus cntents f A are lst. Perfrming MUA (A) = 0077 (B) = 2420 yields Registers Affected: A, (B) Timing: 2 MUB MULTPLY B (Optinal) ORA (ORB) OR TO A (OR TO B) MUB multiplies the cntents f B by the cntents f the effective memry lcatin and places the prduct in A and B with the mre significant prtin in A. Registers Affected: A, B DVA(DVB) 52(12) DVDE AB (DVDE BA) (Optinal) Timing: 5 DVA(DVB) divides the cntents f the A and B Registers (B and A Registers) treated as a duble-precisin number by the cntents f the effective memry lcatin and places the qutient in the B Register with the remainder in the A Register. The A Register (B Register) must initially cntain the mre significant half f the dividend. The cntents f the effective memry lcatin must be greater than the cntents f A (B). Registers Affected: A, B Timing: 13 67(27) ORA perfrms a lgical "inclusive OR with the cntents f the A Register and the cntents f the effective memry lcatin; it places the result in A. The previus cntents f A are lst. Registers Affected: A, (B) Timing: 2 EOA (EO B) EXCLUSVE OR TO A (EXCLUSVE OR TO B) 66(26) EOA perfrms a lgical "exclusive OR with the cntents f the A Register and the cntents f the effective memry lcatin; it places the result in A. The previus cntents f A are lst. Registers Affected: A, (B) Timing: 2 2-3

18 MAA(MAB) 75(35) t MEMORY AND A TO MEMORY (MEMORY AND B TO MEMORY) MAA perfrms a lgical AND with the cntents f the A Register and the cntents f the effective memry lcatin; it places the result in the effective memry lcatin. The previus cntents f the memry lcatin are lst; MAA leaves the cntents f A undisturbed. Y 11 BRANCH NSTRUCTONS BRU 73 BRANCH UNCONDTONALLY The cmputer takes the next instructin frm the lcatin determined by the effective address. BRU cannt be interrupted. Registers Affected: Nne Timing: 1 Registers Affected: M Timing: 3 COMPARSON NSTRUCTONS COA(COB) COMPARE ONES WTH A (COMPARE ONES WTH B) BRC 32 BRANCH, CLEAR NTERRUPT AND'LOAD FLAG (05) COA cmpares the cntents f the A Register, bit by bit, with the cntents f the effective memry lcatin. f the cntents f A and the cntents f the effective lcatin have any nes in crrespnding bit psitins, COA resets the Flag Bit. f there is n such crrespnding pair f ne bits, COA sets the Flag Bit. The cmputer takes the next instructin frm the lcatin determined by the effective address; it als clears the currently active interrupt level. f BRC uses direct addressing, it clears the Flag Bit and sets the PCT bit. f it uses indirect addressing, BRC places int the Flag Bit and PCT bit the cntent f bits 0 and 1 f the first wrd f the last indirect address pair. Registers' Affected: F, PCT BRL BRANCH AND LOAD FLAG Timing: 3 Registers Affected: F Timing: 2 'CMA(CMB) COMPARE MAGNTUDE OF M WTH A (COMPARE MAGNTUDE OF M WTH B) (07) f the cntents f the A Register are arithmetically less than the cntents f the effective memry lcatin, CMA resets the Flag Bit. Otherwise, it sets the Flag Bit. BRL transfers t the effective memry lcatin. f BRL uses direct addressing, it clears the Flag Bit and sets the PCT bit. f it uses indirect addressing, BRL places int the Flag Bit and the PCT bit the cntent f bits 0 and 1 f the first wrd f the last indirect address pair. BRL cannt be interrupted. Registers Affected: F, PCT Timing: Registers Affected: F Timing: 2 BFF BRANCH ON FLAG FALSE CEA(CEB) 46(06) COMPARE M EQUAL TO A (COMPARE M EQUAL TO B) f the cntents f the A Register are equa t the cntents f the effective memry lcatin, CEA resets the Flag Bit. Otherwise, it sets the Flag Bit. Registers Affected: F Timing: f the cntent f the Flag Bit is zer, the cmputer takes the next instructin frm the lcatin determined by the effective address. f the cntent is ne, the ~mputer executes the next instructin in sequence. f a branch ccurs, there can be n interrupt. Registers Affected: Nne Timing: 1 if Branch 2 if N Branch 2-4

19 BFT BRANCH ON FLAG TRUE BMC BRANCH, MARK PLACE, AND CLEAR FLAG y 11 f the cntent f the Flag Bit is ne, the cmputer takes the next instructin frm the lcatin determined by the effective address. f the cntent is zer, the cmputer executes the next instructin in sequence. f a branch ccurs, there can be n interrupt. Registers Affected: Nne Timing: 1 if Branch 2 if N Branch BOA 70 BRANCH ON DECREMENTNG A BOA decrements the cntents f the A Register by ne. t then tests the result unequal t , f unequal, the cmputer takes the next instructin frm the lcatin determined by the effective address. f equa, the cmputer executes the next instructin in sequence. t f a branch ccurs, there can be n interrupt. f this instructin specifies indexing, the indexing is perfrmed befre A (the index register) is decremented. Registers Affected: A Timing: 1 if Branch 2 if N Branch BAX 30 BRANCH AND EXCHANGE A AND B BAX exchanges the cntents f A with the cntents f B; then it branches t the lcatin determined by the effective memry address. BAX cannt be interrupted. f this instructin specifies indexing, the indexing wi be perfrmed befre the interchange f A and lib. Registers Affected: A, B BRM 77 BRANCH AND MARK PLACE Timing: 1 BRM stres the cntents f the Prgram Cunter (which cntains the address f the next instructin in sequence) in bits 9 thrugh 11 f the effective memry lcatin and bitso thrugh 11 f the effective lcatin plusne. t stres the cntent f the Flag Bit in bit 0 and the cntent f the PCT bit in bit 1 f the effective lcatin; bits 2 thrugh 5 f the effective lcatin are unpredictable. Bits 6 thrugh 8 f the effective lcatin are cleared. BRM then branches t the effective memry lcatin plus tw. mmediate addressing is nt allwed. Registers Affected: M, M+ 1 Timing: 3 tas with any instructin, when using immediate addressing with a BOA, the phrase lithe next instructin in sequence refers t the instructin tw lcatins beynd the BOA. BMC stres the cntents fthe Prgram Cunter in bits 9 thrugh 11 f the effective memry lcatin and bits 0 thrugh 11 f the effec.. tive lcatin plus ne. t stres the cntents f the Flag Bit in bit 0 and the cntents f the PCT bit in bi t 1 f the effective lcatin; bits 2 thrugh 5 f the effective lcatin are unpredictable. Bits 6 thrugh 8 f the effective lcatin are cleared. The Flag Bit is cleared and the PCTbit isset. BMCthen branches t the effective memry lcatin plus tw. mmediate addressing is nt allwed. Registers Affected: M, M + 1, F, PCT Timing: 3 Nte that the BMC instructin is the ne nrmally executed when an interrupt ccurs. The add ress stred in th i s case is the lcatin f the next instructin t be executed in the main prgram. SHFT NSTRUCTONS Shift instructins perate n. the A, B, and Flag Registers. The shifts can be single r duble register. All sh ifts are t the left. The number f shifts N is specified in the least significant 4 bits f the effective address. The maximum number f shifts is 15 (178); zer is allwed. N is written in the 4 bits, in nels cmplement frm (i.e., a shift N =7 appears as 10 ), 8 The single r duble shift is determined via bit 7 f the effective address; it is a 0 fr single-register shift and a 1 fr dubleregister shift. The cnventinal address frmats are: One-Wrd Address Tw-Wrd Address Opcde 0=1 lis Cmplef 11 Shift Timing Shift Cunt (Decimal) Timing (Cycles)

20 CYA(CYB) CYCLE A (CYCLE B) CF CYCLE FLAG AND DOUBLE NVERSE 42 (02) CYA shifts the cntents f the A Register N places t the left. All bits shifting past psitin 0 shift int psitin 11. The ne's cmplement f N, the number f psitins t be shifted, is placed in the least significant 4 bits f the effective address. Registers Affected: A(B) d A(B) b CFA(CFB) CYCLE FLAG AND A (CYCLE FLAG AND B) CF shifts the cntents f the B and A Registers and the F lag Bit, taken as a single 25-bit register, N places t the left. Bits shift frm psitin 0 f A int psitin 11 f B, frm psitin f B int the Flag Bit, and frm the Flag Bit int psitin 11 f A. The ne's cmplement f N is placed in the least significant 4 bits f the effective address. Registers Affected: A, B,F CONTROL NSTRUCTONS r0j_b ---,H,--_A -----h 43 (03) EXU EXECUTE 11 CFA shifts the cntents f the A Registerand the Flag Bit, taken as a single 13-bit register, N places t the left. All bits shifting past psitin 0 shift int the Flag Bit, bits frm the Flag Bit g int psitin 11. The ne's cmplement f N is placed in the least significant 4 bits f the effective address. Registers Affected: A(B), F reh A(B) b CYD CYCliDOUBli 02 r [ X y CYD shifts the cntents f the A and B Registers N places t the left. All bits shifting ut f psitin 0 f A shift int psitin 11 f B; all bits shifting ut f psitin 0 f B shift int psitin 11 f A. The ne's cmplement f N is placed in the least significant 4 bits f the effective address. Registers Affected: A, B A H... _B_h CFD CYCLE FLAG AND DOUBLE CFD shifts the cntents f the A and B Registers and the Flag Bit, taken as a single 25-bit register, N places t the left. Bits shift frm psitin 0 f B int psitin 11 f A, frm psitin 0 f A int the Flag Bit, and frm the Flag Bit int psitin 11 f B. The ne's cmplement f N is placed in the least significant 4 bits f the effective address. Registers Affected: A, B, F r0j,---a ---,H,--_B -b EXU executes the instructin in the effective memry lcatin. Then the cmputer executes the next instructin fllwing EXU. f the effective memry lcatin cntains a branch, cntrl ges t the branch-t lcatin. f the effective lcatin cntains anther EXU, the prcess repeats with cntrl always returning t the next lcatin after the first EXU r t the branch-t 10-' catin if the last instructin is a branch instructin. mmediate addressing is nt allwed n EXU (this restrictin des nt apply t the instructin executed}. N "trappable" instructin that wi trap can be executed. Registers Affected: Nne HLT 00 HALT One Wrd Timing: time f instructin executin HLT halts instructin executin and lights the HALT light. T resume cmputatin, the peratr sets the mde switch t DLE and then t RUN r STEP at which time the cmputer executes the instructin in the lcatin addressed by the cntents f the Prgram Cunter. (This wi be the instructin fllwing the ti LT instructin if the peratr has nt changed the cntents f the Prgram Cunter. ) f an interrupt ccurs while halted by a HALT (while still in RUN), the cmputer acknwledges the interrupt and cmputatin resumes. (The instructin fllwing the HLT instructin will be executed fllwing the prcessing f the interrupt.) Registers Affected: Nne Timing: 3,4 2-6

21 TRAPPNG NSTRUCTONS SCT 00 SET PROGRAM-CONTROLLED TRAP 5 6 SCT uncnditinally sets the PCT bit t a ne. SCT cannt be interrupted TCT 01 TEST PROGRAM-CONTROLLED TRAP TCT tests the status f the PCT bit. f PCT is a ne, it sets the Flag Bit t a ne. f PCT is a zer, it sets the Flag Bit t a zer. Registers Affected: F Timing: 3, Registers Affected: PCT Timing: 3,4 BREAKPONT TESTS RCT RESET PROGRAM-CONTROLLED TRAP 00 )6 60 RCT uncnditinally sets the PCT bit t a zer. RCT cannt be interrupted. 11 This instructin tests the status f the Breakpint switches. f the selected switch is set, the Flag Bit is set t a 1. f the switch is reset, the Flag is set ta O. Mnemnic BPT 1 BPT2 BPT 3 BPT 4 Cding Registers Affected: PCT Timing: 3,4 Regi sters Affected: F Timing: 3,4 2-7

22

23 . NPUT/OUTPUT NSTRUCTONS NTRODUCTON The SDS 92 has a cmprehensive input/utput system t cmplement its high internal prcessing speed. This system can transmit data in wrd, character, and single-bit frm t and frm the cmputer at the speed f internal cmputatin. The input/ utput system is f great variety and can assume cntrl f cnditins impsed by a wide range f input/utput j special system devices; but the cmputer always leaves a high degree f flexible input/utput cntrl t the prgrammer. Central Prcessr Memry The system cntains: Buffered input/utput f data wrds, under prgram cn. trl in blcks r as single wrds. nput/utput f blcks f data via subchannels; up t 64 channels simultaneusly perating thrugh a multiplexing system (ptinal). Direct parallel input/utput f 12-bit wrds, singly r in blcks, t and frm external static registers. WOT causes a wrd t be taken frm the specified memry lcatin and placed in the /O Channel t be utput when requested by the currently active peripheral device. Single bit input/utput, such as equipment n/ff status, sense switches, and pulsing and sending f special signals. /O CHANNEl Central Prcessr Memry The /O Channel, standard equipment in the cmputer, perfrms input/utput f wrds singly r in blcks. On utput, the /O channel transmits wrds in 6-bit characters, ne r tw characters per wrd as selected, r in 12-bit (ptinal) single character frm. On input, the /O channel receives wrds in 6-bit characters, ne r tw per wrd, r 12-bit (ptinal) characters as desired. This channel transmits single wrds r blcks. The prgram places the blck cunt in the A Register prir t the transfer and the cmputer cunts this dwn t 7777 autmatically t terminate the transfer peratin. SNGLE WORD TRANSMSSON Using the /O Channel, a prgrdm can transmit data wrds between memry and peripheral devices under single instructin cntrl. T d this, the prgram first activates the channel and the peripheral device with an energize r "alert" instructin (ne f the cnfiguratins f the multi -purpse instructin, ENERGZE OUTPUT M (EOM)). WOT is the WORD OUT instructin; WN is the WORD N instructi.n. WN causes a wrd frm a peripheral device t be taken frm the /O channel and placed directly int the specified memry lcatin with.ut disturbing any internal registers.. T transfer blcks f data wrds via the /O channel, the prgram uses the same EOM cnfiguratin t set the channel fr peratin; the prgram specifies the number f wrds in the transfer.by placing the wrd cunt minus ne in the A Register ((A) + 1 = N). The RECORD OUT (ROT) instructin causes the cmputer t utput wrds frm the effective address M thrugh the effective address plus the cntents f A (M thrugh M + (A)). The RECORD N (RN) instructin causes the cmputer t input frm the actively transmitting peripheral device; the peratin terminates when the cmputer receives N wrds, r when it receives an "end-f-recrd" frm the peripheral device. RN and ROT tie up the cmputer during the entire input/utput transmissin. 3-1

24 Central Prcessr Memry Fr a PN, EOM alerts the sending device, PN stres the least significant 12 bits, the high-rder bits fill the extender, EOM a erts the extender, and anther PN stres the cntents f the extender. Ne i ther f these cd i ng sequences can be interrupted. See the nterrupt System paragraphs fr the Alert Extender EOM fr bth POT and PN. (A) = N-1 N-1 SNGLE BT NPUT/OUTPUT The EOM and SES instructin prvide a general single bit transmitting and sensing facility fr use as test and cntrl signals with special systems and standard peripheral devices. DATA TRANSFER NSTRUCTONS Figure 3-1. ROT/RN Data Transmissin Tw instructins cntrl the prcess f transmitting and receiving data-between peripheral equipment and the central prces \ sr using the /O Channel. These instructins are: EOM S-ES ENERGZE OUTPUT M SENSE EXTERNAL SGNAL The EOM instructi n activates the /O Channel, selects the peripheral device, and requests the desired peratin. The prgrammer uses the SES instructin t test fr all input/utputperatinal cnditins; SES is multipurpse like the EOM. Later sectins describe the exact cnfiguratins f EOM and SES. DRECT PARALLEL NPUT/OUTPUT, 12 BT The parallel input/utput facility allws full, 12-bit wrds t be transmitted directly ut f and int the memry. After activating the peripheral device r special system device with an activating EOM, the PARALLEL OUTPUT (POT) and PARALLEL NPUT (PN) cause any selected wrd in cre memry t be presented t the peripheral device cnnectr; r cnversely, cause a wrd (12-bit signa ) received int the device cnnectr t be stred in the selected lcatin. POT/PN als check r generate crrect memry parity with each wrd transmitted. The system prvides a blck transfer frm f POT and PN with the instructins, BLOCK PARALLEL N (BP) and BLOCK PAR ALLEL OUT (BPO). By placing the wrd cunt N minus ne in the A Register, BP and BPO prvide the identical functin f PN and POT, respectively, n N cnsecutive wrds. Parity checking/generating is autmatic fr these peratins n machines equipped with the memry parity feature. N interrupt can ccur between any f these instructins and the instructin fllwing it. WOT WORD OUT WOT transfers the cntents f the effective memry lcatin int the /O channel buffer. f the buffer is nt ready, the central prcessr hangs Upll unti the buffer empties frm a previus instructin and is ready t accept the new data wrd. Registers Affected: Nne ROT 51 RECORD OUT Timi ng: 4 + wait Starting with the effective memry lcatin, ROT transfers N sequential wrds int the /O channel buffer. The cntents f the A Register are the wrd cunt N minlfs ne; ROT can utput t 4096 wrds per executin. The central prcessr must wait as with WOT befre it transfers the first wrd t the buffer; it als must wait fr the buffer t clear between each wrd transfer. ROT cmpletely ties up the cmputer until the Nth wrd transfers int the channel buffer. The next instructin executes befre the Nth wrd transfers ut f the channel buffer t the cnnected peripheral device. Registers Affected: A WN WORD N 11 Timing: 2 + 2N + wait See POT/BPO, PN/BP nstructins in this sectin. DRECT PARALLEL NPUT/OUTPUT, 24-BT (Optinal) A 12-bit register is available t extend the wrd fr POT/PN peratins t 24 bits. Fr a POT, the device perates as fllws: EOM t activate the extender, POT t place the mst significant 12 bits in the extender, EOM t activate the externa device t get the data, and POT t transmit the lwer -12 bits. This last POT transmits the entire 24 bits. WN transfers the cntents f the channel buffer int the effective memry lcatin. f the buffer is nt already fi lied, the central prcessr hangs Upll unti the buffer fi lis with the wrd being received frm the peripheral device. Registers Affected: M Timing: 5 + wait 3-2

25 RN 55 RECORD N Starting with the effective memry lcatin, RN transfers N wrds frm the channel buffer int sequential lcatins. The cntents f the A Registerare the wrd cunt N minus ne; RN can input up t 4096 wrds per executin. The centra prcessr must wait as with WN befre it receives the first wrd frm the channel buffer; it als must wait fr the buffer t fill between each wrd transfer. RN cmpletely ties up the cmputer until the Nth wrd is in memry. This input will als terminate if the cmputer receives an END signal frm the peripheral device befre the Nth wrd. n either case, the cmputer executes the next instructin after RN terminates. Registers Affected: M t M + (A), A / CHANNEL OPERATON Timing: 3 + 2N + wait The /O Channel can cntrl up t 30 input/utput devices; it autmatically handles character, wrd assembly/disassembly, and input/utput parity detectin and generatin. The channel is bi-directinal and cmmunicates with 6-bit character devices (12-bit ptinal). The prgram specifies whether ne r tw characters are t be assembled/disassembled in each wrd during the transmissin. The prgram uses a Buffer Cntrl EOM t set the peratin cntrls such as frward/backward tape directin, t place the unit address in the channel, and t initiate the prper assembly/disassembly mde. The presence f the unit address activates the channel causing it t lk fr data cming frm a peripheral device r frm memry, as determined by the unit address (see the Unit Address Cde, Table 3-1). T get data frm the channel buffer after it is received there frm a peripheral device during input, the prgram uses a WORD N (WN) instructin, r its blck transfer equivalent, r T /O Device : ~~~~~J ~ L RN. T place data int the channel buffer s that the channel can transmit it t the waiting peripheral device, the prgram uses WORD OUT (WOT), r its blck transfer equivalent, ROT. /O CHANNEL BUFFER DESCRPTON (See Figure 3-2.) During the executin f ROT/RN, the cmputer is cmpletely tied up whi e it handles the data transfers, increments the memry lcatin address fr the data transfers, and tests fr transfer terminatin using the wrd cunt N (by decrementing A by ne whenever a wrd is transferred). Each f the 30 devices which can be attached t a buffer has a unique, tw-digit, ctal address by which it is chsen fr an input/utput peratin. T chse the peripheral device, the prgram lads the prper unit address int the 6-bit Un it Address Register (UAR). This address selects bth thedeviceand, if apprpriate, the functin t be perfrmed. Placing a nn-zer unit address in the Unit Address Register "cnnects" the peripheral unit addressed t the buffer and the buffer becmes "active tl When the UAR cntains a zer address, r any time that a terminal r initial cnditin clears the cntents f UAR, the buffer is "inactive", and it is nt cnnected t a peripheral unit. The Wrd Assembly Register (WAR) and the Single Character Register (SCR) cmprise the active prtin f a buffer. The Wrd Assembly Register, a 12-bit, wrd~sized buffer, cntains the wrd f data actively being received r transmitted during an input r utput peratin. During input, 6-bit characters (plus parity) cme int the Single Character Register where the channel assembles them, ne at a time, int the WAR. Depending n the number f characters per wrd specified, the wrd assembled during input has the frm: Parity Wrd Mde One character 1 st Unpredictable per wrd st Errr Character Cunt E1 Wrd Assembly '-- ~ ~ Figure 3-2. SDS 92 Channel Buffer J6 2nd 11 Tw characters per wrd , 5 _J 3-3

26 Table 3-l. Unit Address Cdes 00 Discnnect Type nput N Type Output N Type nput N.2 42 Type Output N.2 03 Type nput N.3 43 Type Output N.3 04 Paper Tape nput N. 44 Paper Tape Punch Output N. 05 Paper Tape nput N.2 45 Paper Tape Punch Output N.2 06 Card Reader nput N Card Punch Output N Card Reader nput N.2 47 Card Punch Output N.2 10 Magnetic Tape nput N Magnetic Tape Output N Magnetic Tape nput N.1 51 Magnetic Tape Output N.1 12 Magnetic Tape nput N.2 52 Magnetic Tape Output N.2 13 Magnetic Tape nput N.3 53 Magnetic Tape Output N.3 14 Magnetic Tape nput N.4 54 Magnetic Tape Output N.4 15 Magnetic Tape nput N.5 55 Magnetic Tape Output N.5 16 Magnetic Tape nput N.6 56 Magnetic Tape Output N.6 17 Magnetic Tape nput N.7 57 Magnetic Tape Output N High-Speed Printer Output N High-Speed Printer Output N ncremental Pltter Output N ncremental Pltter Output N.2 26 Disc File nput N. 66 Disc File Output N Disc File nput N.2 67 Disc File Output N.2 30 Scan Magnetic Tape N Magnetic Tape Erase N Scan Magnetic Tape N.1 71 Magnetic Tape Erase N.1 32 Scan Magnetic Tape N.2 72 Magnetic Tape Erase N.2 33 Scan Magnetic Tape N.3 73 Magnetic Tape Erase N.3 34 Scan Magnetic Tape N.4 74 Magnetic Tape Erase N.4 35 Scan Magnetic Tape N._5 75 Magnetic Tape Erase N.5 36 Scan Magnetic Tape N.6 76 Magnetic Tape Erase N.6 37 Scan Magnetic Tape N.7 77 Magnetic Tape Erase N.7 3-4

27 An unfi lied character psitin is unpredictable. When assembled during a single-wrd peratin, a WN instructin places the wrd int memry. With RN, the cmputer places each wrd in memry when assembled. During utput, wrds cme frm memry int the WAR where the channel disassembles them int the SCR, ne 6-bit character at a time. Depending n the characters per wrd mde specified, the channel transmits the 6-bit characters (with generated parity) as fllws: Functin Output ne character frm bits thrugh 5 Mde One character per wrd The Buffer Cntrl EOM perates essentially as a setup r preparatin facility fr data transmissins r ther peripheral functins using the /O Channel. The nput/output Cntrl EOM directs peripheral devices directly in such peratins as rewind tape and upspace the printer. EOM in the nternal Cntrl mde perfrms internal cntrl peratins such as activating the (ptinal) 24-bit PN/POT extender lgic. The System EOM is specifically cncerned with special systems; the system determines the particular uses. EOM in any f the last three mdes als can alert a device fr a POT r PN type peratin. NOTE: f an interrupt ccurs during the executin f an EOM, n acknwledgement ccurs until the cmpletin f the executin f the instructin fllwing the EOM. Output tw characters frm bits thrugh 5, 6 thrugh 11 Tw characters per wrd Registers Affected: Nne Timing: 3,4 After the first character transfer, the wrd in the WAR shifts left six bits t be ready fr the next transfer, when tw characters frm each wrd are used. Under ROT cntrl, a new wrd cntail")ing the next characterls) cmes t the WAR when it is required. (OM NSTRUCTONS (pcde 00) BUFFER CONTROL EOM (effective address) U N T Designatin Functin BASC CONFGURATON The EOM instructin is a multipurpse instructin that perates in fur distinct mdes with many functinal cnfiguratins. The mdes are Buffer Cntrl, nput/output Cntrl, nternal Functin Cntrl, and System Cntrl. EOM ENERGZE OUTPUT M nstructin Wrd Effective Address! \ The EOM uses the 15 bit cnfiguratins f the effective memry address asa cntrl wrd t select the different cntrl mdes and tselectall additinal cntrl functins. EOM allws a addressing mdes in btaining the effective address. Setting the tw bits (1, 2) in the address determines the mde f the EOM: 2 Cntrl Mde 0 0 Buffer 0 1 nput/output 0 nternal System /N 00 F/R L/N D/B C/W UNT Bit psitin 0 specifies nterlace peratin. A "0" specifies n nterlace peratin. A "1" alerts the nterlace. Bit psitins 1 and 2 cntain the EOM mde indicatr fr the Buffer Cntrl mde. Bit psitin 3 specifies the directin in which the peripheral device perates. A "0" specifies the frward directin. A "1" specifies the reverse directin. Bit psitin 4 specifies whether the device shuld be started with a leader as in paper tape. A "0" specifies a start with leader. A "1" specifies a start withut leader. Bit psitin 5 specifies the mde f character frmat. A "0" specifies BCD frmat. A "1" specifies Binary frmat. When this is nt apprpriate,,bit 5 prvides special cntrl. Bit psitin 6 is unassigned. ' Bit psitin 7 specifies the number f characters t be assembled int, rdisassembled frm, each transmitted wrd. 0 specifies ne character per wrd, 1 specifies tw. One character per wrd, 0, is used fr full-wrd (12-bit characters) transmissin (ptinal). Bit psitin 8 must always be 1. Bit psitins 9 thrugh 14 specify the unit and the functin t be perfrmed with that unit. 3-5

28 NPUT/OUTPUT CONTROL EOM (effective address) UN T ' YNl 1 FUN CT ON 11 Designatin /N 01 FUNCTON UNT Functin Bit 0 specifies nterlace peratin. A "0" specifies n nterlace. A "" alerts the nterlace. Bits 1, 2 specify the nput/output Cntrl mde. Bits 3 thrugh 7 specify cntrl peculiar t each device. Bit 8 must be l. Bits 9 thrugh 14 cntain the Unit Address f the specified device. A Unit Address f 00 refers t the / Channel itself. STANDARD EOM NSTRUCTONS These EOM effective address cnfiguratins have standard uses. DSC DSCONNECT CHANNEL DSC discnnects the / Channel. This instructin uncnditinally sets the UNT Address Register t 00 regardless f whether the channel is currently addressing a device. DSC discnnects any device cnnected t the channel; it uncnditinally makes the channel inactive and clears the errr indicatr. Registers Affected: Nne Timing: 3, 4 TOP TERMNATE OUTPUT ON THE CHANNEL 10 11' During utput when the last wrd f a blck ges t the channel, TOP terminates utput. After executin f TOP, the fllwing ccurs. When the channel del ivers the last character t the peripheral device, the channel discnnects. TOP must always terminate a channel utput peratin. Registers Affected: Nne Timing: 3, 4 TP TERMNATE NPUT ON THE CHANNEL During input when the last (desired) wrd has been stred in memry, T P term i nates input. TP r DSC shuld always terminate a channel input peratin. Registers Affected: Nne Timing: 3, 4 After TP isgiven during an input peratin, the fllwing ccurs: 1. The / channel receives any further characters frm the input device - as befre. 2. All errr checks are perfrmed - as befre. 3. Hwever, the Wrd Assembly Register is never again cnsidered "full". This means: a. nterlace peratins stre n mre wrds. b. Nn-interlace peratins give n mre End-f-Wrd (11) nterrupts. 4. The abve "scanning-type" sequence cntinues until the End-f-Recrd at which time: a. The End-f-Recrd (12) nterrupt is sent (if armed). b. The channel discnnects. c. The channel becmes inactive. ASC ALERT TO STORE NTERLACE COUNT ASC alerts the interlace ptin that the PN t fllw is a request fr the cntents f the current COUNT cntents. The sequence: ASC PN stres the current cntents f the COUNT register int lcatin M. See nterlace Optin, this sectin. NOTE: The abve sequence must be cnsecutive; n ther instructin shuld be interpsed. Registers Affected: Nne SES NSTRUCTONS (pcde 01) BASC CONFGURA non Timing: 3, 4 The SES is a multipurpse test instructin used fr testing respnses t the input/utput channel and attached peripheral devices as well as fr testing internal and external indicatrs. SES SENSE EXTERNAL SGNAL nstructin Wrd i i Effective Address 0 0 s\x! Like the EOM, the SES uses the bit cnfiguratin f the effective address t select the different tests and als perates in fur mdes that are selected by address bits 1 and 2: Test Mde 0 0 Buffer 0 1 nput/output 1 0 nternal 1 1 System When executed, an SES tests fr a specified cnditin and sets r resets the Flag Bit in respnse t the cnditin. The prgram determines the Flag Bit status via ne f the branch-nflag instructins. SES allws all addressing mdes in btaining the effective address. The Buffer and nput/output Test SESs are the cmplement f the Buffer and nput/output Cntrl EOMs; they sense 3-6

29 the cnditins f the / Channel and its cnnected peripheral devices. NPUT/OUTPUT TEST SES (effective address) YN 0 1 CO N D 11 UNT ' Designatin /N 01 COND UNT Functin Bit 0 specifies nterlace peratin. A "0" specifies n nterlace. A "1" alerts the nterlace. Bits 1 and 2 specify the nput/output Test mde. Bits 3 thrugh 7 specify cnditins t be sensed. Bit 8 must be 1. Bits 9 thrugh 14 cntain the Unit Address f the specified device. STANDARD BUFFER SES NSTRUCTONS (effective address) CAT 4 CHANNEL ACTVE TEST; SET FLAG F NOT ACTVE ' f the channel is ready t accept a new input/utput instructin, CAT sets the Flag Bit. f the channel is active, CAT resets the Flag Bit. (The channel wi test active during an input peratineven after the peripheral has terminated its peratin - until all meaningful data wrds in the character buffer have been stred in memry.) Registers Affected: F Timing: 3,4 CET CHANNEL ERROR TEST; SET FLAG F ERROR CET tests the errr indicatr in the /O Channel fr being set. f set t n errr, CET resets the Flag Bit. f set t errr, CET sets the F lag Bit. Registers Affected: F Timing: 3,4 NTERLACE The /O Channel interlace is an ptinal hardware device that can cntrl and perfrm input/utput peratins independent f, and simu taneus with, central prcessr prgram executin. n using the interlace, the prgram sets up a starting address fr data in r ut, sets up a recrd length f the data t be read r written, and starts the interlaced peratin. The prgram then cntinues cmputatin while the interlace mnitrs the /O peratin, accessing memry when necessary, incrementing the data address as needed, and cunting the number f wrds in the recrd. Usually, when the cunt ges thrugh zer, the peratin is cmpleted and the prgram can use the newly entered data and/r can reset the nterlace fr anther independent, /O transm issin. The nterlace cntains tw registers: the 12-bit COU NT register t cntain the recrd cunt and the 15-bit ADDRESS reg ister t cnta in the data address. When lad ing the recrd cunt (N), the prgram places N-l (ne less than the recrd cunt) in the COUNT register. The prgram can use any /O r Buffer Cntrl EOM t "alert" the nterlace fr peratin. A l-bit in bit ps it ins 0 and 8 f the effective address generated by the EOM will alert the nterlace. The standard assembler frm fr alerting the nterlace is an asterisk (*) in the first clumn f the address f the EOM that activates the peripheral device in the /O transmissin. Fr example, t alert the nterlace while activating the magnetic tape unit number 1 t read tape decimal, ne culd write: RTD *1, 2 A special EOM t alert nly the nterlace, ALC ALERT CHANNEL NTERLACE has the address frm 50100; n 11*.. is needed. The PARALLEL OUTPUT (POT) instructin transmits the starting address and recrd cunt t the nterlace. The three POTs" that are needed functin as fllws (RTD * 1, 2 is used as the alerting EOM): RTD *1,2 POT HADDR POT LOWADDR POT NLESSONE (NOTE: This sequence must be cnsecutive; n ther instructins shu d be interpsed.) where: The least significant bits f the cntents f lcatin HADDR frm the high r mst significant three bits f the starting address, the cntents f lcatin LOWADDR frm the least significant 12 bits f the 15-bit starting address, and the cntents f NLESSONE are the recrd length minus ne (N-1). n each case, the POT transmits the infrmatin int the prper nterlace register. The terminatin f an interlace peratin can be determined by using a CAT, CHANNEL ACTVE TEST; r the prgress f an peratin may be mnitred thrugh the use f the ALERT TO STORE NTERLACE COU NT. ASC (10500) alerts the nterlace that a PN is t fllw t get a recrd f the current COU NT cntents. 3-7

30 The sequence: ASC PN M alerts the nterlace and PNs" the current cntents f the COU NT register int lcatin M. The cntents f COU NT are N-1 minus the number f wrds f the recrd already transm itted. /O CHANNEL NTERRUPTS OPTON Tw interrupts 11 and 12 are directly assciated with the /O channel. These are pririty interrupts with 11 having pririty ver 12. When 11 is requested, it interrupts each time the /O channel buffer empties r fi lis; that is, when requested it ccurs n input each time the buffer cllects a wrd, r it ccurs n utput each time the buffer transmits a cmplete wrd. When 12 is requested, it interrupts when an End-f-Recrd ccurs; that is, it interrupts nly after a cmplete recrd is input r utput. 11 and 12 are always enabled (as described in the nterrupt Paragraphs, nput/output Sectin f this manual). A special instructin, EOM 11XOO, arms/disarms these interrupts. The values f X are: X Functin Disarm 11 and 12 3 Arm 11, disarm 12 5 Arm 12, disarm 11 7 Arm 11 and 12 The instructin EOM 13XOO, as a terminate utput EOM, can be used effectively in cnjunctin with the arming feature. Fr "instance, EOM terminates utput, arms 12 and disarms 11. t functins like this: When the current utput frm the /O channel is finished and the Jl buffer is free, the 12 interrupt ccurs. The standard assembler mnemnic and instructin frm is: ARM where X is as described abve. X nterrupts Used with the nterlace Optin During nterlace peratin, the basic interrupts functin accrding t the names they are given belw: 11 is COU NT EQUAL is END OF RECORD When requested, 11 ccurs when COU NT ges thrugh zer. When requested, 12 ccurs when an End-f-Recrd ccurs. On utput r input: f 11 is nt armed, the nterlace terminates the channel (i. e., effects a~ autmatic TOP r TP) when the COU NT ges thrug h zer. Nte: During input, this means that the peripheral cntinues t the end-f-recrd, but n mre input wrds are stred in memry. f 11 is armed, the nterlace des nt terminate the channel n COUNT passing zer; instead an 11 interrupt is generated. This allws the prgram t re-initiate the COU NT and starting ADDRESS in the nterlace and cntinue perfrming the same / peratin. The Channel always discnnects when the endf-recrd ccurs with n regard t the interrupt arms. Nte: When armed by ARM X, an interrupt cnditin ccuring n 11 r 12 causes the interrupt level t g t the Waiting state. f the nterrupt System is Enabled, the respective interrupt will g t the Active state as its pririty perm its. f the nterrupt System is Disabled, the interrupt stays in the Waiting state indefinitely. POT/BPO, PN/BP NSTRUCTONS Tw instructins, PARALLEL OUTPUT (POT) and PARALLEL NPUT (PN), cause any wrd in cre memry t be presented in parallel at a cnnectr; r, inversely, cause signals sent t a cnnectr t be stred in any cre memry lcatin. The executin f a POT r PN instructin causes a signal t be sent t the external device invlved in the input/utput peratin. During a PN, this signal tells the device t send its data wrd as sn as it is peratinal. Wehn a device becmes peratinal duringareadrpn peratin, ittransmitsaready signal t the central prcessr while at the same time presenting its data wrd. The cmputer places the received data wrd int a specified memry lcatin withut disturbing any arithmetic registers. The cmputer hangs Up" during the executin f PN until it receives the Ready signal frm the external device. During the executinfa POT 'instructin, the central prcessr transmits a signal t the external device alerting it t receive a data wrd. When the device becmes peratinal, it transmits a Ready signal t the central prcessr which releases the data wrd t the external device. The cmputer hangs Up" during the executin f POT until it receives the Ready signal frm the external device. The blck transfers frms f these instructins are BLOCK PARALLEL NPUT (BP) and BLOCK PARALLEL OUTPUT (BPO). Special system requirements demand that cmplete wrds f cntrl r data infrmatin be transferred between the central prcessr and the special external devices. The PN r POT preceded by the activating EOM gives exactly this facil ity. The EOM alerts the system device by specific address and the PN r POT transfers the requ i red wrd. That is, the EOM activates andalertsthespecialdevice and the PN/POT transfers 12 bits t r frm the effective memry lcatin specified. T avid a psssible cmputer hang... up", the SES instructin can test the Ready signal f the specia device prir t the EOM and PN/ POT. f the Ready signal frm the external device sets ne f the pririty interrupts (ptinal), parallel input/utput peratin can ccur as sn as the external device is able t transmit r receive. Since the Ready signal initiating the interrupt persists thrugh the POT r PN executin, n hang-upll ccurs. N interrupt can ccur during the executin f, r between any f these instructins and the instructin fllwing it. 3-8

31 POT POT PARALLEL OUTPUT POT transm its the cntents f the effective memry lcatin in parallel t 12 utput lines f an external device. Registers Affected: Nne BPO Y BLOCK PARALLEL OUTPUT 5 Y Timing: 4 +.wait (h igh-speed) and 4,5 + wait Starting with the effective memry lcatin, BPO transfers the cntents f N sequential lcatins in parallel t 12 utput lines f an external device. The cntents f the A Register are the wrd cunt N minus ne; BPO can utput up t 4096 wrds per executin. The utput lines fi and empty under cntrl f BPO and the Ready signa. Registers Affected: A PN PARALLEL NPUT Timing: 3 + N + wait (high-speed) and 2,3 + 2N + wait Pin stres the cntents f 12 input ines in parallel in the effective memry lcatin. Registers Affected: M BP BLOCK PARALLEL NPUT 5 4 Y Timing: 5 + wait (h igh-speed) and 5,6 + wait Starting with the effective memry lcatin, BP transfers N wrds frm the 12 input lines in parallel int sequential lcatins. The cntents f the A Register are the wrd cunt N minus ne; BP can input up t 4096 wrds per executin. The input lines fill and empty under the cntrl f the Ready signal and BP. Registers Affected: M t M + (A), A SNGLE BT NPUT/OUTPUT Timing: 4 + N + wait (h igh-speed) and 3,4+ 2N + wait Operating in the System mde, the tw instructins, ENERGZE OUTPUT M (EOM) and SENSE EXTERNAL SGNAL (SES), prvide single-bit input/utput transmissins. Executin f an EOM (System Mde) causes a 1.15-micrsecnd signal t be transmitted t ne f a pssible 4096 signal destinatins. The system EOM frmat is: SYSTEM MODE EOM (effective address) d Bit psitins 0-2 cntain the System Mde ndicatr. Bit psitins 3 thrugh 14 cntain the address field that specifies the special system destinatins. Registers Affected: Nne Timing: 3,4 SYSTEM MODE SES (effective address) J Executin f an SES (System Test Mde) causes an address t be presented t the cllectin f special system devices. f the addressed external device is supplying a set signal t the central prcessr, the Flag Bit is set. f there is n signal, the Flag Bit is reset. The SES System Test Frmat is identical t the System EOM Frmat. Timing is 3,4 cycles. /O TERMNATON PROGRAMMNG NOTES 1. There is a test t see whether the /O channel is ready t accept a new input/utput instructin - the CHANNEL ACTVE TEST (CAT). 2. Fllwing the terminatin f an input peratin by an Endf-Recrd, the channel remains active until all significant data wrds have been stred by the prgram r interlace. 3. Fllwing the terminatin f a nn-magnetic tape utput peratin by TERMNATE OUTPUT (TOP), the channel remains active unti the last cha racter has been del ivered t the peripheral device. 4. Fllwing the term inatin f a magnetic tape utput peratin by TOP, the channel remains active unti the magnetic tape un it cmmences stpping. Th is is lng after the last character has been del ivered t the magnetic tape un it. 5. The End-f-Recrd (12) nterrupt is never sent unti the /O channel becmes inactive. Thus, an input prgram (using End-f-Wrd, 11, nterrupts fr example) must take care t stre every input character presented t it by the /O channel (in ur example, every 11 nterrupt must result in a W Nil r "DSC" r "TP"). f nt, the input devicewill prceed t End-f-Recrd and stp, but n 12. nterrupt will ever be given and the channel will never g inactive. The prgrammer has several ptins after he has read as much f a recrd desired: " 1. Discnnect (DSC) - but nt if the peripheral device is a magnetic tape. 2. D nthing - but nly if n mre wrds remain in the recrd (i.e., the entire recrd has been read). 3. Give TP - the input peripheral device wi" cntinue t End-f-Recrd with all nrmal errr checks n the remainder f the recrd. 3-9

32 4. TERMNATE NPUT (TP) and TERMNATE OUTPUT (TOP) have the same ctal cnfiguratin - the /O channel differentiates TP and TOP accrding t the type f peratin it is perfrming. 5. The prgrammer can have n prblem by giving a TP when the input device is cncurrently sending an End-f-Recrd signal r when the channel is already inactive. 6. mprper prgramming (especially n input) can leave the /O channel in an active state. THE 11 NTERRUPT A nn-interlace, nn-character-interrupt /O prgram shuld disarm the 11 nterrupt. f this disarming is nt effected, spurius 11 nterrupts may result: 1. On utput, the first l nterrupt is generated immediately fllwing the activating EOM. 2. During ROT/RN (and WOTjWN), l nterrupts may be generated -even thugh the /O channel is being prperlyattended t by the ROT/RN cmmand. This disarming des nt create many prgramming prblems r cmpatibility prblems-the RESET buttn clears bth /O channel interrupt arms. Thus, nly prgrams which use bth the interrupt and the nn-interrupt mdes f /O prgramming need take heed. PRORTY NTERRUPT SYSTEM (Optinal) NTRODUCTON As an ptin, the SDS 92 may cntain a pririty interrupt system. This system prvides added prgram cntrl f input/ utput peratins, aids in prgramming multiplexed peratins, and'allws immediate recgnitin f special external cnditins. When an interrupt is received, the internal lgic examines the interrupt signal and causes the cmputer t interrupt the prgram sequence at the end f the executin cycle f the current instructin. Withut disturbing the Prgram Cunter Register, the cmputer transfers prgram cntrl t ne f a selected set f memry lcatins. One f the branch and mark place BRM r BMC instructins in this lcatin saves the cntents f the Prgram Cunter, Flag, and PCT. t als transfers t the particular interrupt servicing rutine required. This enters the prper service rutine since each interrupt has a unique interrupt lcatin. T exit frm the rutine, a BRANCH AND CLEAR NTERRUPT (BRC) instructin using indirect addressing returns cntrl t the next instructin in prper sequence in the main prgram; it als clears the interrupt and restres the riginal cntents f the Flag and PCT. The pririty interrupt system has up t 256 System interrupt levels. The levels, numbered evenly upward frm 200a, have pririty accrding t number, with the higher pririty levels having a smaller number. Additinal interrupts btained with SDS ptinal hardware are lcated at interrupt levels numbered frm 150a. n general, these als have pririty accrding t number. Nte that interrupts 150 thrugh 176 have pririty ver any System interrupt (200 r mre). When an interrupt has ccurred and its service subrutine has been entered, an interrupt f higher pririty can interrupt the subrutine and gain prgram cntrl fr the servicing f its mre imprtant peratin. But an interrupt f lwer pririty cannt interrupt an interrupt-prcessing subrutine f a higher level. Thus, the pririty interrupt system allws interrupts t be arranged accrding t their imprtance and/r accrding t their need fr speedy servicing. The abve type f interrupt is called a nrmal pririty interrupt t differentiate it frm anther interrupt feature, the singleinstructin interrupt. This is a different kind f interrupt that causes the executin f nly ne instructin befre autmaticallyclearing itself and returning t the prgram which it interrupted. f the executed instructin is a branch instructin which branches (i.e., BRM r BMC), the interrupt is cleared but cntrl des nt return t the interrupted rutine. Th is type f interrupt needs n branch instructin t clear it. Fr example, by cnnecting an external clck surce t the cmputer, the prgram can maintain a prgrammed real-time clck. Each time the external pulse causes an interrupt, the prgram executes the single instructin, MEMORY PLUS ONE TO MEMORY, t add ne t the selected memry wrd. The main prgram examines this lcatin whenever necessary t determine hw many time increments have elapsed since the clck was started. N new interrupt can ccur between any singleinstructin interrupt and the return t the main prgram. Any f the ptinal, system interrupts can be single- r nrmalinstructin interrupts in any cmbinatin desired. PRORTY NTERRUPT OPERATONS A nrmal pririty interrupt level has three peratinal states: nactive, Wai ting, and Active. n the inactive state, n interrupt signal has been received int the level and nne is currently being prcessed by its interrupt servicing subrutine. N recrd is maintained if the interrupt cannt g int the waiting state. n the waiting state, an interrupt request signal has been received int the level, but is nt being prcessed. This situatin may be due t an interrupt f higher pririty being prcessed at this time. When the system is enabled and all higher waiting interrupts have been prcessed, this level ges t the active state. n the active state, the interrupt has been acknwledged, meaning it has caused the main prgram t recgnize its presence and has transferred t its assigned interrupt lcatin and/r rutine where it is being prcessed. When the interrupt prcessing is cmpleted, executin f a BRANCH AND CLEAR (BRC) sets the interrupt level t the inactive state. A single-instructin interrupt perates in the same way as the nrmal pririty interrupt in the inactive and waiting states. Hwever, when acknwledged, this interrupt enters the active 3-10

33 state, and remains there during the executin f ne instructin. At the cmpletin f the ne instructin, the single-instructin interrupt returns t the inactive state withut the aid f a branch and clear instructin. NTERRUPT CONTROL Tw prgram cntrl features are available in the interrupt system. These features are Enable/Disable and Arm/Disarm. Arm/Disarm (ptinal hardware) cntrls whether an interrupt can prceed frm the inactive state t the waiting state. The disarm cnditinfan interrupt level prhibitsan interrupt signal entering the level frm causing the interrupt t enter "waiting" frm inactive ll With Enable/Disable, the entire set f interrupts in the system can be enabled and disabled under prgram cntrl. When the interrupt system is enabled, interrupts can prceed frm the waiting state t the active state l 1177 Table 3-2. nterrupt Lcatin Assignments Pwer On (always armed) Pwer Off (always armed) Main Frame Parity Errr (armed via a cnsle switch) Data Multiplexing System Parity Errr (armed via a cnsle switch) Unassigned Unassigned nterrupt, Clck Sync (always armed) nterrupt, Clck Pulse (arm furnished) 11 (arm furn ished) 12 (arm furnished) Unassigned Unassigned System nterrupts (arms ptinal, single instructin discretinary) l System nterrupts The fllwing interrupts are exceptins and are always enabled: 1. Pwer fa ii-safe (2 interrupts) 2. Memry parity errr (2 interrupts) 3. Real-time clck (2 interrupts) 4. /O Channel (2 interrupts) The cntrl f the ptinal Arm/Disarm feature perates n individual interrupt levels f the System interrupts ( ), that is, any chsen interrupt level may be selectively armed r disarmed. But the instructin structure fr Arm/Disarm allws these interrupts t be perated n in grups f sixteen. SNGLE NSTRUCTON NTERRUPTS ROUTNES Only the fllwing instructins will be meaningfully interpreted as single-instructin interrupt rutines: 1. EOM 2. BMC, BRM 3. MPO - MPO, in this case, will nt alter the Flag. Hwever, if the restred, incremented perand equals 00008, a different interrupt pu se wi be generated (see Real-Time Clck Optin, Appendix B-1). 4. EXU - Can nly execute the abve-listed instructins. NON-NTERRUPTABLE NSTRUCTONS An interrupt cannt ccur between the executin f ENERGZE OUTPUT M (EOM) and the instructin fllwing it. This is als true fr the input/utput instructins, POT/BPO, PN/BP, WOT/ROT, and WN/RN. N interrupt can ccur between a single-instructin interrupt and the return t the main prgram. When these instructins branch, an interrupt cannt ccur between their executin and the executin f the branch-t instructin: BRU BRL BDA BAX BFF BFT ENABLE/DSABLE NTERRUPT NSTRUCTONS Three instructins are available fr setting, resetting, and testing the state f the NTERRUPT ENABLED indicatr. ER 00 ENABLE NTERRUPT 5 6 ER uncnditinally sets the NTERRUPT ENABLED indicatr and enables the interrupt system. At the end f the next interruptable instructin, if any interrupt levels are waiting, the ne with the highest pririty becmes active. ER cannt be interrupted. Registers Affected: Nne DR DSABLE NTERRUPT Timing: 3,4 DR uncnditinally resets the NTERRUPT ENABLED indicatr and disables the interrupt system. The current state f all interrupt levels is unchanged by this instructin. DR cannt be interrupted. Registers Affected: Nne Timing: 3,4 let 01 NTERRUPT ENABLED TEST; SET FLAG F NTERRUPT SYSTEM ENABLED f the pririty interrupt system is enabled, let sets the Flag Bit. f the pririty interrupt system is disabled, let resets the Flag Bit. Registers Affected: F Timing: 3,

34 ARMNG FEATURE The arming feature is cntrlled fr a grup f 16 interrupts at ne time. (The 24-bit POT/PN ptin is a prerequisite fr the arming feature. ) The sequence f instructins required t arm the selected interrupts is: EOM POT AR HTWELVE Alert the extender Lad mst significant 12 bits int extender Arm interrupts POT LOWTWELVE Transmjt entire 24 bits t the arming chassis and arms selected interrupts EXTENDER ALERT EOM The Extender EOM alerts the extender t accept the next POTted"wrd. AR alerts the arming chassis that a 24-bit cntrl wrd is cming with the POT that fllws. The secnd POT triggers the entire 24-bit transmissin. The effective address f the Extender Alert EOM (an internal type) is: AR 2 4 ARM NTERRU PTS AR prepares the arm interrupt cntrl unit t receive a cntrl wrd fr a grup f 16 interrupt levels. A PARALLEL OUTPUT (POT) must always fllw AR, r an unpredictable peratin results. AR cannt be interrupted. Registers Affected: Nne Timing: 3,4 The tw wrds which the PARALLEL OUTPUT (POT) instructins address have the fllwing frmat: High-Order 12-bit Wrd Address 56 Lw-Order 12-bit Wrd 12 Select Bits nterrupt The address field in bit psitins 0 thrugh 5 identifies wh ich grup f 16 interrupts in the system is being addressed. The C field cntrls what is dne t the particular interrupt levels selected in bit psitins 8 thrugh 23. Bit psitin 8 refers. t the lwest-numbered level f the grup, therefre the ne with the highest pririty. Bit psitin 23 refers t the last r highestnumbered level, the ne with lwest pririty. The first grup f 16 is grup 0, Fr example, wrds f 0024 and 0000 arm level number 202 (the level f secnd highest pririty), The cntrl peratins are: 6-7 Functin 00 Nt used Arm all interrupt levels that are selected by a 1 in bit psitins 8-23 Disarm all interrupt levels that are selected by a in bit psitins 8-23 Arm all interrupts selected by a 1 and disarm all interrupts selected by a 0 in bit psitins NACTVE +, Prceed if ARMED + WATNG + Prceed if ENABLED ACTVE + Prceed if PROPER PRORTY Figure 3-3. nterrupt Arm-Enable Respnse 3-12

35 CONTROL CONSOLE The basic cmputer system includes a cnsle fr peratr cntrl. This cnsle cnnectsdirectly t the central prcessr, cntains switches fr peratin, and displays the cntents f peratinal registers. DSPLAYS The registers displayed n the cnsle directly reflect the cntents f the hardwa re reg isters. f the peratr clears r changes a display, the cntents f the actual reg ister change identically. PROGRAM LOCATON This display cnsists f 15 binary indicatrs with a CLEAR buttn fr the entire register and a set buttn fr each indicatr. The prgram cunter cntains the lcatin f the next instructin t be executed. The peratr may change the cntents f the prgram cunter via the CLEAR and set buttns. When the peratr places the cmputer in RU N, the first instructin cmes frm the lcatin shwn in the PROGRAM LOCATON display. NPUT -OUTPUT The UNT lights cntain the unit address f the peripheral device currently cnnected t the /O Channel. The ERROR ight reflects the status f the /O Channel errr indicatr. HALT The HALT light lights whenever the cmputer executes a halt instructin while in the RUN psitin. Setting the RUN/DLE/ STEP switch t DLE clears the halt. REGSTER DSPLAY This display cnsists f 12 binary indicatrs with a CLEAR buttn fr the entire register and a set buttn under the P Register indicatrs that als serve the A, B, and C Registers. The Register switch selects the internal register t be displayed. The selectable registers are: C A B C Register, which usually cntains the cntents f the memry wrd whse address is in the prgram cunter A Register B Register Placing the cmputer in DLE, clearing the register, and then pressing the buttn in the crrespnding bit psitins under the indicatrs sets the cntents f the selected register. Pressing a buttn places a 1-bit int the selected psitin f the register. MEMORY PARTY f an perand r instructin access frm memry encunters a parity errr and the memry switch is in the HALT psitin MEMORY PARTY lights. Setting the memry parity switch t CONTNUE clears the indicatr and turns ff the light. ENABLE ENABLE lights whenever the interrupt system is enabled. FLAG The FLAG indicatr cnsists f a single binary indicatr. FLAG is lit when the Flag Bit is a 1. SWTCHES POWER The POWER switch turns the cmputer system pwer n r ff. When pwer is n, the switch is it. FLL T initiate a fill ", 1. Press the RESET buttn. 2. Hld dwn the FLL switch crrespnd ing t the peripheral dev ice frm wh ich a fi is desired. 3. Mve the RUN/DLE/STEP switch frm DLE t RUN while cntinuing t hld the apprpriate FLL. 4. Release the FLL switch. Fill causes the fllwing: 1. An EOM pcde is generated. Bit 0 = 0 Bit 1 =0 Bit 2 = 0 ~ Buffer Cntrl Mde Bit 3= 0--- Frward Directin Bit 4 = 0 Bit 5 = ~ Binary Mde Bit 6 = 0 Bit 7 = 1 ---~. Tw Characters per Wrd Bit a = 1 Bit 9 - Bit 14 = The unit address f the indicated peripheral: Paper Tape Cards Mag Tape Disc 04a 06 a loa 26 a 3-13

36 --flll-- NT(RRUPT ---- NPUT OUTPUT ---- REGSTER DSPLAY UNT HALT (NABLEO [RROR W PAP(Jt MEMORY TAPE CARDS PARTY flac PROGRAM loc. lion HO RESE T.l>-.. AC O"UM CLUt TAPE =1 " " " NCRE MENT NTERRUPT RUN - HALT RE SET DLE CONTNUE p. SET STEP. BREAKPONT OtH MEM ORY Figure 3-4. SDS 92 Cmputer Cntr l Pnel

37 2. 9 wrds (r t End-f-Recrd) read int memry starting in lcatin Cmputatin begins at lcatin NOTE: The /O Channel is still active and the input peripheral device is sti sending characters t the channel. (f the fill rutine is less than 9 wrds, the End-f Recrd makes the channe inactive; cmputatin sti ges t ) RUN/DLE/STEP The RUN/DLE/STEP switch is a three-psitin, tggle switch with tw statinary psitins and a spring-laded mmentary psitin in STEP. n the RU N psitin, cmputatin ccurs at machine speed. n the DLE psitin, the cmputer idles immediately after an instructin has been read frm memry. f the Register switch is in the C psitin, the first wrd f an instructin may be viewed in the REGSTER DSPLAY. Depressing the switch t STEP reaccesses and executes the instructin; the cmputer returns t the dle state. T "step" anther instructin, the peratr releases the switch t the DLE psitin and then depresses it again t STEP. N interrupts can ccur (i.e., g int the active state) while stepping. HOLD/NCREMENT Placing the HOLD/NCREMENT switch in the "up" psitin causes the current cntents f the prgram cunter t be held. This inhibits the prgram cunter frm cunting. Mmentarily placing the HOLD/NCREMENT switch in the NCREMENT psitin increments the prgram cunter by ne and brings the cntents f the newly addressed lcatin t the C Register. RESET This switch initializes the cntrl sectin f the cmputer. t resets the /O Channel, clears the FLAG, sets PCT, clears the NTERRUPT ENABLED, clears any parity errr indicatin, clears all interrupts arms, and clears a interrupt levels. The peratr must set the RUN/DLE/STEP switch t DLE befre pressing this switch. Switch Select This tw-psitin tggle (labeled C and P) selects which REG STER DSPLAY/PROGRAM LOCATON will be affected by the C LEAR and set buttns. Register Select This three-psitin switch selects the register t be shwn n the REGSTER DSPLAY lights. MEMORY PARTY n the HALT psitin, this switch causes the cmputer t enter the dle state whenever a memry parity errr ccurs. n the CONTNUE psitin, the cmputer des nt change state when a memry parity ccurs. n the NTERRUPT state, any memry parity will result in ne f tw interrupts (ptinal). BREAKPONT The fur BREAKPONT switches are externally cntrlled, internally testable prgram switches. Breakpint test instructins test them. MEMORY OUT This is a mmentary switch that causes the cmputer, in DLE, t place the cntents f the lcatin specified by the prgram cunter int the C Register. MEMORY N Th is is a mmentary swi tch that causes the cmputer, in D LE, t place int the lcatin specified in the prgram cunter fhe cntents f the C Register. PERPHERAL EQUPMENT DESCRPTON This sectin describes sme f the input/utput devices thatcan be attached t a buffer and explains their use. NPUT/OUTPUT TYPEWRTER The cntrl cnsle may cntain an electric, input/utput typewriter fr peratr cntrl, errr r status messages, and similar functins. The typewriter cnnects t the /O Channel, has the input unit address 01, and the utput unit address 41. Appendix 1-1 cntains the typewriter cdes. The typewriter cntrl instructins fllw. The sample instructins use Typewriter N. 1 with 2 characters per wrd mde. RKB 1,2 READ KEYBOARD 2 Characters/Wrd 02301t This instructin activates the /O Channel and cnnects t it Typewriter N. 1. RKB readies the channel t read input frm the keybard. This instructin lights the input light n the typwriter. TYP 1,2 WRTE TYPEWRTER 2 Characters/Wrd This instructin activates the /O Channel and cnnects t it Typewriter N.1. TYP readies the channel t write utput t the typewriter. t This ctal number is the EOM r SES effective address cnfiguratin. 3-15

38 EXAMPLE: Typewriter Output This example types the fllwing message: DO frm lcatin OUTWD; the internal cdes fr these characters are in this lcatin. The rutine uses Typewriter N.1; the rutine assumes the channel t be initially inactive. Lcatin nstructin Cmments N RES 2 This assembler directive reserves tw lcatins fr the mark entry. TYP 1,2 This EOM instructin cnnects Typewriter N. 1 t the channel fr utput and spec ifies tw characters per wrd. The ctal cnfiguratin f the EOM address is WOT OUTWD This instructin transfers the cntents f lcatin OUTWD t the /O Channel. The new cntents f the channel are utput t the typewriter as tw 6-bit charactersand typed. The next instructin in sequence is executed as sn as the wrd is placed in the channel. TOP Th is instructin terminates utput n the channel. When the channel and the Sing e Character Register are c lear f characters t be utput, the channel sets its Unit Address Register t zer; th is discnnects the channel. When accessed, this instructin executes immediately; the next instructin in sequence is then executed. The ctal cnfiguratin f this EOM address is BRU *N This instructin transfers t sme ther prgram area. OUTWD This wrd cntains the internal cde fr the characters DO. EXAMPLE: Typewriter Output then nput This example types ut the message: PROG then awaits the input f a single character. nput terminates with a carriage return typed by the peratr; the husekeeping necessary t determine when the carriage return has been input is nt given. N TEST RES TYP WOT WOT TOP CAT BFF RKB WN 2 1,2 MSSGE MSSGE+l TEST 1,1 KEYWD Cnnect channel t Typewriter N. 1. Output first wrd f message. The central prcessr "hangs Up" n this instructin until the secnd character frm the preceding instructin has cleared the channel buffer int the Single Character Buffer fr utput. Then this WOT executes filling the channel buffer with cntents f lcatin MSSGE + 1. Terminate utput when channel system is clear. The prgram "hangs Up" here unti the channel transmits the last character. This instructin cnnects Typewriter N. 1 t the channel fr input and specifies ne character per wrd. The ctal cnfiguratin is The cmputer "hangs Up" n this instructin until a characterentersthechannel frm the keybard; then the wrd in the channel buffer is placed int lcatin KEYWD. The input character is in bit psitins 0 thrugh 5 f KEYWD. Bit psitin 6 thrugh 11 are unpredictable At this pint, the wrd in KEYWD is placed elsewhere in memry and the rutine returns t the WN abve. When executed, a test is made t determine if the new input character is the carriage return cde. ndexing r indirect addressing can be used with the WN t facilitate input. When the carriage return is detected, the fllwing is executed. DSC BRU *N This instructin discnnects the channel by immediately clearing the Unit Address register t zer. The cta cnfiguratin f the EOM address is Return t main prgram. 3-16

39 PAPER TAPE NPUT/OUTPUT Frmat The paper tape used is ne-inch wide, affrding space fr eight data hles and a sprcket hle in each frame f infrmatin. There are ten frames per inch f paper tape. Six hle psitins are used fr infrmatin, ne is used fr an dd parity check, and the eighth is unused. frames). Bit psitin 4 f the EOM that addresses the punch cntains a "0" t punch leader; bit psitin 4 cntains a "1" t punch withut leader. The EOM instructin that addresses and alerts the punch prduces gap. N terminal punch peratin prduces gap after punching a blck. The punch perates asynchrnusly. f the channel des nt supply characters t the punch fast enugh, the punch waits fr each character, lsing n data and creating n errrs. p B A B '0' '0. ' i ~ Directin f Travel Blck f nfrmatin nfrmatin is rganized n the tape in blcks. A blck is a grup f frames set ff by a gap f at least ne blank frame (in which nly the sprcket hle is punched) at either end. Blcks may be f variable lengths. n sme peratins, a tape may cnsist f nly ne blck, such as a surce language tape prepared ff-line. n this case, the prgram need nt read the entire blck at ne time, but may stp the reader between frames, by discnnecting via DSC, and then start again t read the remainder r anther prtin f the blck. Prgramming There are n status tests fr the reader r punch, that is, they are always ready fr peratin. When the channel addresses either device, the device starts t send r accept data within apprximately ne character time. The reader and punch perate nly in the binary mde and the frward directin. The reader r punch ignres any different mde specified, and uses the frward-binary mde. Unit address f 04 is fr Paper Tape Reader 1, and unit address 44 is fr Paper Tape Punch 1. Paper Tape nstructins The fllwing instructins use the /O channel, Paper Tape Number 1 with tw characters per wrd frmat. RPT 1, 2 READ PAPER TAPE This instructin initiates a paper tape read peratin n tape read statia number 1 cnnected t the channel in the tw characters per wrd frmat. A prgram reads paper tape in a straightfrward way, using RN r a WN in a read lp unti the desired number f wrds are input r until gap is detected. The tape stps in less than n~ frame; this means that n frame is missed between subsequent read peratins. An input peratin that terminates because f gap (End-f-Recrd) stps the tape after the first blank f the gap. When starting the tape fr reading, the tape reader ignres any leading blank frames. After reading a meaningful data wrd (ne r tw characters as defined by the prgram) frm the tape, the reader recgnizes the next blank frame as gap and signals the channel with an End-f-Transmissin indicatin. Punching The EOM t alert the tape punch als turns n the punch mtr (if nt already n). f the punch instructin (EOM) s indicates, the punch unit punches a segment f leader (gap, r blank PTL 1, 2 PUNCH PAPER TAPE WTH LEADER This instructin initiates a paper tape punch peratin n tape punch statin number 1 cnnected t the channel in the tw characters per wrd frmat. t generates apprximately twelve (12) frames f leader preceding the first punched frame. PPT 1, 2 PUNCH PAPER TAPE WTHOUT LEADER This instructin initiates a paper tape punch peratin n tape punch statin number 1 cnnected t the channel in the tw characters per wrd frmat. t generates n leader preceding the first punched frame

40 EXAMPLE: Punch Paper Tape This rutine punches ne blck f eight wrds (16 characters) frm lcatins thr~gh precedes the blck. The rutine is a clsed subrutine. Lcatin nstructin Address Cmments A twelve-frame leader FRST RES 2 This instructin is an assembler mnemnic used fr cnvenience t reserve the subrutine entry lcatins. PTL 1,2 This instructin cnnects the channel t Paper Tape Punch N. 1 and specifies tw characters per wrd mde. The instructin asks fr leader t be punched. The ctal cnfiguratin fr this EOM is LDA =7 This instructin sets (A) equal t 7. ROT This instructin transfers each wrd as needed t the channel beginning in lcatin TOP This instructin is executed in 4 r 5 cyc les and then the cmputer executes the next instructin. The executin f TOP causes the channel t discnnect when the last character shifts ut f the buffer and transmits ut f the Sing e Character Register. BRU *FRST This instructin returns t the main prgram. EXAMPLE: Read Paper Tape This rutine reads a 64-character blck frm paper tape int memry beginning at lcatin The rutine uses the tw character per wrd mde, making the input 32 wrds. The rutine is a 'c lsed subrutine. FRST RES 2 This assembler instructin reserves the entry lcatins. RPT 1,2 This instructin cnnects t the channel the Paper Tape Reader N. 1 and specifies tw characters per wrd mde. The cta cnfiguratin fr this EOM is LDA =33 The 33 represents tw mre than the expected recrd size. RN This instructin receives each wrd in the blck beginning in lcatin and ging thrugh 02037, 8 When the channel detects the End signal (gap) fllwing the blck during the input transmissin, the RN finishes executin and the cmputer ges t the next instructin. CARD NPUT/OUTPUT Frmat The cmputer uses 80-clumncards in tw frmats: Hllerithand binary. The reader reads Hllerith-cded infrmatin frm cards and the crrespnding SDS character cdes g int memry. n th is mde, each card clumn cntains the equivalent f ne 6-bit internal character. The character cdes are in Appendix -l. Binary-cded infrmatin ges nt the card with tw 6-bit characters per clumn. n binary mde, ne clumn frms a wrd. The reader reads the card frm clumn 1 t 80 in a tp-bttm rder. A single card hlds 160 characters. Figure 3-5 shws the relatin f Hllerith infrmatin n a card and in memry. Reading The card reader scans the card, clumn by clumn, starting with clumn ne, and transmits either 80 r 160 characters depending n the mde f peratin. With pwern and cards in the hpper, the peratr readies the reader by pressing the START buttn. During prgram peratin, the prgram must test fr the Ready cnditin befre initiating a card-read. A Read EOM instructin starts the card-reading peratin; then the prgram cntrls the flw f infrmatin int memry via a RN r WN lp. The end f the card sets the End-f-Recrd cnditin. n the Hllerith mde, any clumn-read that is nt punched in ne f the 64 cmbinatins listed in Appendix 1-1 results in a Validity check. Presence f a Validity check causes an errr signal t be sent t the channel and lights the VALDTY CHECK ight n the reader. f the stacker shu d becme fu, r the hpper empty, the reader ges Nt Ready and ights the NOT READY light. The card reader remains in the Nt Ready state until the peratr crrects the situatin and presses the START buttn. Upn reading the last card, the reader sets an End-f File signal if its EOF ON switch is n. The central prcessr can test the End-f-Fi e signal which determines if mre cards are in the hpper. Punching The punch punches cards a rw at a time, starting with rw 12. The punch cupler in bth Hllerith and binary mdes autmatically rearranges the infrmatin t be punched. The card punch prgram must present the entire image, 80 r 160 characters, t the punch 12 times fr each card. The punch perates in the fllwing manner. As each rw f the card appraches the punch statin, the cupler examines every character f the image t determine which clumn psitin in that rw shu d be punched. After the 12th utput, the punch punches rw 9 and cmpletes the card cyc e. The card punch is Ready t punch if there are cards in the magazine, the stacker is nt full, and the START buttn has been 3-18

41 ~CD _... Card A C> ~ ~ U ,...,... ~ - c::> = - c... en c.n c....., ~ = CD... O'J.,.. 00 en c.n... -~_ (,,(,0 01)... c.n :~c;t CD c... a" U1.,.. r-~ ~... ~ =_ CO... c.n... =0<.:0 CD en c.n... ~Nc.c c -." en c.n <.0 CO en c.n... ~ (Q CD... 0') c.n., , c; CD g -.. en - c.n... -N g; (l:) CO "... en ~CD c -... en c.n en c.n... C>..., ~ CD O'J c.n... ~c:.... C') c.n Cn"" '"'" ~ - i:j... c.n... t..) ~... ""... c.n... c,...) C=> ""...,cnc.n.,..w...:.-c..., en W N - ~ W Q t.: '-0 QO c..n... w t;'j <"" "" ti W f:) = = ~~ e... en c.n ~ W ::;:<.0 0:> w ~ - c:::)... c.n"" W N - = t CD (X... en c.n W c.n... c..,) r-.,) D.:..::. ~U)... Q ~ :: CD g... ext... en c.n... c.." ex)... en c.n.,.. w c.n CX'... C') c.n... w == "" _ = c.n e!u:) Cr:)... en <.n.-. Ct.) <;;'-0 c -.. c.n"" Ct.) ~c. c -.t en U" -:jq -!!- N ~ _u: -~ VJ.--i -:!."> :;0-0 ;.0 - B Memry S T A R -i B ; T C R ~ ~ T.t; , B Figure 3-5. Card Read nt Memry in Hllerith pressed. The punch remains Ready as lng as the abve cnditins are true. A punch card instructin given when the punch is Ready causes a card t feed past the punch statin. The prgram must then give the same instructins 12 times t transmit the card image t the cupler. Prgramming nstructins The card reader instructins belw use unit number 1 with the tw characters per wrd transmissin mde. CRT 1 CARD READER READY TEST This test determines if the selected card reader is Ready t read. f the reader is Nt Ready, the cmputer resets the Flag Bit. CFT 1 CARD READER END-OF-FLE TEST This test determines if the End-f-File cnditin frm the card reader has been detected. f nt, the cmputer sets the Flag Bit. f the EOF cnditin has been detected, the cmputer resets the Flag Bit. The reader remains in the End-f-Fi e cnditin unti cardsare added t the hpper r until the EOF ON switch is turned ff. RCD 1,2 READ CARD DECMAL (Hllerith) RCD alerts the card reader, causes a card t feed frm the hpper, and selects the Hllerith mde (as each clumn is read, it is translated t an SDS internal cde). This mde reads up t 80 characters (40 wrds) frm a card. RCB 1,2 READ CARD BNARY RC B a erts the card reader, causes a card t feed frm the hpper and selects the binary mde (as each clumn is read it is transmitted as tw 6-bit binary characters). This mde reads up t 160 characters (80 wrds) frm a card. Card Punch nstructins CPT 1 CARD PUNCH READY TEST This test determines if the selected card punch is Ready t punch. f s, the cmputer sets the Flag Bit. f the punch is Nt Ready, the cmputer resets the Flag Bit. The peratr makes the punch Ready by placing blank cards in the magaz ine and pr-essi ng the START buttn. PC D 1,2 PUNCH CARD DECMAL (Hllerith) PC D alerts the punch, causes a card t feed past the punch statin and selects the Hllerith mde. A transmissin f 80 characters (40 wrds) must fllw this instructin. The instructin PC D fllwed by the transmissin instructins fr 80 characters per card must be repeated 12 times. PCB 1,2 PUNCH CARD BNARY PCB alerts the punch, causes a card t feed past the punch statin and selects the binary mde. A transmissin f 160 characters (80 wrds) must fllw this instructin. The instructin PCB fllwed by the transmissin instructinsfr 160 characters per card must be repeated 12 times. 3-19

42 EXAMPLE: Card Read This prgram reads ne card in Hllerith mde. t is a clsed subrutine. The prgram enters the rutine via a BRM. Lcatin nstructin Address Cmments FRST RES 2 This assembler instructin reserves lcatins fr the subrutine entry. TEST CRT This instructin is the card reader Ready test fr Card Reader Number 1. t sets the Flag Bit if ready. BFF TEST This instructin branches back t the test n Nt Ready. An exit t a Nt Ready crrective rutine can be put here. RCD, 2 This instructin cnnects the Card Reader 1 and starts a card mving tward the read statin. Hllerith mde is specified. The ctal cnfiguratin fr this instructin is LDA =39 This is the repeat cunt fr RN. RN READ Beginning in READ, this instructin transfers wrds frm the channel int the lcatins until the entire card is read. BRU "'FRST This instructin branches back t the main prgram. EXAMPLE: Card Punch The prgram punches ne card in Hllerith mde beginning frm lcatin the prgram presents the card image t the punch. The B Register cunts the 12 times FRST RES 2 This instructin reserves the lcatins fr the subrutine entry. LDB =11 TEST CPT This instructin tests the card punch fr a Ready cnditin. t sets the F lag Bit if Ready. BFF TEST This instructin branches back t the test, CPT, if the Flag is reset. An exit t a time lp with.the facility t tell the peratr that the card punch wi nt becme Ready can be placed here. GEE PCD, 2 This instructin executes if the punch is Ready. t cnnects the channel t the Card Punch Number, and starts a card mving tward the punch statin. The tw characters per wrd and Hlleriih mde are specified. LDA =39 Starting with lcatin 03740, ROT transmits 40 wrds t the Punch. ROT TOP This terminates utput. CTEST CAT Wait fr the last character t be transmitted. BFF CTEST SUB =1 SUB decrements (B) by ne and sets F if the new (B) is equal t , BFF GEE Nte that the card image must be sent t the channel twelve times t punch a card. BRU *FRST Return t main prgram via lcatin FRST. 3-20

43 MAGNETC TAPE NPUT/OUTPUT Magnetic tape units used in SDS cmputer systems are BMcmpatible. The tape is ne-half inch wide, Mylar base material, 1.5 mils thick. Tape reels (10 1/2 inch, plastic) cntain up t 2400 feet f tape. A reflective marker, placed n the back f the tape apprximately ten feet frm the beginning f it, indicates the lad pint. The leading ten feet leave space fr threading tape thrugh the guides n the unit. The lad pint marker is n the My-ar side f the tape alng the edge nearest the peratr when the tape is munted. A similar marker is alng the ther edge f the tape t mark the end-freel. Abut 14 feet f tape are reserved between the end-freel marker and the end f the tape. This space includes at least ten feet f leader and enugh tape t hld a recrd f 9,600 characters in 200 bpi density after the end-f-reel marker is sensed. The lngitudinal check character always reflects an even parity check fr each channel. n the BCD mde, the check character itself always has an even number f 1-bits. n the binary mde, hwever, the check character may have either an even r an dd number f 1-bits. This means that a reverse scan ver a binary recrd may result in turning n the errr indicatr in the buffer even thugh the recrd itself is crrect. As a general rule, the prgram ignres the errr indicatr after a reverse peratin. Rutines shuld always place a TAPE READY TEST (TRT) between tape peratins f ppsite directin t ensure that the tape unit stps and reverses. Gd prgramming terminates tape writing by several inches f erasure whenever subsequent resumptin f recrding is anticipated. This eliminates the effects f a pssible extraneus character that might arise thrugh subsequent tape repsitining. Characters are recrded n tape in seven parallel tracks. A change in the magnetic flux in a track recrds a 1-bit fr a given character psitin. N change in magnetic flux indicates a O-bit. Six f the tracks cntain infrmatin; the seventh track is a parity check. The system allws bth even and dd parity, as needed. Binary recrding uses dd parity. n this mde, the tape recrds the six-bit charcicters frm memry withut change. Binary-cded decimal (BCD) recrding uses even parity. n this mde, the tape cntrl unit transfrms characters frm the channel t cnfrm with standard BM, BCD interchange cde (see Appendix A-1). Only the capacity f available cre strage in the cmputer limits blck length. A recrd gap (sectin f blank tape) abut 3/4-inch lng separates blcks n tape. n writing, the tape autmatically prduces gap at the end f a recrd. Reading begins with the first character sensed after the gap and cntinues until the next gap is encuntered. An inter-recrd gap, fllwed by a special, single-character recrd, marks the end f a file f infrmatin. The character is a Tape Mark ( ). Writing a ne-wrd recrd in BCD with ne-character-per-wrd frmat can recrd such a mark. A prgram may write ne r mre files n a reel f tape. On reading an End-f -File recrd, the tape cntrl unit stps the tape and sets its End-f-File indicatr which may be tested by the prgram. The tape cntrl unit cnsiders any recrd cntaining nly Tape Mark ( ) characters an End-f-File. The tape reads such characters int m-emry like any ther characters. As the tape unit writes infrmatin, it makes an dd-even cunt f the number f 1-bits in each track. At the end f each recrd, it writes a bit fr each track such that the ttal number f 1-bits in each track is even. This parity check sum is always even whether the character parity is even r dd. The character cntaining these check bits is the lngitudinal parity character; the tape unit writes it slightly past the end f recrded infrmatin in the blck. A Read Binary r Read BCD EOM starts a tape which cntinues until the tape unit detects an End-f-Recrd gap. f the cmputer des nt instruct the tape unit t cntinue, it stps in the middle f that gap. When the tape stps, the tape unit discnnects frm the channel. f the tape encunters an End-f-File, the tape cntrl unit sets its EOF indicatr. The central prcessr can test this indicatr which remains set until the tape unit cntrl receives a new EOM. The tape always stps after the Tape Mark. At the end f the file, the prgram reads the EOF character ( ) int memry alng with its check character. n a tw character per wrd read, this appears in the first wrd f the input area as a 1717 wrd. When the tape unit is writing n tape, it may transmit flux disturbing surges ahead f the current writing psitin; these surges affect previusly written recrds further dwn the tape. This means that a recrd in the middle f a fi e cannt be updated r rewritten if the recrds that fllw it are t be read. Any errr detected either by the channel in the character parity check r by the cntrl unit with the lngitudina parity check sets the channel errr -indicatr. When detecting such an errr in reading, the rutine shuld backspace the tape ver the errneus recrd and attempt t lire-read the recrd. The tape backspaces ver recrds using the Scan feature. A Scan reverse EOM starts the tape in reverse. A TERMNATE NPUT (TP) EOM shuld immediately fllw. The prgram then waits fr the channel t becme inactive (r awaits the End-f-Transmissin interrupt if armed and the interrupt system is enabled). When the channel becmes inactive (r the Endf-Transmissin interrupt ccurs), the tape stps in frnt f the backwardly traversed recrd. A Scan peratin is similar t a Read peratin except that the channel shifts the characters read thrugh its Wrd Assembly Register, but des nt cnsider a wrd cmplete unti a tape 3-21

44 gap is encuntered. When the tape reaches the gap, the channel uses the last tw characters in the wrd assembly as the nly wrd read frm the recrd. When scanning in reverse, the wrd cnsists f the last tw characters scanned that are the first tw lgical characters f the recrd. This peratin assembles these characters in reverse. Fr example, if the first tw characters f the recrd are 12 and the tape scans the recrd in reverse, these appear as 21 in the wrd stred fr that recrd. The same peratins ccurs in the frward scan with the last tw characters f the recrd frming the wrd stred. The Scan is useful fr reverse searching n the first wrd f the recrds in the fi e being searched. n this case, the rutine starts the tape in a reverse scan and hangs Upll n a WN. When the tape reaches the beginning f the recrd, the first wrd f the recrd transfers t the buffer. The WN stres the first wrd and the prgram checks the key wrd against the search key. f they agree, then the prgram need nly wait fr the channel t becme inactive and the rutine reads the recrd frward. f the recrd is nt the desired ne, the prgram gives anther Scan reverse withut waiting fr the channel t becme inactive. f the tape encunters the End-f-Reel marker while reading, the tape lgic sets the End-f-Reel indicatr in the tape unit; the prgram can test this at any time. An End-f-File nrmally indicates the end f recrded infrmatin n tape. Pssibly, hwever, the End-f-Reel indicatr may mark the last recrd n the reel. Writing A Write rutine writes tape after testing the tape unit fr Ready and testing fr the fi e prtect ring n the tape reel (i.e., the flag was set by the test). The Write tape EOM starts tape mtin; the tape remains in mtin unti it receives the terminatin signal frm the channel. The tape cntrl unit then writes the remaining characters f the recrd (thse in the channel buffer) and writes the lngitudinal check character. When the read-after-write head reads this check character, the tape signals the channel that it has reached Gap. f the tape receives n further Write instructin within ne millisecnd, the tape stps and discnnects. f the user wishes t backspace r rewind and then t return at sme later time t recrd additinal infrmatin at the end f the previus series f recrds, the rutine shuld write an Endf-File character r erase a segment f t~pe after the series f written recrds. This practice prvides psitive identificatin f the end f a file and facilitates return t a specific lcatin n the tape. f the prgrammer des nt use this methd, the tape may nt subsequently stp in the same lcatin at the end f the series f recrds as it did when writing the last recrd. This wuld leave a segment f tape in the gap which has nt been written and may cause errneus peratin when reading the,tape. n additin t writing under prgram cntrl, the prgram can als erase tape. When an Erase EOM with an erase unit address is used, the tape perates as thugh it were in a Write mde, except that it recrds n infrmatin. The prgram cunts the number f wrds t be erased. The use f this type f erase is fr the crrectin f a Write errr. When a Write errr ccurs, an ERASE REVERSE TAPE starts the tape in reverse. Then the same cunt used t write the recrd riginally cntrls the erase. This prcedure ensures that the tape always returns t the beginning f the errneus recrd, even if a bad spt n the tape might appear as a gap. The rutine may nw rewrite the recrd. f the Write still prduces an errr, the rutine erases the recrd backward and then erases it frward, using the same cunt and bypassing the sectin f tape where the difficulty ccurred. The rutine may nw rewrite the recrd n a new sectin f tape. The erase prcedure is used t prduce the required 3.75 inches f blank tape between the lad pint and the first recrd. A rutine des this by erasing 300 wrds at 200 bpi density, 834 wrds at 556 bpi density, r 1200 wrds at 800 bpi density. EOM instructins t the tape units specify start-withut-eader since the tape un it generates gap at the end f a" recrds fr leader. A leader instructin shuld never be included in a magnetic tape prgram because an attempt t generate leader may cause an errneus peratin. Prgramming The SES and EOM instructins fr nrmal tape peratins are isted belw. The EOM instructins use tw characters per wrd frmat. TRT n TAPE READY TEST 1051n TRT test tape unit number n fr Nt Ready. f the tape is Nt Ready, the cmputer sets the Flag Bit. f the tape is Ready, the cmputer resets the Flag Bit. A tape is Nt Ready: if there is n physical unit set t the lgical unit number be i ng tested, if the selected unit is nt in the Autmatic mde, r if the tape is in mtin fr any peratin. FPT n FLE PROTECT TEST 1411n FPT tests tape unit number n fr file prtect ring. f the file ring is inserted, the cmputer sets the Flag Bit. f nt inserted, the cmputer resets the Flag Bit. The reset will ccur if lgical unit n is absent frm the channel line. 3-22

45 BTT n BEGNNNG OF TAPE TEST 1211n BTT tests tape unit number n fr the beginning f the tape. f it is nt psitined n the lad-pint marker, the cmputer sets the Flag Bit. f psitined at the lad-pint marker, the cmputer resets the Flag Bit. The reset will ccur if lgical unit n is absent frm the channel line. ETT n END OF TAPE TEST 11lln ETT tests whether tape unit number n is nt psitined at the end f the tape. f the tape unit has nt sensed the End-f Reel marker, the cmputer sets the Flag Bit. f the End-f Reel marker has been sensed, the cmputer resets the Flag Bit. The End-f-Reel cnditin is reset when the tape is mved backward ver the End-f-Reel marker. The reset will ccur if lgical unit n is absent frm the channel line. DT2 n DENSTY TEST, 200 BP 1631n DT2 tests tape unit number n fr being set at 200 bpi density. f nt, the cmputer sets the Flag Bit. f s, the cmputer resets the Flag Bit. DT5 n DENSTY TEST, 556 BP 1671n DT5 tests tape unit number n fr being set at 556 bpi density. f nt, the cmputer sets the Flag Bit. f s, the cmputer resets the Flag Bit. DT8 n DENSTY TEST, 800 BP 1731n DT8 tests tape unit number n fr being set at 800 bpi density. f nt, the cmputer sets the Flag Bit. f s, the cmputer resets the Flag Bit. TFT TAPE END-OF-FLE TEST TFT test the tape cntrl unit fr a tape under its cntrl encuntering an End-f-Fi e during the last Read r Scan peratin. f the End-f-File indicatr is reset, the cmputer sets the Flag Bit. f the End-f-File indicatr is set, the cmputer resets the Flag Bit. The End-f-File indicatr remains set until anther tape peratin is requested. WTB n,2 WRTE TAPE N BNARY 0335n WTB starts tape unit n in a Binary Write mde. WTD n,2 WRTE TAPE N DECMAL (BCD) 0235n WTD starts tape unit Wn in a BCD Write mde. EFT n,2 ERASE FORWARD TAPE 0337n EFT starts tape unit n in an Erase mde. ERT n,2 ERASE REVERSE TAPE 0737n ERT starts tape unit n in reverse in an Erase mde. RTB n,2 READ TAPE N BNARY 0331n RTB starts tape unit n in a Binary Read mde. RTD n,2 READ TAPE N DECMAL (BCD) 0231n RTD starts tape unit n in a BCD Read mde. SFB n,2 SCAN FORWARD N BNARY 0333n SFB starts tape unifn frward in a Binary Scan mde. SFD n,2 SCAN FORWARD N DECMAL (BCD) 0233n SFD starts tape unit n frward in a BCD Scan mde. SRB n,2 SCAN REVERSE N BNARY 0733n SRB starts tape unit n in reverse in a Binary Scan mde. SRD n,2 SCAN REVERSE N DECMAL (BCD) 0633n SRD starts tape unit n in reverse in a BCD Scan mde. REW n REWND 1411n REW starts tape unit n in a Rewind. RTS a CO NVERT READ TO SCAN RTS cnverts an in-prcess Read peratin t a Scan. f the interrupts are disabled when the gap is encuntered and the prgram is hanging n a WN (executed after RTS, but befre the gap), the WN brings int memry the last tw characters frm the channel buffer. f the interrupts are enabled, an End-f Wrd (11) interrupt ccurs when the gap is encuntered by the tape unit; the last character is avai lable via a WN. f anther Read r Scan EOM is executed within 1 millisecnd f the gap ccurrence, the tape des nt stp and n End-f-Recrd (2) interrupt ccurs; if nt, an 12 interrupt ccurs when the tape is actively stpping (1 millisecnd). Nte: All scans must be in the 2 characters/wrd mde. This necessarily implies that the read peratin preceding an "RTS" must have been in the 2 characters/wrd mde. MAGNETC TAPE EXAMPLE PROGRAMS The fllwing examples shw samples f cmplete input/utput prgrams fr magnetic tape. 3-23

46 EXAMPLE: Magnetic Tape Read This prgram reads ne recrd frm Magnetic Tape N. 1 n the /O Channel. The prgram is a clsed subrutine. The tape is nt at the beginning r the end f the tape. Lcatin nstructin Cmments FRST RES 2 This instructin reserves lcatins fr the subrutine entry. TEST TRT This instructin tests Ready Magnetic Tape N. 1. the cmmand is The ctal cnfiguratin fr BFT TEST This instructin branches back t TRT if the F lag is set. An exit t a rutine that determines reasn fr the nn-ready cnditin can be placed here. RTD 1,2 This instructin activates the channel, cnnects it t Magnetic Tape N.1, and starts tape mtin. The tw characters per wrd and BCD mdes are specified. LDA =99 This cunt is fr the RN instructin t read 100 wrds. RN Read 100 wrds starting at lcatin TP Terminate input. BRU *FRST This instructin branches back t the main prgram via FRST. EXAMPLE: Write Magnetic Tape This prgram writes ne recrd n magnetic tape. The prgram is a clsed subrutine; it uses Magnetic Tape N. 1. FRST RES 2 This instructin reserves lcatins fr the subrutine entry. TEST TRT This instructin tests whether Magnetic Tape N. 1 is ready. BFT TEST Thi s tests the Flag True. Thi s instructin branches back t the Ready test if the Flag is set. FPT This instructin tests whether the fi e prtect ring is present n the tape reel. f s, the cmputer sets the Flag B it. The cta cnfiguratin f the address is BFF BRML f the Flag is reset, branch t BRML. WTD 1,2 This instructin cnnects the channel t Magnetic Tape N.1, specifies BCD transfer mde, and starts the tape mving. Tw characters per wrd mde is specified. The ctal cnfiguratin f the instructin is LDA =99 The 100 is the blck length. ROT Starting at lcatin 02000, ROT writes 100 wrds. TOP This terminates utput. CTEST CAT Wait fr channel t discnnect. BFF CTEST BRU *FRST This instructin branches back t the main prgram via FRST. BRML BRM OPER This instructin branches and marks t an assumed rutine t call the peratr and instructs him t insert file-prtect ring n Magnetic Tape N

47 LNE PRNTER SDS buffered line printers are capable f printing up t 1000 lines per minute at 132 characters per line, with a standard set f 56 characters. Printing is accmpl ished by means f a rtating character drum and a bank f 132 print hammers. The drum passes 56 different characters, in ines f 132 each, past the hammer bank. Upn cmmand frm the cmputer, the selected print hammers drive the paper against the ribbn and nt the apprpriate character typeface as it passes the print psitin. The characters are transmitted sequentially fr strage in the printer buffer befre printing. A prgrammable frmat tape lp prvides fixed (r preselected) space cntrl. Upspac ing f 1 t 7 ines, as well as page cntrl, may be accmplished by prgram instructins. An ptinal, ff- ine faci ity allws the prgram r the peratr t initiate card-t-printer r magnetic tape-t-printer peratins simu taneus with cmputatin (see Off-Line Printing). Printer Cntrls The printer cntrls, Figure 3-6, fr SDS ine printers cnsist f eight switches and indicatrs. ( P~%ER ) ( READY) fl--...:~..:...;~:..:..~e=-d---1) ( FAUL T ) Figure 3-6. Printer Cntrl ndicatr Lights and Switches The POWER ON switch is an alternate actin switch. The cmputer must be turned n fr this switch t be activated. Pressing POWER ON lights the tp half f the indicatr, turns n the mtrs and hammer driver pwer supply, and starts a timer that allws the mtrs t reach prper speed. After 20 secnds the bttm half lights, indicating that the printer is perable. When the printer is initially turned n, the READY indicatr is ff. When pressed, it is turned n if: 1. paper is laded in the line pri nter, 2. the lwer half f the POWER ON switch is lighted, and 3. the hammer pwer supply is n. This indicatr autmatically ges ff when the abve cnditins are nt real ized. The printer is ready fr either n- ine rff- ine peratin when READY is turned n. Ready is reset t preclude cmputer interventin while changing paper r ribbn, r perating the TOP OF FORM r SNGLE SPACE switches. Pressing TOP OF FORM causes the printer t psitin paper accrding t frmat tape channell. This indicatr is lighted nly when the frmat tape is psitined at channell, that is, tp-f-frm n a standard tape lp. Th is switch is perative when there is paper in the printer and the READY indicatr isff. Pressing SNGLE SPACE causes the printer t upspace paper ne single space, independently f the vertical frmat tape. Th is switch is perative when there is paper in the machine and READY is ff. The FAULT indicatr lights when the printer detects a parity errr as infrmatin transfers frm the buffer t the print hammers, r when it detects a parity errr in incming data frm magnetic tape r cards during an ff- ine peratin. t remains lighted unti the next EOM addresses the printer. The cnditin f the ight crrespnds t the status f a prgramtestable fau t ind icatr in the printer. MANUAL OFF LNEt is a cmbinatin switch and indicatr fr ff- ine peratin. The cmputer r the peratr may initiate ff- ine peratin, which is indicated by the illuminatin fthe bttm half f this switch. f the peratr presses this switch t initiate ff-line peratin, the tp half is als lighted. This indicatr is nrmally reset when the end-f-file is detected frm the input unit. Pressing READY when it is lighted als resets it, that is, by switching the printer frm the "ready" t the "nt ready" state. The FORMAT/SPACE t switch is used in ff- ine peratin. The peratr may use either mde, spacing a single space after each ine f print, r using the first character stred n tape r cards as a vertical frmat character. The TAPE/CARD t switch selects the desired input device. Paper Tape Frmat Lp A paper tape frmat lp, placed in the printer, allws upspacing t prceed t prespecified vertical psitins n the print page. The frmat lp is an eight.:.channel paper tape. Putting a punch in the specified channel at the desired vertical spacing selects the channel upspace. Channel 1 is the tp-f-frm channel, channel 7 is the bttm-f-frm channel, and channel 0 is the single-upspace channel. n the ff- ine mde with SPACE cntrl, channel 0 cntrls single spacing. When printing with n frmat lp inserted in the printer, single upspacing ccurs regardless f the channel specified. Terminating Line Printer Output When the sing e-wrd mde f transmissin is used fr printing n the line printer, each character transmissin fr a line must be fllwed by a TERMNATE OUTPUT (TOP) instructin. TOP is autmatically generated with interlaced utputs. Errr Cnditins 1. Print fault - parity errr during transfer f character infrmatin frm print buffer t print hammers. 2. Buffer errr - parity r character rate errr during transfer f infrmatin thrugh buffer. t f an ff- ine cupler is nt attached t the printer, the MANUAL OFF LNE, FORMAT SPACE, and TAPE CARD indicatrs neither light nr affect printer peratin. 3-25

48 3. nput fau t - parity errr in incming data frm cards r magnetic tape (during ff- ine peratin nly). Off-Line Printing The ptinal, ff- ine facil ity allws the ine printer t prduce printed recrds frm card r magnetic tape surces withut cmputer attentin. The character transm issin prceeds directly frm the surce t the cmputerfr ther input/ utput peratins (e.g., card reading n card reader 2, card punch, paper tape read/punch, disk read/write, etc.). Once initiated, the printing peratin is cntrlled by the surce and prceeds until the surce generates an end-f-file signal (see card input and magnetic tape input fr apprpriate endf-file cnditins). The FAU LT indicatr ights when a parity errr is detected during the reading f a tape recrd; the ff- ine printer rereads the recrd in an attempt t read gd data. f th is reread recrd cntains an errr, FAULT lights, the ff-line peratin terminates, and the printer ges back n- ine if physically cnnected t the cmputer and the MANUAL indicatr is ff. When a val idity check ccurs during a card read, FAU LT ights, the peratin terminates, and the printer ges back n-line if the MANUAL indicatr is ff. The next EOM addressing the printer resets FAULT if the printer is n-line. f the MANUAL indicatr is n, the errr cnditin may be cleared by pressing READY ff and then n again. f a fault ccurs in an ff-line peratin initiated by the cmputer, the usual methd fr clearing the errr is: 1. Press MANUAL n. 2. Press READY ff. 3. Press READY n. 4. Press MANUAL ff. n a manually-initiated ff-line peratin, steps 1 and 4 are nt required. Off-line printing can be frmatted as desired thrugh the use f a single upspace r the frmat cntrl mde (see Table 3-3). Off-line printing terminates by an end-f-file indicatr frm either device. Upn terminatin f an ff-line peratin, a physically cnnected ff-line printer system returns n-line, prvided the MANUAL indicatr is ff. Table 3-3. Frmat Cntrl Characters Cde Character Functin 00 0 Skip t frmat channel Skip t frmat channell 02 2 Skip t frmat channel Skip t frmat channel Skip t frmat channel Skip t frmat channel Sk ip t frmat channel Skip t frmat channel (hyphen) D nt space 41 J Upspace 1 line 42 K Upspace 2 lines 43 L Upspace 3 lines 44 M Upspace 4 lines 45 N Upspace 5 lines 46 0 Upspace 6 lines 47 P Upspace 7 lines Printing Off-Line Under Operatr Cntrl The prcedure fr peratr cntrl f ff- ine printing is: 1. Switch n the desired input device. (Magnetic tape is selected by dial ing it t lgical tape number 7.) 2. Place paper at tp f frm, as desired, by means f the TOP OF FORM switch. 3. Select desired input device by means f the TAPE/CARD switch. 4. Select either the FORMAT r SPACE mde as required. 5. Press MANUAL OFF LNE switch. 6. Press READY switch n, which initiates actual data transfer. Printing Off-Line Under Cmputer Cntrl The prcedure fr cmputer cntrl f ff- ine printing is: 1. Turn the equipment n. 2. Prepare the desired input device fr peratin. 3. Select desired input device by means f the TAPE/CARD switch. 4. Select either the FORMAT r SPACE mde as required. 5. Press the READY switch n. 6. Under prgram cntrl, test the tape r card unit and the ine printer fr ready" cnd itin. 7. Then, t start transfer f data, give the POL instructin t print ff-line. Prgramming SES and EOM instructins that have spec ial use with the printer fllw. Fr cnvenience, assume that the instructins address the channel and cnnect, test, r use Line Printer Number 1 n the channel. PRT 1 PRNTER READY TEST This instructin tests the printer fr a Ready cnditin. f the printer can accept a ine t be printed, r accept a skip r space instructin, it is Ready. f the printer is Ready, the cmputer sets the Flag Bit. f the printer is Nt Ready, the cmputer resets the Flag Bit. When the printer is upspac ing paper, PRT tests fr Ready befre the dpw ic; ' rnmnlp.tp.. Thp.rp.fnrp ,. PRT ---' is ineffective _ fr - searatina - tw successive upspace peratins. The secnd upspace specified may verride the first ne un less suffic ient de lay is inserted (see PSP). EPT 1 END OF PAGE TEST This instructin tests the printer fr having paper psitined at the End-f-Page, which is marked by a punch in channel 7. f nt at End-f-Page, the cmputer sets the Flag Bit. f at Endf-Page, the cmputer resets the Flag Bit. PFT 1 PRNTER FAU LT TEST This instructin tests whether the PRNT FAULT indicatr isset. f nt set, the cmputer sets the Flag Bit. f set, the cmputer resets the Flag Bit. 3-26

49 POL 1 PRNTER OFF-LNE Apprximate cmpletin times fr PSP (frm initiatin f instructin t paper stp) are: This instructin places the printer ff-line t begin an ff-line Upspace 1 line: 25 millisecnds print peratin. The card reader and/r magnetic tape attached Upspace mre than 1 line: Add 10 millisecnds fr each t the channel als ges ff-line (see Off-line Printing). additinal line. PSC 1, n PRNTER SKP TO FORMAT CHANNEL n 1n560 Off-line Print Terminatin The printer sk ips t frmat cntr channe n, where n dentes a channel number frm 0 t 7. The frmat cntrl is an eightchannel paper tape lp that is as lng as the paper being used. (See PSP fr timing.) Off-line printing terminates when an end-f-file indicatr frm the magnetic tape unit r card reader ccurs. When printing frm magnetic tape, the print peratin terminates when the first character read frm a recrd is the end-f-fi e cde, ctal 17. PSP 1, n PRNTER UPSPACE n LNES 1n760 The printer upspaces frm 0 t 7 ines as specified by n. Cnsecutive upspace instructins must be separated by a sufficient time delay. Otherwise, the tw PSP instructins may be merged by the printer. When printing frm cards, the print peratin terminates when the end-f-file signal cmes frm the reader. This ccurs when the card hpper becmes empty and the EOF ON switch n the reader is n (END OF FLE indicatr lights). f the hpper becmes empty when EOF ON is nt ighted, the printer waits fr mre cards t be placed in the hpper and the reader t becme ready. When the reader isagain ready, printing resumes. EXAMPLE: Print Tw Lines This prgram prints tw ines at the tp f a page with a single upspace between. Assume that the printer is Ready r is becming Ready after a print peratin. The prgram is a clsed subrutine fr printer number 1. Lcatin nstruct in Address Cmments FRST RES LDA 2 = 65 Saves lcatins fr subrutine entry. Lad A with 65 fr the length f a line image. TSTl PRT This instructin tests fr printer Ready. f nt Ready, the cmputer resets the Flag Bit. f Ready, the cmputer sets the Flag. BFF TSTl Nt Ready, retu rn t the test. PSC 1, This instructs the printer t mve paper t the tp f the page. The ctal cnfiguratin is PLP 1, 2 Cnnect line printer t the channel, specify 2 character/wrd mde. ROT LNE1 Output 66 wrds frm line 1 image area. TOP Terminate utput. TST2 CAT Wait fr channe t discnnect BFF TST2 LDA = 65 Relad A with 65. TST3 PRT Wait fr printer t becme ready after printing first line. BFF TST3 PSP 1, Upspace printer 1 line. The ctal cnfiguratin is PLP 1, 2 Address printer. ROT LNE2 Output image fr line 2. TOP Terminate. BRU *FRST Exit the subrutine via the BRU. 3-27

50 SDS CHARACTER CODES Characters Typewriter Printer SDS nternal Cde Card Cde Magnetic Tape Characters BCD Cde n Tape Typewriter Printer SDS nternal Cde Card Cde Magnetic Tape BCD Cde n Tape Space # r Blank K L M N P Q K L M N P Q 11 R R 120 Car. Ret.!0!0 13 $ >.J >.J & r + A B C D +.A. B C D E' F 26 G H G H Backspace? l r) < 36 Stp : t) / s T U V W X Y Z Blank / S T U V W X Y z Tab *0 * % r ( \ 76 <' Delete 77@ Blank Cl CD 8) The characters?! and * are fr input nly. The functins Backspace, Carriage Return, r Tab always ccur n utput. On the ff-line paper tape preparatin unit, 37 serves as a stp cde and 77 as a cde delete. The internal cde 12 is written n tape as a 12 in BCD. When read, this cde is always cnverted t 00. The cdes 12-0 and 11-0 are generated by the card punch; hwever, the card reader wi als accept fr 32 and fr 52 t maintain cmpatibility with earlier s.ystems. Fr the 64-character printers nly. A-l

51 TABLE OF POWERS OF TWO 21\ ~ n O O O O. a a a O O a a a O O O O O O O O O O. 000 ado O O O. a a a a a a a a a a a a a a 7 1 a a 1 a O A-2

52 OCTAL - DECMAL NTEGER CONVERSON TABLE 0000 t 0777 Octal) 0000 t 0511 (Decima/) Octal Decimal ,; ~ ~ Ol lc)oo 0512 t t (Octal) toeciml) J ~ OS Q ~ OS A-3

53 Octal-Decimal nteger Cnversin Table i , , t 2777 (Octal) 1024 t 1535 (Decimal) Octal Decimal '> ~ ' t 3777 (Octal) 1536 t 2047 (Decimal) A-4

54 Octal-Decimal nteger Cnversin Table t (Ocll) tdecimal! Octal Decimal t t (Ocll) (Deciml) Q \ , ! ' ';' j - ---' ~ ~ ~ < ~ ~ , , ! ' ' U "/ ~ A-5

55 Octal-Decimal nteger Cnversin Table i B , ~ t t (Octal) (Decimal) Octal Decimal a q ' ' : ~ ) il S \ t (Octal) (Decimal) A-6

56 OCTAL DECMAL FRACTON CONVERSON TABLE 'OCTAL DEC. OCTAL Dl::C. OCTAL DEC. OCTAL m:c G t ll ~ ' " \ ~ ' A-7

57 Octal-Decimal Fractin Cnversin Table OCTAL DEC. OCTAL DEC. OCTAL DEC. OCTAL DEC , , , QOO , , , ,000123,000316, , , , , ,000389, , OG , , A-a

58 Octal-Decimal Fradin Cnversin Table OCTAL DEC. OCTAL DEC. OCTAL DEC. OCTAL DEC ' t ll ' QO{) ' Dl A-9

59 TWO'S COMPLEMENT ARTHMETC SDS cmputer systems hld numbers in memry in tw's cmplement frm. Single-precisin numbers have 23 magnitude bits and a sign bit. The sign bit is in the first bit psitin t the left f the mst significant f the magnitude bits. Thus, the sign bit actually is a part f the number in all arithmetic peratins. A "0" bit dentes a psitive sign and a bit dentes a negative sign. n this system, the negative f a number is its tw's cmplement. An algrithm fr finding the tw's cmplement f a binary number with attached sign bit is: T find the tw's cmplement f the binary number B that has.!l significant bits including the sign bit, subtract it frm the number 2 n expressed in binary frm. This latter number is a "1 11 fllwed by nzers. EXAMPLES: The fllwing example indicates the tw's cmplement f binary numbers held in five bits plus a sign bit. Their decimal equivalents are n the left. Decimal Binary Negative f Tw's Cmplement Number Equivalent Decimal Number f Binary Equivalent, n the additin example belw, decimal ntatin is n the left and binary ntatin n the right lll!Ql n the cmputer, 24-bit numbers are written as eight ctal digits fr cnvenience. The fllwing example shws three frms f the same additin -- decimal, binary, and ctal, respectivel y. The binary number is assumed t be an integer. Decimal Binary Octal As the examples indicate, the sign bit is an integral part f the number t which it is attached and its value, plus r minus, is autmatically taken care f during the use f tw's cmplement arithmetic. This prperty is used when numbers f different length are added. Fr example, assume that these tw signed, tw's cmplemented, negative numbers f 6-bit at.1d 3-bit length are added: Decimal = Ntice that the third least significant bit f the first number is added t the sign bit f the secnd number causing an errneus result. This errr is crrected by filling in the empty, mst significant bit psitins with the value f the sign bit f the shrter number: Decimal Th is prperty suggests: Binary = ) Fill ing the empty bit psitins with the sign value f a psitive number, that is, zers, has n changing effect n the result,and 2) f the tw's cmplement is taken by the methd suggested, where n is the larger number's length, the sign value is ~tmatically appended t the smaller number. Fr instance, in the abve example, if the cmplement f 03 is taken using n = 6, the sign is prperly appended t the number. This prcedure is called lextending li the sign f a number. A-lO

60 OPTONAL EQUPMENT REAL-TME CLOCK The Real-Time Clck (RTC) prvides a highly flexible timerientatin system fr the SDS 92 Cmputer. t derives time pulses frm the 60-cycle cmputer pwer supply. These pulses are then used t prduce a timing mark every mi isecnds r ptinally every 8.33 millisecnds. The Real-Time Clck can als accept timing marks frm a custmer-supplied input, thereby allwing time measurement t any required reslutin fr special applicatins. These timing marks are supplied at standard SDS lgic levels t the cmputer's RTC circuitry. The timing marks are then used by the cmputer and its interrupt system t prvide either an elapsed-time cunter r a cntinuusly incrementing time cunter depending n the needs f the custmer. The RTC wi perate in either mde depending nly n the cmputer's stred prgram. Tw pairs f lcatins f pririty interrupts are prvided with the RTC. These are as fllws: Lcatin Nrmal Single nstructin Cmputer Descriptin CLOCK SYNC CLOCK PULSE The Clck Pulse and Clck Sync interrupts functin tgether t prvide elapsed-time, event-cunter r time-f-day clcks. The Clck Pulse interrupt is a single-instructin interrupt. (Nte: See Single nstructin nterrupts in Sectin.) An MPO instructin is usually placed in the Clck Pulse interrupt lcatin. When MPO is used as a single-instructin interrupt subrutine, it causes the cntents f the effective address t be incremented by ne but it des nt alter the current cntent f the flag. Furthermre, if the new (incremented) cntents f the effective address is 0000, a Clck Sync interrupt is generated. The Clck Sync interrupt can be generated in n ther way. ELAPSED-TME CLOCK The elapsed-time c lck times the length f a prgram r subrutine, r initiates r discntinues prcessing at prgramdetermined time intervals. An arbitrary memry lcatin is reserved as a cunter. When initialized, this cell cntains the 2's cmplement f the number f time intervals t be cunted. The Clck Pulse interrupt lcatin cntains an MPO instructin. Each Clck Pulse interrupt results in incrementing the clck cunt by ne. When the cunt is finished, an interrupt t the Clck Sync lcatin ccurs. A supervisry r ther apprpriate cntrl prgram can then be entered t perfrm the custmerdesired peratin. CONTNUOUS LY NCREMENTNG CLOCK The cntinuusly incrementing clck maintains "time-f-day" fr the cmputer. Tw memry lcatins serve t cunt the timing marks. n this case, the Clck Pulse is used t increment the least significant twelve bits f the cunt. (The Clck Pulse interrupt lcatin cntains an MPO instructin.) The Clck Sync is used t increment the mst significant twelve bits f the cunt. (The Clck Sync interrupt subrutine includes an MPO instructin.) A simple, straightfrward subrutine can be entered t recnstruct the exact time-f-day frm this twenty-fur bit cunt. ARM/DSARM The Clck Pulse interrupt can be armed and disarmed with these instructins: EOM Effective Address Actin The Clck Sync interrupt is always armed. AUTOMATC POWER FAL-SAFE SYSTEM Disarm Clck Pulse nterrupt Arm Clck Pu se nterrupt The cmputer cre memry hlds its infrmatin with all pwer remved, but infrmatin in the cmputer registers is destryed by lss f pwer. Upn fai lure f main pwer t the cmputer, this system prvides that the cntents f all registers and ther vlati e infrmatin are autmatically stred in cre memry; als, further writing int cre strage is inhibited durrng the decay perid f the cmputerdc pwer supplyutputs. Errneus memry cntrl is prevented during pwer-ff and pwer-n peratins. Pwer-ff/-n interrupt rutines permit prper resumptin f a prgram, autmatically, after pwer is restred. The system cnsists f relay-cntrlled, ac pwer-sensing and memry-sequencing circuitry, tw high-pririty interrupt channels, and a "shut-dwn/start-up" prgramming sequence. The Sense External Signal (SES) instructin is an aid in prgramming this ptin. ts effective address is f the OFF interrupt (152) has just ccurred, this SES sets the Flag. DATA MULTPLEXNG SYSTEM NTRODUCTON The standard /O systems prvided with the SDS 92 Cmputer prvide fr peratin with all standard SDS peripheral equipments and fr high-perfrmance special devices. The Data Multiplexing System prvides an alternate /O system that is f particular use in dealing with multiple surces f data and fr systems which may have data rates frm lw t very high. The SDS 92 Cmputer has essentially tw majr paths alng wh ich /O data can flw t and frm memry. The fi rst path is the same that is used by the main frame itself. The B-1

61 PN BP POT BPO Pririty nterrupts Central Prcessr Basic /O Channel First Path Memry..-- Fixed Lcatin nterlace Cntr 1--"-'-- Wrds fr the Attached DSCs Memry Parity. Checking Optin ~e::; P:; Data Multiplexing System 1 L ElN Pririty nterrupt Data Multiplex Channel Address Register nput 1. Data 2. Addresses 3. 4-Bit Functin Cdes DSC- Data Register Data Register 6-Bit Characters (lr 2 per 12-Bit Wrd) 12-Bit Characters Output 1. Data 2. Cntrl 12- r 24-Bit Characters DSC Pririty DSC 11* -P-ri-~i-tY-~t-e-rr-u~~ - - ~ ~ ~ Char. Register UnitAddress ""'--"-"~ ElN 1 t /O DEVCE Data/cntm~ - * N strage reg i sters. ---,' ~~S ~ Pririty nterrupt SDS 92 Cmputer Cnfiguratin B-2

62 PN/POT peratins use the first path. The basic /O channel als uses this path. n additin t this path, which is primari y under the cntrl f the main frame, there is an ptinal secnd path that is cmpletely under the cntrl f the units attached t it. The secnd path has pririty ver the first fr access t memry. This path is made available with the installatin f a Data Multiplexing System. The Data Multiplexing System (DMS) cnsists f a Data Multiplex Channel (DMC) and ne r mre Data Subchannels (DSC). A maximum f 64 subchannels are allwed. Transmissin between a DSC and cmputer memry is cntrlled by tw interlace cntrl wrd-pairs unique t the DSC and wired int fixed, adjacent lcatins in memry. During a transmissin, the cntrlling DMC uses these tw wrd-pairs fr cntrl f address and recrd length. Fur DSCs (ne DSC- and three DSC-s) culd be placed in a system as fllws. The DSCs are numbered frm 100, 104,... t 1148' Cntrl wrd quads assc i ated wi th the DSCs are numbered accrd i ng y: fr DSC-100, etc. DATA MULTPLEX CHANNEL (DMC) The Data Multiplex Channel is a basic unit fr the Data Multipexing System. t cnnects t the SDS 92 Cmputer via the secnd path t memry. The DMC cntains a 13-bit Data Register, 15-bit Address Register, and cntrl lgic t enable the DMS t perfrm a variety f functins. The data and address are cnnected t memry when a transfer f infrmatin is imminent. Prgram cntrl required fr input/utput perates directly n the individual Data Subchannel (DSC), nt n the DMC. When external data addresses are prvided t the DMC, the DMC transmissins require ne cycle fr each 12-bit wrd transmitted and tw cycles fr each 24-bit duble wrd transmitted. The DMC has an internal interlace feature. This feature allws subchannels t specify the addresses f wrd pairs in memry where the data address and cunt are lcated. When perating with internal interlace, the subchannel supplies the address f its assciated interlace cntrl wrds instead f the actual data address. The DMC accesses the interlace wrd pair, increments the address prtin, decrements the wrd cunt, restres mdified wrds, and then accepts data frm, r transmits data t, the requesting subchannel. The DMC als supplies a signal t the subchannel, if the decremented wrd cunt is zer. The frmat f the'internal interlace wrd pair is: --Wrd N+1--1 'Wrd Cunt Wrd N---- Data Address The 9-bit wrd cunt permits blck lengths t 512 wrds. Transmissins using internal interlace require five cycles, if the required transmissin is fr a 12-bit wrd, and six cyc les, if the required transmissin is fr a 24-bit duble wrd. The DMC prvides fr autmatic memry incrementing. The cunting capability f the DMC Data Register permits an externally specified memry wrd t be incremented. When such 11 a memry increment peratin is t be perfrmed, the subchannel signals the DMC with a special increment line and supplies the address. Fr memry increments, the DMC accesses memry, increments it, and then restres the wrd. f a memry increment peratin results in an all-zer wrd (r duble wrd), the DMC signals the subchannel. The zer signal may then be used t interrupt the prgram. Memry increments require tw cycles. Cntrl f the varius DMC functins is achieved by fur Functin Cde ines frm the subchannels. The DMC, in cnjunctin with the main frame Memry Parity Checking Optin, insure the integrity f data transmissins. Wrds read frm memry are checked fr parity; parity is generated fr wrds stred in memry; wrds received by the DMC are checked fr prper parity; a parity errr signal is generated by the DMC and sent t the subchannel when an input parity discrepancy is detected. DATA SUBCHANNELS (DSC-N) A number f subchannels can be attached t the DMC. The tw described belw are standard subchannels. Subchannels can cntrl and generate prgram interrupts, but d nt include the interrupt levels themselves. The signl,s must be ruted t ptinal interrupt levels. The subchannels use a pririty scheme t determine which may transmit t the DMC at any given time. Up t 64 DSCs may be cnnected t a DMC. A DSC may use the internal interlace feature f the DMC t cntrl its transmissin, r it may be equipped with an External nterlace (EN). A DSC using internal interlace has tw wrd pairs assigned t it. These tw wrd pairs are lcated in cntiguus memry lcatins and are fixed fr a given subchannel. The prgram may select either the even wrd pair r dd wrd pair lcatin. f the even wrd pair lcatin is selected, the subchannel wi autmatically switch t the dd wrd pair lcatin when the cunt field f the even wrd pair wrd is zer. The prgram can als select whether the subchannel switches back t the even wrd pair when the cunt field f the dd wrd pair is zer. The subchannel generates an interrupt signal when the cunt field f either wrd pair reaches zer. Transmissin terminatin ccurs when the dd wrd pair's cunt equals zer, if the subchannel des nt switch back t the even wrd pair. The tw wrd pai~ internal interlace allws a subchannel t hand e cntinuus data by alternately wrking frm ne memry area r anther. By allwing the subchannel t switch autmatically frm ne interlace wrd pair t the ther, the prgram is relieved f the necessity fr making real-time respnses t the zer cunt cnditin. Using first the even pair then the dd pair interlace wrds allws a maximum transmissin f 1024 wrds r duble wrds. CHARACTER SUBCHANNEL (DSC-) The DSC- cntains a 12-bit data register that can assemble and disassemble tw 6-bit characters, and transmit ne r tw06-bit characters r ne 12-bit character. (DSC- has a unit address B-3

63 register.) t checks and generates the parity f characters t enable it t cuple with standard SDS peripheral equipment. The subchannel may perate with either internal r external interlace. t has ne mde f utput and tw mdes f input. During utput, it transmitsuntil the dd internal interlace wrd 'pair cunt is zer and then terminates, if interlace cycl ing is nt requested. The utput may als be terminated ifthedevice sends an END signal t the channel. This END signal may cause the DSC- t generate an interrupt t the prgram. nput, like utput, may always be terminated due t an external END signal. TheprgramcanalsspecifythattheDSC terminates and discnnects n zer cunt, r discnnects nly n the END signal. n either case, hwever, all transmissin t memry is terminated after the dd interlace cunt reaches zer, if interlace cycling is nt requested. FULL WORD SUBCHANNEL (DSC-) The DSC- is a general-purpse subchannel, designed t allw any device t be cnnected t it. t cntains n strage fr data. Depending n the Functin Cde prvided t the DMC, the DSC- will permit 12- r 24-bit (plus parity) transmissin between the DMC and external devices cnnected t the DSC-. The external device must be capable f hlding the data during the transm issin t/frm the DMC. (An A-t-D cnverterwu d have such capability.) Like the DSC-, the DSC- can perate with either internal r external interlace. ts peratin in this respect is identical t the DSC-. The DSC- als cntains cntrl lgic t facilitate memry increment peratins in cnjunctin with the DMC. EXTERNAL NTERLACE (EN) The External nterlace can be attached t the DSC t cntrl the transmissin f its data t/frm memry. The EN cnsists f a 15-bit address register and a 9-bit cunt register. These registers are laded autmatically when the subchannel is activated, the infrmatin cming frm the internal interlace memry lcatins. Once the EN is set up, it will cntrl the transm issin f the DSC at a maximum rate f ne wrd per memry cycle. After each wrd is transmitted, the EN increments its address register and decrements its cunt. When the cunt equals zer, the EN signals the DSC, which can then generate a prgram interrupt and/r ntify the external device. Transrn:ssin nrmally terminates n zer cunt. Sequencing f interlace wrds is identical t the sequence f peratins perfrmed fr internal interlace, except that nly fur memry cyc! es are used fr interl ace wrd prcessi ng. The first istaccess the interlace wrd pair initiallyi the secnd is t restre the interlace wrd pair when the cunt reaches zer. MEMORY PARTY NTERRUPTS SDS cmputers incrprate an extensive memry parity checking system. The inclusin f parity generatin and checking circu itry assures the integrity f all data and instructins transferred amng the memry, the central prcessing unit, and input/utput channels. n nrmal peratin a switch n the cmputer cnsle specifies the actin t be perfrmed by the cmputer when a memry parity errr is detected. Tw actins are avai lable: the cmputer halts with the parity indicatr lightedi r the cmputer ignres the parity errr and prceeds with the prgram. n many real-time appl icatins it is desirable t keep the cmputer running when a parity errr isdetected. Als, the prgram must be ntified f the errr withut stpping cmputat in. An ptinal feature prvides this capability by means f tw levels f armed interrupts. One interrupt level is assciated with the central prcessr and the Time-Multiplexed Cmmunicatin Channelsi the ther interrupt level with the Direct Access Cmmunicatin Channels and the Data Multiplexing System. Memry parity errrs detected frm these tw surces prduce a pririty interrupt assciated with the cause. The prcessing rutine assciated with the interrupt can then take apprpriate actin, such as re-initiate the failed peratin, ntify the peratr, renter a diagnstic rutine. Such actin allws memry parity errrs t be recgnized and handled prperly withut hindering the cmputer's perfrmance f realtime r n- ine calculatins. B-4

64 TRAPPNG RETURN SUBROUTNE EXAMPLE The fllwing cde determines hw many cells (ne r tw) the trapped instructin used: it then increments the subrutine entry accrdingly t prvide the prper return address. has the frm: MUASM F 'CT Unpredictable 3 bits Assume (1) the trap instructin is a multiply simulatr at lcatin 124, and (2) the branch in lcatin 124 is BRM MUASM. Assume als that MUA hardware is nt present in the machine. Executing an instructin cntaining the MUA peratin cde causes the BRM MUASM t be executed. The marked place 12 bits which marks the Flag and PCT bits in 0, 1, zers in bits 6 thrugh 8, and the trap instructin address in bits 9, 10, 11 t MUASM and in bits 0 thrugh 11 in MUASM + 1. The subrutine return rutine fllws: MUASM PLUSONE DATA DATA LOB *MUASM Lad trapped instructin. LOA =1 Lad an incrementer. COB =040 BFT TRUE Branch if bit 6 is reset. COB =037 BRU ACK F = 1 if address was an immediate address (tw wrds); F = 0 if it was direct single precisin. TRUE COB =010 BFT ACK Branch if bit 8 is reset (i.e., if F is set t 1 which implies tw wrd-full address with n index). COB =020 F = 0 if indirect address, single precisin; F = 1 if tw wrd indexed ACK ACA =0 Add 1 t A if tw wrd (add 0 if ne wrd). MPA MUASM+1 Add 1 r 2 t the subrutine entry. MPF MUASM This is fr address verflw crrectin. B-5

65 SOS 92 MEMORY ALLOCATON ' s r\ Unassigned Scratch Pad Unassigned DSC nterlace Cntrl Wrd Pairs Trap 12 Trap 52 Trap 13 Trap 53 Trap 10 Trap 50 Trap 11 Trap 51 Trap 14 Trap 54 Trap 15 Trap 55 \ nterrupt, POWER ON (always arm"'ed) nterrupt, POWER OFF (always armed) nterrupt, MAN FRAME PARTY (armed via cnsle switch) nterrupt, OAT A MU LTPLEXNG SYSTEM PARTY (armed via cnsle switch) Unassigned Unassigned nterrupt, CLOCK SYNC (always armed) nterrupt, CLOCK PULSE (arm furnished,. type) nterrupt, l (arm furnished) nterrupt, 12 (arm furnished) Unassigned Unassigned System nterrupts (up t 256 levels; any may be f. type if desired). --- Single nstructin nterrupt r --- nterrupt system must be enabled befre interrupt ges active. s - nterrupt always prceeds frm Waiting t Active B-6

66 SDS 92 NSTRUCTON LST - FUNCTONAL CATEGORES nstructin Mnemnic Cde Name Functin Timing* LOAD!...STORE LDA 64 LOAD A (M) --A 2 LDB 24 LOAD B (M) --B 2 STA 44 STORE A (A) --M 2 STB 04 STORE B (B) --M. 2 XMA 74 EXCHANGE M AND A (A)---(M) 3 XMB 34 EXCHANGE M AND B (B)---(M) 3 FLAG XMF 17 EXCHANGE M AND F (M)O---F 3 LDF 57 LOAD F (M)O --F 3 SFT 0044 SET FLAG TRUE 1--F 3,4 SFF 0042 SET FLAG FALSE --F 3,4 NF 0046 NVERT FLAG f (F)=l, 0 --F; if (F)=O, 1--F 3,4 ARTHMETC ADA 62 ADD TO A (A)+ (M) -- A; Carry - F 2 ADB 22 ADD TO B (B)+ (M) ---- B; Carry --- F 2 ACA 63 ADD WTH CARRY TO A (A)+ (M)+ F -- A; Carry -- F 2 ACB 23 ADD WTH CARRY TO B (B)+ (M)+ F - B; Carry --- F 2 SUA 60 SUBTRACT TO A (A) - (M) ---A; Carry --- F 2 SUB 20 SUBTRACT TO B (B) - (M) - B; Carry --F 2 SCA 61 SUBTRACT WTH CARRY TO A (A) - (M) - F ---A; Carry --- F 2 SCB 21 SUBTRACT WTH CARRY TO B (B) - (M) - F --- B; Carry ---F 2 MPA 76 MEMORY PLUS A TO MEMORY (M)+ (A) ---M; Carry --F 3 MPB 36 MEMORY PLUS B TO MEMORY (M)+ (B) --M; Carry -- F 3 MPO 16 MEMORY PLUS ONE TO MEMORY (M)+l ---M; Carry~F 3 MPF 56 MEMORY PLUS FLAG TO MEMORY (M)+ (F) --- M; Carry --- F 3 MUA 13 MU LTPL Y A (Optinal) (A)x (M) --AB 5 MUB 53 MULTPLY B (Optinal) (B)x(M) ---AB 5 DVA 52 DVDE AB (Optinal) (AB)+(M) -B; R--A 13 DVB 12 DVDE BA (Optinal) (BA)+(M) --- B; R --A 13 LOGCAL ANA 65 AND TO A (A) and (M) --A 2 ANB 25 AND TO B (B) and (M) --B 2 ORA 67 OR TOA (A) r (M) --A 2 ORB 27 OR TO B (B) r (M) --B 2 EOA 66 EXCLUSVE OR TO A (M)(A) r (M)(A) ---A 2 *See page 2-1 fr interpretatin and use f the Timing clumn. B-7

67 SDS 92 NSTRUCTON LST - FUNCTONAL CATEGOR,ES (cntinued) nstructin Mnemnic Cde Name Functin Timing LOGCAL (cntinued) EOB 26 EXCLUSVE OR TO B (M)(B) r (M)(B) --B 2 MAA 75 MEMORY AND A TO MEMORY (M) and (A) --M 3 MAB 35 MEMORY AND B TO MEMORY (M) and (B) --M 3 COMPARSON COA 45 COMPARE ONES WTH A f (A)(M) = 0, set Fi if (A)(M) 10, reset F 2 COB, 05 COMPARE ONES WTH B f (B)(M)=O, set Fi if (B)(M)O, reset F 2 CMA 47 COMPARE MAGNTUDE OF M WTH A f.(a) ~(M), set Fi if (A) < (M), reset F 2 CMB 07 COMPARE MAGNTUDE OF M WTH B f (B) ~(M), set Fi if (B) «M), reset F 2 CEA 46 COMPARE M EQUAL TO A f (M) (A), set F; if (M) =(A), reset F 2 CEB 06 COMPARE M EQUAL TO B f (M)(B), set Fi if (M)=(B), reset F 2 BRANCH SHFT BRU 73 BRANCH UNCONDTONALLY M ---P BRC 32 BRANCH, CLEAR NTERRUPT, AND LOAD FLAG M --- Pi c lear nterrupt (see page 2-4) 3 BRL 33 BRANCH AND LOAD FLAG M --- i (see page 2-4) BFF 31 BRANCH ON F LAG FALSE f F = 0, M ---- Pi 1 if F = 1, take next instructin 2 BFT 71 BRANCH ON F LAG TRUE f F = 1, M ---- Pi 1 if F = 0, take next instructin 2 BDA 70 BRANCH ON DECREMENTNG A (A) A f (A) , M --- Pi 1 f (A) = 7777, take next instructin 8 2 BAX 30 BRANCH AND EXCHANGE A AND B (A)~ (B)i (M) --- P BRM 77 BRANCH AND MARK PLACE (P) ---M, M+1i M+2---Pi (F) -MO; (PCT)--- M1 3 BMC 37 BRANCH, MARK PLACE, AND CLEAR FLAG (See page 2-5) 3 CYA 42* CYCLE A A cycled left N places 3-7 CYB 02* CYCLE B B cycled left N places 3-7 CFA 43* CYCLE FLAG AND A F,A cycled left N places 3-7 CFB 03* CYCLE FLAG AND B F, B cycled left N places 3-7 CYD 02/42* ** CYCLE DOUBLE A, B cycled left N places 3-7 CFD 43* CYCLE FLAG AND DOUBLE A, B, F cycled left N places 3-7 CF 03* CYCLE FLAG AND DOUBLE NVERSE B, A, F cycled left N places 3-7 CONTROL EXU 72 EXECUTE nstructin M is perfrmed, P unchanged HLT 0041/ ** HALT Ha ts cmputatin 3,4 *See page 2-5 fr indicatin f the instructin structure and cde redundancy. ** A slash (/) indicates that either instructin cde can be used t perfrm the same peratin. B-8

68 SDS 92 NSTRUCTON LST - FUNCTONAL CATEGORES (cntinued) nstructin Mnemnic Cde Name Timing TRAPPNG SCT 0061 SET PROGRAM-CONTROLLED TRAP 1-PCT 3,4 RCT 0060 RESET PROGRAM-CONTROLLED TRAP O-PCT 3,4 TCT 0160 TEST PROGRAM-CONTROLLED TRAP f PCT = 0, O-F; if PCT = 1, 3,4 l~f BREAKPONT TESTS BPT BREAKPONT NO.1 TEST Test Breakpint Switch 3,4 BPT BREAKPONT NO.2 TEST Test Breakpint Switch 3,4 BPT BREAKPONT NO.3 TEST Test Breakpint Switch 3,4 BPT BREAKPONT NO.4 TEST Test Breakpint Switch 3,4 NTERRUPTS ER 0051 ENABLE NTERRUPT 3,4 DR 0050 DSABLE NTERRUPT 3,4 let 0150 NTERRUPT ENABLED TEST; SET FLAG F NTERRUPT SYSTEM ENABLED 3,4 AR ARM NTERRUPTS 3,4 CHANNEL CONTROL AND TESTS DSC DSCONNECT CHANNEL 3,4 TOP TERMNATE OUTPUT ON CHANNEL 3,4 TP TERMNATE NPUT ON CHANNEL 3,4 ALC ALERT CHANNEL NTERLACE 3,4 ASC ALERT TO STORE NTERLACE COU NT 3,4 CAT CHANNEL ACTVE TEST; SET FLAG F NOT ACTVE 3,4 CET CHANNEL ERROR TEST; SET FLAG F ERROR 3,4 NPUTLOUTPUT WN 15 WORD N (Channel)- M 5 + wait RN 55 RECORD N (Channel d )_M N wr s 3 + 2N + wait WOT 11 WORD OUT (M)- Channel 4 + wait ROT 51 RECORD OUT (M d )-Channel N wr s 2 + 2N + wait PN 14 PARALLEL NPUT (Unit M)_ M in parallel 5 + wait, and 5,6 + wait POT 10 PARALLEL OUTPUT (M)_Unit M in parallel 4 + wait, and 4,5 + wait BP 54 BLOCK PARALLEL NPUT (Unit M)_ M in parallel, 4 + N + wait, and N sequential lcatins. 3,4+2N+wait BPO 50 BLOCK PARALLEL OUTPUT (M)_ Unit M in parallel, 3 + N + wait, and N sequential lcatins 2,3 + 2N + wait EOM 00(40)* ENERGZE OUTPUT M 3.5 fjsec pulse t pints addressed 3,4 SES 01(41)* SENSE EXTERNAL SGNAL f Signal = 1, set Flag Bit; if Signal = 0, reset Flag Bit 3,4 *Cdes EOM 40 and SES 41 are reserved fr use in special system applicatins. B-9

69

70 SDS 92 NSTRUCTON LST - NUMERCAL ORDER nstructin Cde Mnemnic Name 00(40)* EOM ENERGZE OUTPUT M /0041** HLT HALT DSC DSCONNECT CHANNEL ASC ALERT TO STORE NTERLACE COUNT TP TERMNATE NPUT ON CHANNEL TOP TERMNATE OUTPUT ON CHANNEL AR ARM NTERRUPTS ALC ALERT CHANNEL NTERLACE 0042 SFF SET FLAG FALSE 0044 SFT SET FLAG TRUE 0046 NF NVERT FLAG 0050 DR DSABLE NTERRUPT 0051 ER ENABLE NTERRUPT 0060 RCT RESET PROGRAM-CONTROLLED TRAP 0061 SCT SET PROGRAM-CONTROLLED TRAP 01(41)* SES SENSE EXTERNAL SGNAL CET CHANNEL ERROR TEST; SET FLAG F ERROR CAT CHANNEL ACTVE TEST; SET FLAG F NOT ACTVE 0144 BPT 1 BREAKPONT NO. 1 TEST 0145 BPT 2 BREAKPONT NO. 2 TEST 0146 BPT 3 BREAKPONT NO.3 TEST 0147 BPT 4 BREAKPONT NO.4 TEST 0150 let NTERRUPT ENABLED TEST; SET FLAG F NTERRUPT SYSTEM ENABLED 0160 TCT TEST PROGRAM-CONTROLLED TRAP 02*** CYB CYCLE B 02/42** *** CYD CYCLE DOUBLE 03*** CFB CYCLE FLAG AND B 03*** CF CYCLE FLAG AND DOUBLE NVERSE 04 STB STORE B 05 COB COMPARE ONES WTH B 06 CEB COMPARE M EQUAL TO B 07 CMB COMPARE MAGNTUDE OF M WTH B 10 POT PARALLEL OUTPUT 11 WOT WORD OUT 12 DVB DVDE BA (Optinal) 13 MUA MULTPLY A (Optinal) Paae Reference 3-5,3-6, ,3-7, ,3-8,3-9, *Cdes EOM 40 and SES 41 are reserved fr use in spec ial system appl icatins. ** A slash (/) indicates that either instructin cde can be used t perfrm the same peratin. ***See page 2-5 fr indicatin f the instructin structure and cde redundancy. B-ll

71 SDS 92 NSTRUCTON LST - NUMERCAL ORDER (cntinued) nstructin Cde Mnemnic Name Pa~e Reference 14 PN PARALLE L NPUT 3-8, WN WORD N MPO MEMORY PLUS ONE TO MEMORY XMF EXCHANGE M ANDF SUB SUBTRACT TO B SCB SUBTRACT WTH CARRY TO B ADB ADD TO B ACB ADD WTH CARRY TO B LDB LOAD B ANB AND TO B EOB EXCLUSVE OR TO B ORB OR TO B BAX BRANCH AND EXCHANGE A AND B BFF BRANCH ON FLAG FALSE BRC BRANCH, CLEAR NTERRUPT, AND LOAD FLAG BRL BRANCH AND LOAD FLAG XMB EXCHANGE M AND B MAB MEMORY AND B TO MEMORY MPB MEMORY PLUS B TO MEMORY BMC BRANCH, MARK PLACE, AND CLEAR FLAG * CYA CYCLE A * CFA CYCLE FLAG AND A * CFD CYCLE FLAG AND DOUBLE STA STORE A COA COMPARE ONES WTH A CEA COMPARE M EQUAL TO A CMA COMPARE MAGNTUDE OF M WTH B BPO BLOCK PARALLEL OUTPUT 3-8, ROT RECORD OUT DVA DVDE AB (Optina ) MUB MULTPLY B (Optinal) BP BLOCK PARALLEL NPUT 3-8, RN RECORD N MPF MEMORY PLUS FLAG TO MEMORY LDF LOAD F SUA SUBTRACT TO A SCA SUBTRACT WTH CARRY TO A ADA ADD TO A 2-2 *See page 2-5 fr indicatin f the instructin structure and cde redundancy. B-12

72 SDS 92 NSTRUCTON LST - NUMERCAL ORDER (cntinued) nstructin Cde Mnemnic Name Page Reference 63 ACA ADD WTH CARRY TO A LDA LOAD A ANA AND TO A EOA EXCLUSVE OR TO A ORA OR TO A BDA BRANCH ON DECREMENTNG A BFT BRANCH ON FLAG TRUE EXU EXECUTE BRU BRANCH UNCONDTONALLY XMA EXCHANGE M AND A 2-1 " 75 MAA MEMORY AND A TO MEMORY MPA MEMORY PLUS A TO MEMORY BRM BRANCH AND MARK PLACE 2-5 B-13

73

74 SDS 92 NSTRUCTON LST - ALPHABETCAL ORDER Mnemnic nstructin Cde Name Paae Reference ACA 63 ADD WTH CARRY TO A 2-2 ACB 23 ADD WTH CARRY TO B 2-2 ADA 62 ADD TO A 2-2 ADB 22 ADD TO B 2-2 AR ARM NTERRUPTS 3-12 ALC ALERT CHANNEL NTERLACE 3-7 ANA 65 AND TO A 2-3 ANB 25 AND TO B 2-3 ASC ALERT TO STORE NTERLACE COUNT 3-6 BAX 30 BRANCH ON DECREMENTNG A 2-5 BDA 70 BRANCH AND DECREMENTNG A 2-5 BFF 31 BRANCH ON FLAG FALSE 2-4 BFT 71 BRANCH ON FLAG TRUE 2-5 BMC 37 BRANCH, MARK PLACE, AND CLEAR FLAG 2-5 BP 54 BLOCK PARALLEL NPUT 3-8,3-9 BPO 50 BLOCK PARALLEL OUTPUT 3-8,3-9 BPT BREAKPONT NO. 1 TEST 2-7 BPT BREAKPONT NO.2 TEST 2-7 BPT BREAKPONT NO.3 TEST 2-7 BPT BREAKPONT NO.4 TEST 2-7 BRC 32 BRANCH, CLEAR NTERRUPT, AND LOAD FLAG 2-4 BRL 33 BRANCH AND LOAD FLAG 2-4 BRM 77 BRANCH AND MARK PLACE 2-5 BRU 73 BRANCH UNCONDTONALLY 2-4 CAT CHANNEL ACTVE TEST; SET FLAG F NOT ACTVE 3-7 CEA 46 COMPARE M EQUAL TO A 2-4 CEB 06 COMPARE M EQUAL TO B 2-4 CET CHANNEL ERROR TEST; SET FLAG F ERROR 3-7 CFA 43* CYCLE FLAG AND A 2-6 CFB 03* CYC LE FLAG AND B 2-6 CFD 43* CYCLE FLAG AND DOUBLE 2-6 CF 03* CYCLE FLAG AND DOUBLE NVERSE 2-6 CMA 47 COMPARE MAGNTUDE OF M WTH A 2-4 CMB 07 COMPARE MAGNTUDE OF M WTH B 2-4 COA 45 COMPARE ONES WTH A 2-4 COB 05 COMPARE ONES WTH B 2-4 CYA 42* CYCLE A 2-6 CYB 02* CYCLE B 2-6 *See page 2-5 fr indicatin f the instructin structure and cde redundancy. B-15

75 SDS 92 NSTRUCTON LST - ALPHABETCAL ORDER (cntinued) Mnemnic nstructin Cde Name CYD 02/42* ** CYCLE DOUBLE DR 0050 DSABLE NTERRUPT DSC DSCONNECT CHANNEL DVA 52 DVDE AB (Optinal) DVB 12 DVDE BA (Optinal) ER 0051 ENABLE NTERRUPT EOA 66 EXCLUSVE OR TO A EOB 26 EXCLUSVE OR TO B EOM 00(40)*** ENERGZE OUTPUT M EXU 72 EXECUTE HLT /0041** HALT let 0150 NTERRUPT ENABLED TEST; SET FLAG F NTERRUPT SYSTEM ENABLED NF 0046 NVERT FLAG LDA 64 LOAD A LDB 24 LOAD B LDF 57 LOAD F MAA 75 MEMORY AND A TO MEMORY MAB 35 MEMORY AND B TO MEMORY MPA 76 MEMORY PLUS A TO MEMORY MPB 36 MEMORY PLUS B TO MEMORY MPF 56 MEMORY PLUS FLAG TO MEMORY MPO 16 MEMORY PLUS ONE TO MEMORY MUA 13 MULTPLY A (Optinal) MUB 53 MULTPLY B (Optinal) ORA 67 OR TOA ORB 27 OR TO B PN 14 PARALLEL NPUT POT 10 PARALLEL OUTPUT RCT 0060 RESET PROGRAM-CONTROLLED TRAP RN 55 RECORD N ROT 51 RECORD OUT SCA 61 SUBTRACT WTH CARRY TO A SCB 21 SUBTRACT WTH CARRY TO B SCT 0061 SET PROGRAM-CONTROLLED TRAP SES 01 (41)*** SENSE EXTERNAL SGNAL SFF 0042 SET FLAG FALSE SFT 0044 SET FLAG TRUE Paae Reference ,3-6, , ,3-8,3-9, ,3-7, *See page 2-5 fr indicatin f the instructin structure and cde redundancy. **A slash V) indicates that either instructin cde can be used t perfrm the same peratin. ***Cdes EOM 40 and SES 41 are reserved fr use in special system appl icatins. B-16

76 SDS 92 NSTRUCTON LST - ALPHABETCAL ORDER (cntinued) \ Mnemnic nstructin Cde Name Pase Reference STA 44 STB 04 SUA 60 SUB 20 TCT 0160 TP TOP WN 15 WOT 11 XMA 74 XMB 34 XMF 17 STORE A STORE B SUBTRACT TO A SUBTRACT TO B TEST PROGRAM-CONTROLLED TRAP TERMNATE NPUT ON CHANNEL TERMNATE OUTPUT ON CHANNEL WORD N WORD OUT EXCHANGE M AND A EXCHANGE M AND B EXCHANGE M AND F B-17

77 SOS 92 NPUT/OUTPUT NSTRUCTONS Mnemnic Octal Cde Name Mnemnic Octal Cde Name Buffer nstructins and Tests BUFFER CONTROL BUFFER TESTS EOM A, T 00 r 40 Energize Output M DSC Discnnect Channel SES A, T 01 r 41 Sense External Signal TOP Terminate Output n Channel CAT Channel Active Test TP Terminate nput n Channel CET Channel Errr Test ASC Alert t Stre nterlace Cunt ALC Alert Channel nterlace DAT A TRANSFER PARALLEL NPUT/OUTPUT WOT A, T 11 Wrd Out POT A, T 10 Parallel Output ROT A, T 51 Recrd Out BPO A, T 50 Blck Parallel Output WN A,T 15 Wrd n PN A, T 14 Parallel nput RN A, T 55 Recrd n BP A, T 54 Blck Parallel nput Peripheral Device nstructins and Tests TYPEWRTER LNE PRNTER (cnt. ) RKB 1, Read Keybard PSC 1, n 0001n560 Printer Skip t Frmat Channel n TYP 1, Write Typewri ter PSP 1, n 0001 n760 Pri nter Space n Li nes PLP 1, Print Line Printer PAPER TAPE MAGNETC TAPE RPT 1, Read Paper Tape PTL 1, Punch Paper Tape with Leader TRT n n T ape Ready Test PPT 1, Punch Paper Tape, N Leader FPT n n File Prtect Test BTT n n Beginning f Tape Test CARD ETT n n End f Tape Test DT2 n n Density Test, 200 BP CRT Card Reader Ready Test DT5 n n Density Test, 556 BP CFT Card Reader EOF Test DT8 n n Density Test, 800 BP RCD 1, Read Card Dec imal (Hllerith) TFT Tape End-f-File Test RCB 1, Read Card Binary WTB n, n Write Tape in Binary CPT Card Punch Ready Test WTD n, n Write Tape in Decimal (BCD) PCD 1, Punch Card Decimal (Hllerith) EFT n, n E rase Frward Tape PCB 1, Punch Card Binary ERT n, n Erase Reverse Tape RTB n, n Read Tape in Binary RTD n, n Read Tape in Decimal (BCD) LNE PRNTER SFB n, n Scan Frward in Binary SFD n, n Scan Frward in Decimal (BCD) PRT Pri nter Read y T es t SRB n, n Scan Reverse in Binary EPT End f Page Test SRD n, n Scan Reverse in Decimal (BCD) PFT Printer Fault Test REW n n Rewind POL Printer Off-line RTS Cnvert Read t Scan Legend A = address; *A = indirect address; =A = immediate address; T = index tag; n = number (0-7) Mnemnics and Octal Cdes are given fr device number 1 in a tw-character/wrd mde.

78 SC1ENrrFC DATA SYSTEMS 1649 Seventeenth Street Santa Mnica, Califrnia Phne (2 13) UP