1722A Global System Clock Streams (aka Media Clock Streams) Principles and Suggestions

Transcription

1 1722A Glbal System Clck Streams (aka Media Clck Streams) Principles and Suggestins Rb Silfvast 15-Apr-2013 versin 2 The purpse f Media Clck Streams is t distribute a cmmn timing grid t multiple ndes n a cmmn AVB netwrk, such that all ndes can use this same grid t perate n sampled data with synchrnicity in bth frequency and phase. A generalized AVB dmain must cncurrently supprt multiple, independent clck frequencies (als knwn as clck dmains). Therefre, the gptp clck cannt directly serve as the cmmn timing grid fr. Rather, the gptp clck is used by the varius ndes, as a measuring stick, t derive clck(s) based n infrmatin received in netwrk PDUs. A well established (and uncntested) mdel t fllw is standard synchrnus digital lgic design, such as a digital lgic bard, a VLSI chip, r an FPGA. In this mdel, a glbal clck is prvided frm a single pint in the system, and distributed t a large number f flip-flps acrss the system. (In an AVB netwrk, each nde is analgus t a different grup f flip-flps, and the whle LAN is analgus t the digital system). Fr digital systems that have multiple clck dmains (a very cmmn ccurrence), multiple GCLK signals are received and then distributed thrughut the system. See diagrams fr illustratin f the key cncepts. The netwrk delay in AVB is analgus t the in a digital lgic circuit. We might als say that the transmit is subject t variability, analgus t the clck-t-utput f a flip flp. Presentatin Time is analgus t the clck arrival at a listener flip flp, and matches ur mdel in that this is the when the data present n the input pin f the flip flp is handed ff t the circuit inside the flip flp. Nte that the data must arrive at the input pin befre the clck event ccurs. Same is true fr each and every stream PDU: It must arrive befre its crrespnding presentatin. This principle is fully cnsistent with best practices in prfessinal digital audi systems, as standardized in AES (Clause 5.3 Equipment Timing Relatinships ) This cmmn timing grid (CTG) is ultimately 1x the sampling rate f the, but the mechanism used t distribute the grid parameters can perate at a much lwer rate. Fr audi, the CTG is the audi sampling clck Fr vide, the CTG may be the vide frame clck r the line clck. If it is the line clck, we need a mechanism t demark ticks n the grid that crrespnd t frame start (first line in a vide frame).

2 Fr Digital Cntrl Systems, the CTG is mst likely the system sampling clck Operate n sampled (frm the first paragraph f this dc) can mean anything frm ingest (e.g. acquire frm signal input chain), t utgest (deliver t signal utput chain), t prcess via DSP, r ther usage. The pint is that all such peratins are synchrnized t a glbal clck. The timing grid must be expected t be subject t sme errr (jitter and/r phase skew) between different ndes. (In the digital lgic design mdel, this is exactly analgus t clck tree skew, which even exists inside VLSI r FPGA chips). We wuld like t minimize the netwrk bandwidth used by MCS, and therefre define a slutin that des nt require high rates. We assume that is independent f netwrk (802.1AS). We d NOT want t restrict a surce (r MCS surce) t have a fixed and cnstant relatinship t netwrk. Therefre we need t distribute clck timing infrmatin acrss the netwrk (rather than relying n ndes t be lcked t sme universal clck like GPS/TAI). Nte this assumptin is cunter t the assumptin made by SMPTE, wherein all ndes are assumed t have TAI built in. But ur MCS slutin will nt preclude applicatin f the SMPTE slutin; bth culd c-exist n the same LAN. A single master MCS surce is required t generate this glbal clck. We shuld strictly bject t the cncept f plural ndes generating plural versins f a MCS that is intended t be cmmn. The exceptin t this rule is an imprtant ne: Hw d we supprt redundant MCS? Fr example, d listeners all have t use the primary MCS (if present) and nly fall back t secndary MCS when primary ges away? Or can they use either ne at will? In the mdel prpsed by SMPTE, the single master MCS surce is GPS, r ther mechanism which delivers a universal clck t all netwrk ndes. It is the same cncept that we prpse here; but instead f using the netwrk itself t deliver sync, it relies n an external system fr this task (thus it is arguably mre cmplex). The MCS des nt need t (and prbably shuld nt) deliver every tick mark n the timing grid. Instead, it shuld deliver a sufficient supply f tick marks t allw listener t interplate tick marks t re-cnstruct the lcal timing grid, and t respnd/adapt t changes in the glbal clck frequency reasnably quickly. Because clcking can be tricky and cnfusing t a large prtin f ur user base (bth prduct makers and prduct users), and because it is critically imprtant fr prper system peratin (just like in a digital hardware design), sme gverning bdy shuld be explicit abut recmmending best practices. We expect that AVnu will fill this rle, since IEEE des nt generally gvern best practices IEEE needs t give AVnu the hks in the standards that can be used t specify best practices in a clear and bjective way

3 One example f a best practice is t distribute a master MCS t all devices (wh perate n that particular clck dmain) directly. We shuld discurage the (wrse) practice f cascading clck streams thrugh endpints. (it seems there is n gd reasn fr this, since all ndes n a LAN are reachable by the nde talking the MCS). I prpse that we cnsider changing the name f MCS t Glbal System Clck () streams. This might help t encurage the best practice described abve and avid cascading f clck streams (because nce a clck is cascaded it is, hpefully, n lnger seen as glbal ) One imprtant reasn fr a new name is because the term clck stream is already being used in reference t systems fllwing the standard. It may be very difficult t deprecate that term, and nt wrth trying t d s. We might use the term master rather than glbal. One pssible prblem with this is that master and bth begin with M. The term glbal means that this stream is available everywhere n the netwrk. It des nt imply that this is the nly clck stream that is available everywhere. As nted abve, a digital lgic design cmmnly has several glbal clcks feeding different clck dmains.

4 Digital Lgic (System) Design : Standard Best Practice Schematic Dut clcked strage asynchrnus prcessing lgic Dut clcked strage in in asynchrnus prcessing lgic Dut Dut clcked strage clcked strage in system clck surce glbal clck distributin tree in Timing Diagram Fr illustratin (scale exaggerated) CLK DATA (cnstant) async prcessing (data changing) (cnstant) async prcessing (data changing) (cnstant) async prcessing (data changing) (cnstant) hld transit (budget) hld transit (budget) hld transit (budget) Nw with clck perid >> /hld s CLK DATA Nw with clck skew / jitter CLK DATA gets wider transit budget gets smaller

5 AVB Netwrk with Glbal System Clck (GCS) streams AVB Endpint AVB Endpint Listener Talker Listener Talker clck recvery Media wrkings clck recvery Media wrkings Netwrk Infrastructure system clck surce lcated in any AVB endpint (shuld be stensibly designated as the master system clck ) AVB Endpint Listener Talker Nte clck recvery is a 1722 listener functin Media wrkings clck recvery

6 Cnceptual Timing Diagram fr AVB Media Synchrnizatin and Delivery Crrespnds t ne Media Clck dmain n an AVB netwrk. Fr illustratin purpses, nt t scale Glbal System Clck activity netwrk transit d netwrk transit d lst d netwrk transit arrives receiver creates base clck arrives receiver creates base clck missing receiver free-wheels thrugh missing stamps arrives receiver creates base clck cntains stamps every N samples T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8 T 13 T cmpare/match t lcal gptp clck gptp clck is asynchrnus t clck. and used as a measuring stick fr incming stamps lcal PLL phase aligned recvered clck this is the cmmn timing grid fr all ndes which perate in this clck dmain Media Data Pipeline talker cnfigured fr 6 samples per talker activity DATA SET A cllect samples, build DATA SET B cllect samples, build DATA SET C cllect samples, build previus data sets in transit netwrk transprt DATA SET A transit budget DATA SET B transit budget DATA SET C transit budget subsequent data sets in transit listener activity rx rx delivered with nminal margin delivered with lts f margin P DATA SET A decde, use samples P DATA SET B decde, use samples rx delivered just barely in P DATA SET C decde, use samples Overall latency (nt cunting applicatin prcessing, ADC, DAC, etc) presentatin stamps P must land n the cmmn grid