Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements

Size: px
Start display at page:

Download "Sequential Digital Design. Laboratory Manual. Experiment #3. Flip Flop Storage Elements"

Transcription

1 The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #3 Flip Flop Storage Elements

2 Objectives To become familiar with flip-flops. To implement and observe the operation of different flip-flops. To become familiar with flip-flops' timing diagrams. Theoretical Background Flip Flops Flip-Flop is the common name given to two-state devices which offer basic memory for sequential logic operations. Flip-flops are heavily used for digital data storage and transfer and are commonly used in banks called "registers" for the storage of binary numerical data. For a latch, the output essentially responds immediately to changes on the input lines (and possibly the presence of a clock pulse). A flip-flop is designed to change its output at the edge of a controlling clock signal. 2

3 Types of Flip-Flops There are several types of flip-flops and they are D, S-R, J-K and T flip-flops, but the two most important kinds are the D and J-K flip-flops. S-R Flip-Flop An S-R flip-flop is similar to an S-R latch in that S = 1 sets the Q output to 1, and R = 1 resets the Q output to 0. The essential difference is that the flip-flop has a clock input, and the Q output can change only after an active clock edge. The figure below shows an S-R flip-flop constructed from two S-R latches and gates. This flipflop changes state after the rising edge of the clock. The circuit is often referred to as a masterslave flip-flop. The following table shows the operation summary of the SR Flip-Flop. S R CLK Q Q' 0 0 Q (No Change) Q' (No Change) (undefined) 0 (undefined) 3

4 For the master-slave flip-flop, if the inputs change while the clock is low, the flip-flop output may be incorrect. Give a look at the following timing diagram. D Flip-Flop We can design a flip flop using two ways. The first one is the construction of a D flip-flop with two D latches and an inverter, as shown in the figure below. The first latch is called the master and the second the slave. The circuit samples the D input and changes its output Q only at the positive edge of the synchronizing or controlling clock (designated as CLK). 4

5 Here is the timing diagram for the master-slave D flip-flop. Another construction of an edge-triggered D flip-flop uses three SR latches as shown in the figure below. Two latches respond to the external D (data) and CLK (clock) inputs. The third latch provides the outputs for the flip-flop. 5

6 Below is the operation summary table for the D flip-flop. D CLK Q The graphic symbol for the edge-triggered D flip-flop is shown below. It is similar to the symbol used for the D latch, except for the arrowhead-like symbol in front of the letter Clk, designating a dynamic input. The dynamic indicator (>) denotes the fact that the flip-flop responds to the edge transition of the clock. A bubble outside the block adjacent to the dynamic indicator designates a negative edge for triggering the circuit. The absence of a bubble designates a positive-edge response. J-K Flip-Flop The most economical and efficient flip-flop constructed in this manner is the edge-triggered D flip-flop, because it requires the smallest number of gates. But other types of flip-flops still can be constructed by using the D flip-flop and external logic. Two flip-flops less widely used in the design of digital systems are the JK and T flip-flops. There are three operations that can be performed with a flip-flop: Set it to 1, reset it to 0, or complement its output. With only a single input, the D flip-flop can set or reset the output, depending on the value of the D input immediately before the clock transition. Synchronized by a clock signal, the JK flip-flop has two inputs and performs all three operations. The circuit diagram of a JK flip-flop constructed with a D flip-flop and gates is shown below. 6

7 The J input sets the flip-flop to 1, the K input resets it to 0, and when both inputs are enabled, the output is complemented. The J-K flip-flop can be an extended version of the S-R flip-flop. This is the same circuit as for the S-R master-slave flip-flop, except S and R have been replaced with J and K, and the Q and Q outputs are feeding back into the input gates. The following table shows the operation summary for J-K flip-flop. J K CLK Q 0 0 Q (No Change) Q' (Complement) 7

8 And here is the timing diagram for a J-K flip-flop. T Flip-Flop The T (toggle) flip-flop is a complementing flip-flop and can be obtained from a JK flip-flop when inputs J and K are tied together, or with a D flip-flop and an exclusive-or gate. T flipflop is frequently used in building counters. The following table shows the operation summary for T flip-flop. J CLK Q 0 Q (No Change) 1 Q' (Complement) 8

9 Flip-Flop Applications Frequency Division The process of dividing or reducing the output frequency to half of its input signal frequency is called Frequency division. As the name implies, the frequency divider circuits are used to produce the digital signal output exactly half the input frequency. This means if we process an input signal of frequency 100 Hz, then the frequency divider circuit will provide the output of 50 Hz. Simple Traffic Light This is one simple application of D-type flip-flops. Traffic light simulation using two D-type flipflops, an AND gate and a clock, provided to one of flip-flops. Timing of the lights can be maintained by changing the clock frequency. Higher the clock frequency, faster will the lights blink and vice-versa. 9

10 Question Complete the following timing diagram for the previous circuit. Solution 10

11 Light On/Off Switch circuit The T flip-flop can be used as a toggle switch to switch a lamp on or off. But what if the switch in the previous circuit has bouncing problem, will the circuit work correctly? If not, how can we solve it? Of course, the circuit will not work correctly as there is so many presses on the switch at a small amount of time. If the number of presses was odd, it will work correctly. But if it was even, the lamp light will not change. We can solve it by using a debouncing circuit. 11

12 Lab Work Equipments required Circuit Wizard Simulation Software. KL trainer kit. IC 7404(NOT), IC 7408(AND), IC 7432(OR), IC 7400(NAND), IC 7402(NOR). Connecting wires and Breadboard. The Datasheets of the IC s. Implementation Use Circuit Wizard to design, test and simulate the required circuits, then implement the circuits practically in the laboratory. 1. Construct RS flip-flop using Basic Logic Gates. 2. Construct D flip-flop using D latch. 3. Construct D flip-flop using RS flip-flop. 4. Construct J-K flip-flop using D flip-flop. 5. Convert a J-K flip-flop to a T flip-flop. 6. Construct Frequency Divisor Circuit using J-K flip-flop. 7. Construct the simple traffic lights circuit. Exercises: Good Luck 12

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters The Islamic University of Gaza Engineering Faculty Department of Computer Engineering Spring 2018 ECOM 2022 Khaleel I. Shaheen Sequential Digital Design Laboratory Manual Experiment #7 Counters Objectives

More information

Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany

Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany Digital Logic Design Sequential Circuits Dr. Basem ElHalawany Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs

More information

D Latch (Transparent Latch)

D Latch (Transparent Latch) D Latch (Transparent Latch) -One way to eliminate the undesirable condition of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 1 at the same time. This is done

More information

Introduction to Sequential Circuits

Introduction to Sequential Circuits Introduction to Sequential Circuits COE 202 Digital Logic Design Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals Presentation Outline Introduction to Sequential Circuits Synchronous

More information

Other Flip-Flops. Lecture 27 1

Other Flip-Flops. Lecture 27 1 Other Flip-Flops Other types of flip-flops can be constructed by using the D flip-flop and external logic. Two flip-flops less widely used in the design of digital systems are the JK and T flip-flops.

More information

COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem ahmadsm AT kfupm Phone: Office:

COE 202: Digital Logic Design Sequential Circuits Part 1. Dr. Ahmad Almulhem   ahmadsm AT kfupm Phone: Office: COE 202: Digital Logic Design Sequential Circuits Part 1 Dr. Ahmad Almulhem Email: ahmadsm AT kfupm Phone: 860-7554 Office: 22-324 Objectives Sequential Circuits Memory Elements Latches Flip-Flops Combinational

More information

ECE 341. Lecture # 2

ECE 341. Lecture # 2 ECE 341 Lecture # 2 Instructor: Zeshan Chishti zeshan@pdx.edu October 1, 2014 Portland State University Announcements Course website reminder: http://www.ece.pdx.edu/~zeshan/ece341.htm Homework 1: Will

More information

Chapter. Synchronous Sequential Circuits

Chapter. Synchronous Sequential Circuits Chapter 5 Synchronous Sequential Circuits Logic Circuits- Review Logic Circuits 2 Combinational Circuits Consists of logic gates whose outputs are determined from the current combination of inputs. Performs

More information

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M CSE-4523 Latches and Flip-flops Dr. Izadi NOR gate property: A B Z A B Z Cross coupled NOR gates: S M S R M R S M R S R S R M S S M R R S ' Gate R Gate S R S G R S R (t+) S G R Flip_flops:. S-R flip-flop

More information

CPE 200L LABORATORY 3: SEQUENTIAL LOGIC CIRCUITS UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: SR FLIP-FLOP/LATCH

CPE 200L LABORATORY 3: SEQUENTIAL LOGIC CIRCUITS UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: SR FLIP-FLOP/LATCH CPE 200L LABORATORY 3: SEUENTIAL LOGIC CIRCUITS DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING UNIVERSITY OF NEVADA, LAS VEGAS GOALS: Learn to use Function Generator and Oscilloscope on the breadboard.

More information

EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP

EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP 1 Chapter Overview Latches Gated Latches Edge-triggered flip-flops Master-slave flip-flops Flip-flop operating characteristics Flip-flop applications

More information

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall Objective: - Dealing with the operation of simple sequential devices. Learning invalid condition in

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 6 Following the slides of Dr. Ahmed H. Madian ذو الحجة 1438 ه Winter

More information

Experiment 8 Introduction to Latches and Flip-Flops and registers

Experiment 8 Introduction to Latches and Flip-Flops and registers Experiment 8 Introduction to Latches and Flip-Flops and registers Introduction: The logic circuits that have been used until now were combinational logic circuits since the output of the device depends

More information

Unit 11. Latches and Flip-Flops

Unit 11. Latches and Flip-Flops Unit 11 Latches and Flip-Flops 1 Combinational Circuits A combinational circuit consists of logic gates whose outputs, at any time, are determined by combining the values of the inputs. For n input variables,

More information

ELCT201: DIGITAL LOGIC DESIGN

ELCT201: DIGITAL LOGIC DESIGN ELCT201: DIGITAL LOGIC DESIGN Dr. Eng. Haitham Omran, haitham.omran@guc.edu.eg Dr. Eng. Wassim Alexan, wassim.joseph@guc.edu.eg Lecture 7 Following the slides of Dr. Ahmed H. Madian محرم 1439 ه Winter

More information

LAB 7. Latches & Flip Flops

LAB 7. Latches & Flip Flops بسام عب د الكريم جاد هللا النبريص Bass am Ak J Alnabr iss Islamic University of Gaza Faculty of Engineering Computer Engineering Dept. Digital Design Lab : ECOM 2112 Fall 2016 Eng. Bassam Nabriss LAB 7

More information

EET2411 DIGITAL ELECTRONICS

EET2411 DIGITAL ELECTRONICS 5-8 Clocked D Flip-FlopFlop One data input. The output changes to the value of the input at either the positive going or negative going clock trigger. May be implemented with a J-K FF by tying the J input

More information

Logic Design. Flip Flops, Registers and Counters

Logic Design. Flip Flops, Registers and Counters Logic Design Flip Flops, Registers and Counters Introduction Combinational circuits: value of each output depends only on the values of inputs Sequential Circuits: values of outputs depend on inputs and

More information

LAB #4 SEQUENTIAL LOGIC CIRCUIT

LAB #4 SEQUENTIAL LOGIC CIRCUIT LAB #4 SEQUENTIAL LOGIC CIRCUIT OBJECTIVES 1. To learn how basic sequential logic circuit works 2. To test and investigate the operation of various latch and flip flop circuits INTRODUCTIONS Sequential

More information

Chapter 6 Digital Circuit 6-5 Department of Mechanical Engineering

Chapter 6 Digital Circuit 6-5 Department of Mechanical Engineering MEMS1082 Chapter 6 Digital Circuit 6-5 General digital system D Flip-Flops, The D flip-flop is a modification of the clocked SR flip-flop. The D input goes directly into the S input and the complement

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

Rangkaian Sekuensial. Flip-flop

Rangkaian Sekuensial. Flip-flop Rangkaian Sekuensial Rangkaian Sekuensial Flip-flop Combinational versus Sequential Functions Logic functions are categorized as being either combinational (sometimes referred to as combinatorial) or sequential.

More information

DIGITAL CIRCUIT LOGIC UNIT 11: SEQUENTIAL CIRCUITS (LATCHES AND FLIP-FLOPS)

DIGITAL CIRCUIT LOGIC UNIT 11: SEQUENTIAL CIRCUITS (LATCHES AND FLIP-FLOPS) DIGITAL CIRCUIT LOGIC UNIT 11: SEQUENTIAL CIRCUITS (LATCHES AND FLIP-FLOPS) 1 iclicker Question 16 What should be the MUX inputs to implement the following function? (4 minutes) f A, B, C = m(0,2,5,6,7)

More information

RS flip-flop using NOR gate

RS flip-flop using NOR gate RS flip-flop using NOR gate Triggering and triggering methods Triggering : Applying train of pulses, to set or reset the memory cell is known as Triggering. Triggering methods:- There are basically two

More information

Synchronous Sequential Logic

Synchronous Sequential Logic Synchronous Sequential Logic -A Sequential Circuit consists of a combinational circuit to which storage elements are connected to form a feedback path. The storage elements are devices capable of storing

More information

Chapter 5 Synchronous Sequential Logic

Chapter 5 Synchronous Sequential Logic Chapter 5 Synchronous Sequential Logic Chih-Tsun Huang ( 黃稚存 ) http://nthucad.cs.nthu.edu.tw/~cthuang/ Department of Computer Science National Tsing Hua University Outline Introduction Storage Elements:

More information

Chapter 6. Flip-Flops and Simple Flip-Flop Applications

Chapter 6. Flip-Flops and Simple Flip-Flop Applications Chapter 6 Flip-Flops and Simple Flip-Flop Applications Basic bistable element It is a circuit having two stable conditions (states). It can be used to store binary symbols. J. C. Huang, 2004 Digital Logic

More information

Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers

Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers EEE 304 Experiment No. 07 Name Of The Experiment: Sequential circuit design Latch, Flip-flop and Registers Important: Submit your Prelab at the beginning of the lab. Prelab 1: Construct a S-R Latch and

More information

Chapter 8 Sequential Circuits

Chapter 8 Sequential Circuits Philadelphia University Faculty of Information Technology Department of Computer Science Computer Logic Design By 1 Chapter 8 Sequential Circuits 1 Classification of Combinational Logic 3 Sequential circuits

More information

Engr354: Digital Logic Circuits

Engr354: Digital Logic Circuits Engr354: igital Circuits Chapter 7 Sequential Elements r. Curtis Nelson Sequential Elements In this chapter you will learn about: circuits that can store information; Basic cells, latches, and flip-flops;

More information

Digital Circuits ECS 371

Digital Circuits ECS 371 igital Circuits ECS 371 r. Prapun Suksompong prapun@siit.tu.ac.th Lecture 17 Office Hours: BK 3601-7 Monday 9:00-10:30, 1:30-3:30 Tuesday 10:30-11:30 1 Announcement Reading Assignment: Chapter 7: 7-1,

More information

MC9211 Computer Organization

MC9211 Computer Organization MC9211 Computer Organization Unit 2 : Combinational and Sequential Circuits Lesson2 : Sequential Circuits (KSB) (MCA) (2009-12/ODD) (2009-10/1 A&B) Coverage Lesson2 Outlines the formal procedures for the

More information

Sequential Logic and Clocked Circuits

Sequential Logic and Clocked Circuits Sequential Logic and Clocked Circuits Clock or Timing Device Input Variables State or Memory Element Combinational Logic Elements From combinational logic, we move on to sequential logic. Sequential logic

More information

Experiment # 9. Clock generator circuits & Counters. Digital Design LAB

Experiment # 9. Clock generator circuits & Counters. Digital Design LAB Digital Design LAB Islamic University Gaza Engineering Faculty Department of Computer Engineering Fall 2012 ECOM 2112: Digital Design LAB Eng: Ahmed M. Ayash Experiment # 9 Clock generator circuits & Counters

More information

LATCHES & FLIP-FLOP. Chapter 7

LATCHES & FLIP-FLOP. Chapter 7 LATCHES & FLIP-FLOP Chapter 7 INTRODUCTION Latch and flip flops are categorized as bistable devices which have two stable states,called SET and RESET. They can retain either of this states indefinitely

More information

Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering

Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering Sri Vidya College of Engineering And Technology Virudhunagar 626 005 Department of Electrical and Electronics Engineering Year/ Semester/ Class : II/ III/ EEE Academic Year: 2017-2018 Subject Code/ Name:

More information

DIGITAL CIRCUIT COMBINATORIAL LOGIC

DIGITAL CIRCUIT COMBINATORIAL LOGIC DIGITAL CIRCUIT COMBINATORIAL LOGIC Logic levels: one zero true false high low CMOS logic levels: 1 => 0.7 V DD 0.4 V DD = noise margin 0 =< 0.3 V DD Positive logic: high = 1 = true low = 0 = false Negative

More information

Unit 9 Latches and Flip-Flops. Dept. of Electrical and Computer Eng., NCTU 1

Unit 9 Latches and Flip-Flops. Dept. of Electrical and Computer Eng., NCTU 1 Unit 9 Latches and Flip-Flops Dept. of Electrical and Computer Eng., NCTU 1 9.1 Introduction Dept. of Electrical and Computer Eng., NCTU 2 What is the characteristic of sequential circuits in contrast

More information

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS

DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS COURSE / CODE DIGITAL SYSTEM FUNDAMENTALS (ECE421) DIGITAL ELECTRONICS FUNDAMENTAL (ECE422) LATCHES and FLIP-FLOPS In the same way that logic gates are the building blocks of combinatorial circuits, latches

More information

INTRODUCTION TO SEQUENTIAL CIRCUITS

INTRODUCTION TO SEQUENTIAL CIRCUITS NOTE: Explanation Refer Class Notes Digital Circuits(15EECC203) INTRODUCTION TO SEQUENTIAL CIRCUITS by Nagaraj Vannal, Asst.Professor, School of Electronics Engineering, K.L.E. Technological University,

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

DALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 220. Experiment 4 - Latches and Flip-Flops

DALHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 220. Experiment 4 - Latches and Flip-Flops DLHOUSIE UNIVERSITY Department of Electrical & Computer Engineering Digital Circuits - ECED 0 Experiment - Latches and Flip-Flops Objectives:. To implement an RS latch memory element. To implement a JK

More information

Chapter 4. Logic Design

Chapter 4. Logic Design Chapter 4 Logic Design 4.1 Introduction. In previous Chapter we studied gates and combinational circuits, which made by gates (AND, OR, NOT etc.). That can be represented by circuit diagram, truth table

More information

Asynchronous (Ripple) Counters

Asynchronous (Ripple) Counters Circuits for counting events are frequently used in computers and other digital systems. Since a counter circuit must remember its past states, it has to possess memory. The chapter about flip-flops introduced

More information

Synchronous Sequential Logic

Synchronous Sequential Logic MEC520 디지털공학 Synchronous Sequential Logic Jee-Hwan Ryu School of Mechanical Engineering Sequential Circuits Outputs are function of inputs and present states Present states are supplied by memory elements

More information

CHAPTER 4: Logic Circuits

CHAPTER 4: Logic Circuits CHAPTER 4: Logic Circuits II. Sequential Circuits Combinational circuits o The outputs depend only on the current input values o It uses only logic gates, decoders, multiplexers, ALUs Sequential circuits

More information

(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay)  CSC S.J. Park. Announcement Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 7 (07 Feb 2008) 1 Announcement 2 1 Combinational vs. Sequential Logic Combinational Logic Memoryless Outputs

More information

Flip-Flops and Sequential Circuit Design

Flip-Flops and Sequential Circuit Design Flip-Flops and Sequential Circuit Design ECE 52 Summer 29 Reading ssignment Brown and Vranesic 7 Flip-Flops, Registers, Counters and a Simple Processor 7.5 T Flip-Flop 7.5. Configurable Flip-Flops 7.6

More information

EE292: Fundamentals of ECE

EE292: Fundamentals of ECE EE292: Fundamentals of ECE Fall 2012 TTh 10:00-11:15 SEB 1242 Lecture 23 121120 http://www.ee.unlv.edu/~b1morris/ee292/ 2 Outline Review Combinatorial Logic Sequential Logic 3 Combinatorial Logic Circuits

More information

To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit.

To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit. 6.1 Objectives To design a sequential logic circuit using D-Flip-flop. To implement the designed circuit. 6.2 Sequential Logic So far we have implemented digital circuits whose outputs depend only on its

More information

Sequential Logic. E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1

Sequential Logic. E&CE 223 Digital Circuits and Systems (A. Kennings) Page 1 Sequential Logic E&CE 223 igital Circuits and Systems (A. Kennings) Page 1 Sequential Circuits Have considered only combinational circuits in which circuit outputs are determined entirely by current circuit

More information

Lecture 8: Sequential Logic

Lecture 8: Sequential Logic Lecture 8: Sequential Logic Last lecture discussed how we can use digital electronics to do combinatorial logic we designed circuits that gave an immediate output when presented with a given set of inputs

More information

Chapter 5: Synchronous Sequential Logic

Chapter 5: Synchronous Sequential Logic Chapter 5: Synchronous Sequential Logic NCNU_2016_DD_5_1 Digital systems may contain memory for storing information. Combinational circuits contains no memory elements the outputs depends only on the inputs

More information

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

Introduction. NAND Gate Latch.  Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1 2007 Introduction BK TP.HCM FLIP-FLOP So far we have seen Combinational Logic The output(s) depends only on the current values of the input variables Here we will look at Sequential Logic circuits The

More information

CPS311 Lecture: Sequential Circuits

CPS311 Lecture: Sequential Circuits CPS311 Lecture: Sequential Circuits Last revised August 4, 2015 Objectives: 1. To introduce asynchronous and synchronous flip-flops (latches and pulsetriggered, plus asynchronous preset/clear) 2. To introduce

More information

NEW MEXICO STATE UNIVERSITY Electrical and Computer Engineering Department. EE162 Digital Circuit Design Fall Lab 5: Latches & Flip-Flops

NEW MEXICO STATE UNIVERSITY Electrical and Computer Engineering Department. EE162 Digital Circuit Design Fall Lab 5: Latches & Flip-Flops NEW MEXICO STATE UNIVERSITY Electrical and Computer Engineering Department EE162 Digital Circuit Design Fall 2012 OBJECTIVES: Lab 5: Latches & Flip-Flops The objective of this lab is to examine and understand

More information

UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram

UNIT III. Combinational Circuit- Block Diagram. Sequential Circuit- Block Diagram UNIT III INTRODUCTION In combinational logic circuits, the outputs at any instant of time depend only on the input signals present at that time. For a change in input, the output occurs immediately. Combinational

More information

Sequential Circuits: Latches & Flip-Flops

Sequential Circuits: Latches & Flip-Flops Sequential Circuits: Latches & Flip-Flops Overview Storage Elements Latches SR, JK, D, and T Characteristic Tables, Characteristic Equations, Eecution Tables, and State Diagrams Standard Symbols Flip-Flops

More information

Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date:

Digital Fundamentals. Lab 5 Latches & Flip-Flops CETT Name: Date: Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Rev. 3 (7/2015) J. Bradbury Digital Fundamentals CETT 1425 Lab 5 Latches & Flip-Flops

More information

Synchronous Sequential Logic

Synchronous Sequential Logic Synchronous Sequential Logic Ranga Rodrigo August 2, 2009 1 Behavioral Modeling Behavioral modeling represents digital circuits at a functional and algorithmic level. It is used mostly to describe sequential

More information

Sequential Logic Circuits

Sequential Logic Circuits Sequential Logic Circuits By Dr. M. Hebaishy Digital Logic Design Ch- Rem.!) Types of Logic Circuits Combinational Logic Memoryless Outputs determined by current values of inputs Sequential Logic Has memory

More information

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops Objective Construct a two-bit binary decoder. Study multiplexers (MUX) and demultiplexers (DEMUX). Construct an RS flip-flop from discrete gates.

More information

Digital Fundamentals: A Systems Approach

Digital Fundamentals: A Systems Approach Digital Fundamentals: A Systems Approach Latches, Flip-Flops, and Timers Chapter 6 Traffic Signal Control Traffic Signal Control: State Diagram Traffic Signal Control: Block Diagram Traffic Signal Control:

More information

Sequential Logic Basics

Sequential Logic Basics Sequential Logic Basics Unlike Combinational Logic circuits that change state depending upon the actual signals being applied to their inputs at that time, Sequential Logic circuits have some form of inherent

More information

Slide 1. Flip-Flops. Cross-NOR SR flip-flop S R Q Q. hold reset set not used. Cross-NAND SR flip-flop S R Q Q. not used reset set hold 1 Q.

Slide 1. Flip-Flops. Cross-NOR SR flip-flop S R Q Q. hold reset set not used. Cross-NAND SR flip-flop S R Q Q. not used reset set hold 1 Q. Slide Flip-Flops Cross-NOR SR flip-flop Reset Set Cross-NAND SR flip-flop Reset Set S R reset set not used S R not used reset set 6.7 Digital ogic Slide 2 Clocked evel-triggered NAND SR Flip-Flop S R SR

More information

Digital Circuit And Logic Design I. Lecture 8

Digital Circuit And Logic Design I. Lecture 8 Digital Circuit And Logic Design I Lecture 8 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Analysis Panupong Sornkhom, 2005/2

More information

Digital Circuit And Logic Design I

Digital Circuit And Logic Design I Digital Circuit And Logic Design I Lecture 8 Outline Sequential Logic Design Principles (1) 1. Introduction 2. Latch and Flip-flops 3. Clocked Synchronous State-Machine Panupong Sornkhom, 2005/2 2 1 Sequential

More information

AIM: To study and verify the truth table of logic gates

AIM: To study and verify the truth table of logic gates EXPERIMENT: 1- LOGIC GATES AIM: To study and verify the truth table of logic gates LEARNING OBJECTIVE: Identify various Logic gates and their output. COMPONENTS REQUIRED: KL-31001 Digital Logic Lab( Main

More information

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012

Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 1 McGill University Faculty of Engineering ECSE-221B Introduction to Computer Engineering Department of Electrical and Computer Engineering Mid-Term Examination Winter 2012 Examiner: Rola Harmouche Date:

More information

CHAPTER1: Digital Logic Circuits

CHAPTER1: Digital Logic Circuits CS224: Computer Organization S.KHABET CHAPTER1: Digital Logic Circuits 1 Sequential Circuits Introduction Composed of a combinational circuit to which the memory elements are connected to form a feedback

More information

Chapter 5 Sequential Circuits

Chapter 5 Sequential Circuits Logic and Computer Design Fundamentals Chapter 5 Sequential Circuits Part 2 Sequential Circuit Design Charles Kime & Thomas Kaminski 28 Pearson Education, Inc. (Hyperlinks are active in View Show mode)

More information

Digital Circuits 4: Sequential Circuits

Digital Circuits 4: Sequential Circuits Digital Circuits 4: Sequential Circuits Created by Dave Astels Last updated on 2018-04-20 07:42:42 PM UTC Guide Contents Guide Contents Overview Sequential Circuits Onward Flip-Flops R-S Flip Flop Level

More information

The word digital implies information in computers is represented by variables that take a limited number of discrete values.

The word digital implies information in computers is represented by variables that take a limited number of discrete values. Class Overview Cover hardware operation of digital computers. First, consider the various digital components used in the organization and design. Second, go through the necessary steps to design a basic

More information

B.Tech CSE Sem. 3 15CS202 DIGITAL SYSTEM DESIGN (Regulations 2015) UNIT -IV

B.Tech CSE Sem. 3 15CS202 DIGITAL SYSTEM DESIGN (Regulations 2015) UNIT -IV B.Tech CSE Sem. 3 5CS22 DIGITAL SYSTEM DESIGN (Regulations 25) UNIT -IV SYNCHRONOUS SEQUENTIAL CIRCUITS OUTLINE FlipFlops SR,D,JK,T Analysis of Synchronous Sequential Circuit State Reduction and Assignment

More information

Flip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001

Flip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001 Flip-Flops and Related Devices Wen-Hung Liao, Ph.D. 4/11/2001 Objectives Recognize the various IEEE/ANSI flip-flop symbols. Use state transition diagrams to describe counter operation. Use flip-flops in

More information

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic Chapter 5. Synchronous Sequential Logic 1 5.1 Introduction Electronic products: ability to send, receive, store, retrieve, and process information in binary format Dependence on past values of inputs Sequential

More information

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING

DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING DRONACHARYA GROUP OF INSTITUTIONS, GREATER NOIDA Affiliated to Mahamaya Technical University, Noida Approved by AICTE DEPARTMENT OF COMPUTER SCIENCE & ENGINEERING Lab Manual for Computer Organization Lab

More information

Logic Design ( Part 3) Sequential Logic- Finite State Machines (Chapter 3)

Logic Design ( Part 3) Sequential Logic- Finite State Machines (Chapter 3) Logic esign ( Part ) Sequential Logic- Finite State Machines (Chapter ) Based on slides McGraw-Hill Additional material 00/00/006 Lewis/Martin Additional material 008 Roth Additional material 00 Taylor

More information

Flip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari

Flip Flop. S-R Flip Flop. Sequential Circuits. Block diagram. Prepared by:- Anwar Bari Sequential Circuits The combinational circuit does not use any memory. Hence the previous state of input does not have any effect on the present state of the circuit. But sequential circuit has memory

More information

INC 253 Digital and electronics laboratory I

INC 253 Digital and electronics laboratory I INC 253 Digital and electronics laboratory I Laboratory 9 Sequential Circuit Author: ID Co-Authors: 1. ID 2. ID 3. ID Experiment Date: Report received Date: Comments For Instructor Full Marks Pre lab 10

More information

Synchronous Sequential Logic

Synchronous Sequential Logic Synchronous Sequential Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2012 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Sequential

More information

Introduction to Microprocessor & Digital Logic

Introduction to Microprocessor & Digital Logic ME262 Introduction to Microprocessor & Digital Logic (Sequential Logic) Summer 2 Sequential Logic Definition The output(s) of a sequential circuit depends d on the current and past states of the inputs,

More information

Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active.

Flip-Flops. Because of this the state of the latch may keep changing in circuits with feedback as long as the clock pulse remains active. Flip-Flops Objectives The objectives of this lesson are to study: 1. Latches versus Flip-Flops 2. Master-Slave Flip-Flops 3. Timing Analysis of Master-Slave Flip-Flops 4. Different Types of Master-Slave

More information

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET

Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET Dev Bhoomi Institute Of Technology Department of Electronics and Communication Engineering PRACTICAL INSTRUCTION SHEET LABORATORY MANUAL EXPERIMENT NO. 1 ISSUE NO. : ISSUE DATE: REV. NO. : REV. DATE :

More information

Review of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state.

Review of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state. pp. 4-9 Krishi Sanskriti Publications http://www.krishisanskriti.org/jbaer.html Review of Flip-Flop Divya Aggarwal Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi Abstract:

More information

Logic Gates, Timers, Flip-Flops & Counters. Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur

Logic Gates, Timers, Flip-Flops & Counters. Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur Logic Gates, Timers, Flip-Flops & Counters Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur Logic Gates Transistor NOT Gate Let I C be the collector current.

More information

CHAPTER 1 LATCHES & FLIP-FLOPS

CHAPTER 1 LATCHES & FLIP-FLOPS CHAPTER 1 LATCHES & FLIP-FLOPS 1 Outcome After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output

More information

Physics 323. Experiment # 10 - Digital Circuits

Physics 323. Experiment # 10 - Digital Circuits Physics 323 Experiment # 10 - Digital Circuits Purpose This is a brief introduction to digital (logic) circuits using both combinational and sequential logic. The basic building blocks will be the Transistor

More information

Synchronous Sequential Logic

Synchronous Sequential Logic Synchronous Sequential Logic ( 范倫達 ), Ph. D. Department of Computer Science National Chiao Tung University Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.edu.tw/~ldvan/ Outlines Sequential

More information

ELE2120 Digital Circuits and Systems. Tutorial Note 7

ELE2120 Digital Circuits and Systems. Tutorial Note 7 ELE2120 Digital Circuits and Systems Tutorial Note 7 Outline 1. Sequential Circuit 2. Gated SR Latch 3. Gated D-latch 4. Edge-Triggered D Flip-Flop 5. Asynchronous and Synchronous reset Sequential Circuit

More information

Latches, Flip-Flops, and Registers. Dr. Ouiem Bchir

Latches, Flip-Flops, and Registers. Dr. Ouiem Bchir Latches, Flip-Flops, and Registers (Chapter #7) Dr. Ouiem Bchir The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and Kinney. Sequential

More information

The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both).

The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both). 1 The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both). The value that is stored in a flip-flop when the clock pulse occurs

More information

Solar Power for Small Hall

Solar Power for Small Hall Solar Power for Small Hall [image from www.speedace.info] The university is interested in installing a Solar Power Generating Facility on the roof of Small Hall. Project not official at university level

More information

Combinational vs Sequential

Combinational vs Sequential Combinational vs Sequential inputs X Combinational Circuits outputs Z A combinational circuit: At any time, outputs depends only on inputs Changing inputs changes outputs No regard for previous inputs

More information

Final Exam review: chapter 4 and 5. Supplement 3 and 4

Final Exam review: chapter 4 and 5. Supplement 3 and 4 Final Exam review: chapter 4 and 5. Supplement 3 and 4 1. A new type of synchronous flip-flop has the following characteristic table. Find the corresponding excitation table with don t cares used as much

More information

(Refer Slide Time: 2:05)

(Refer Slide Time: 2:05) (Refer Slide Time: 2:05) Digital Circuits and Systems Prof. S. Srinivasan Department of Electrical Engineering Indian Institute of Technology, Madras Triggering Mechanisms of Flip Flops and Counters Lecture

More information

FE REVIEW LOGIC. The AND gate. The OR gate A B AB A B A B 0 1 1

FE REVIEW LOGIC. The AND gate. The OR gate A B AB A B A B 0 1 1 FE REVIEW LOGIC The AD gate f A, B AB The AD gates output will achieve its active state, ACTIVE HIGH, when BOTH of its inputs achieve their active state, ACTIVE E HIGH. A B AB f ( A, B) AB m (3) The OR

More information

Introduction to Digital Logic Missouri S&T University CPE 2210 Flip-Flops

Introduction to Digital Logic Missouri S&T University CPE 2210 Flip-Flops Introduction to igital Logic Missouri S&T University CPE 2210 Flip-Flops Egemen K. Çetinkaya Egemen K. Çetinkaya epartment of Electrical & Computer Engineering Missouri University of Science and Technology

More information

Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours

Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours Digital Networks and Systems Laboratory 2 Basic Digital Building Blocks Time 4 hours Aim To investigate the basic digital circuit building blocks constructed from combinatorial logic or dedicated Integrated

More information