CSE 275 Digital Design Lab Lab 8 Serial Adder/Subtractor Penn State Erie, The Behrend College Fall Semester 2007 Number of Lab Periods: 2

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1 1 Discussion CSE 275 Digital Design Lab Lab 8 Serial Adder/Subtractor Penn State Erie, The Behrend College Fall Semester 2007 Number of Lab Periods: 2 The purpose of this lab is to design, simulate, and implement a 4-bit serial adder/subtractor (SADDSUB). A block diagram of the unit is shown below. The SADDSUB has two internal 4- bit shift registers (REGA and REGB), a single 1-bit FA with a carry-hold flip-flop, a 2 s complement unit with a carry-hold flip-flop, and a 2-to-1 MUX. Its inputs are a 4-bit data input (D3~D0), a rising edge trigged clock signal (), two clock-enable signals (CE_A and CE_B), a parallel load/shift selector (LOADH_SHIFTL), an asynchronous reset signal (CLR), and an add/subtract selector (ADDL_SUBH). Its outputs are the outputs of 4-bit shift register A (QA3~QA0) and 4-bit shift register B (QB3~QB0). The 4-bit shift register B is used to store the result of the addition and subtraction. D3~D0 CE_A CE B LOADH_SHIFTL CLR CE REGA D3 D2 D1 D0 SI LOAD CLR QA3~QA0 QA3~QA1 QA0 CE D3 D2 D1 D0 REGB SI LOAD CLR QB3~QB0 QB3~QB1 QB0 ADDL_SUBH MUX BCOMP B 2COMP CO CI C FDC D CLR Q CI A B CO FA SUM C D Q FDC CLR Figure 1 Block Diagram of the Serial Adder/Subtractor 1

2 The clock-enable signals are passed to the internal registers. These are used to enable/disable the clock signal coming into the corresponding register (high = enable). That is, if an internal register s clock-enable signal is low (disabled), then the register holds its state even though a rising edge clock signal comes. This allows you to work on one register while the other remains unchanged. Operation begins with resetting the unit by setting the CLR line high then dropping it low again. The reset signal clears the internal registers and the carry-hold flip-flops. Operation continues by loading the registers with data. When the SADDSUB is in parallel load mode (LOADH_SHIFTL= 1 ), the two registers are loaded, each at a clock rising edge, via the shared 4-bit data input D3~D0 (so it takes two clock rising edges to load both registers). For example, to load REGA, we set CE_A and LOADH_SHIFTL high, place the data on the input data lines, then cycle the clock. Once the registers are loaded with data, the SADDSUB is placed in shift-compute mode (LOADH_SHIFTL= 0 ). In this mode, the operation of addition is performed in a serial way, i.e. only the least significant bit (LSB) of the data in the register A is added to the LSB bit of the data in the register B during one clock cycle (Notice that the LSB bits of both registers are the inputs to the 1-bit FA). After the addition, when the next clock arrives, the LSBs of the two data will be shifted out of both registers. Instead, the bits located to the left of the LSBs will be shifted into the LSBs (Notice that both register A and register B are shift-right registers) and perform the addition. This is repeated for four clock cycles to complete 4-bit data addition. Also, you may notice that the output of the 1-bit FA is connected to the input, SI, of the register B. That means four summed bits are shifted into the register B clock-by-clock while the original data is shifted out of the register. Besides, the carry-out bit from the addition of the last clock cycle is held by its carry-hold flip-flop and fed into the FA as the carry-in bit for the current addition. The carryout bit of the current addition is sent to the carry-hold flip flop as the carry-in for the bit addition in the next clock cycle. To perform subtraction, the least significant bit of register B is run through a serial 2 s complement unit. A MUX is used to choose either the LSB of the register B, for addition, or the output of the 2 s complement unit, for subtraction, as input to the FA. The choice depends on the state of the ADDL_SUBH line (low for addition, high for subtraction). Also, a carry-hold flip-flop is used to hold the carry-out bit and feed the bit to the unit again as the carry-in for next bit. 2 Pre-Lab To calculate the 2's complement serially, use a single bit slice of your solution to Problem 6 in Chapter 4 (Homework 6 Problem 7) of the textbook in CSE 271. To design the SADDSUB circuit, you will need two 4-bit shift-right registers with parallel load/shift selector (LoagH_ShiftL), asynchronous active high reset (CLR), clock () and clock enable (CE), as well as one-bit full adder (FA). Notice that in this lab, your register only needs to perform right shifts (not left shifts). Figure 2 Positive-edge-triggered D flip-flop with asynchronous reset and clock enable. 2

3 To build the shift registers in your design, use the positive-edge-triggered D flip-flops (by the symbol FDCE as defined in the Xilinx ISE library, see Figure2). The function of the register is as follows: The CLR has highest priority. If the CLR is active (CLR=1), then the register data output Q is forced to zero. If the CLR is not active and the clock enable input CE is active (CE=1), then the register (according to positive edge of the clock ) remembers the value presented on the data input D. If the CE is not active, then the register holds its previous value. For the carry-hold flip flops, you can use the symbol, FDC, where the clock enable is 1. In the pre-lab, do the following tasks: 1. Draw a schematic called SREG for the 4-bit shift register. This register should have a data input D3~D0, serial data input (SI), clock input (), load input (LOADH_SHIFTL), clock enable input (CE), reset input (CLR), and parallel data out (Q3~Q0). The function of SREG should be as follows: The CLR has highest priority (resets the register). If both the CE and LOADH_SHIFTL are active, then on the rising edge of the clock, the register loads data D3~D0. If the LOADH_SHIFTL input is not active, then at the rising edge of the clock, the register shifts right, filling the vacant space with the serial input (SI) bit. If the input CE is inactive, then the register holds its value. Notice that the LSB of the data output Q0 is also the serial data output of the shift-right register and that serial data is shifted into the MSB of the register. 2. Draw a block diagram of the 2 complement unit. Include all necessary circuitry to generate the 2's complement serially. 3 In-lab In the lab, we will use Xilinx ISE software to draw, simulate, and implement the SADDSUB on the PLDT-3 board. 1. Create a new project. 2. Draw a schematic diagram of the shift-right register. Save this schematic diagram under name SREG. Use the ModelSim simulator to check if this circuit works correctly. Generate a symbol SREG for the shift register. 3. Draw a schematic diagram of the 2 s complement circuit. Save this schematic diagram under the name, TWOSCOMP. Use the ModelSim simulator to check if this circuit works correctly. Generate a symbol TWOSCOMP for the 2 s complement circuit. 4. Draw a schematic diagram of the entire serial adder/subtractor. Save this schematic diagram under the name SADDSUB. (You need to copy the schematic diagram, FA, from Lab 5, save it in the directory of your current project and add it to your current project.) The schematic should have ten inputs, CLR,, CE_A, CE_B, LOADH_SHIFTL, ADDH_SUBL, D3~D0, and eight outputs, QA3 ~ QA0, and QB3 ~ QB0. Use the ModelSim simulator to check if this circuit works correctly. Generate a symbol SADDSUB for this circuit. 5. Copy the code, hex2disp.sch, hex2disp.sym as well as seg_a.sch, seg_a.sym,, seg_g.sch, and seg_g.sym, developed in Lab 4 and add them into the current project. Check if the symbol, hex2disp, is in the project library. 3

4 6. Generate a new schematic, lab8, in the project. Place the symbols, SADDSUB and two hex2disps, on this schematic and connect the outputs of the QA3~QA0 and QB3~QB0 to the inputs of each of the hex2disp symbols. 7. Connect ibufs and obufs to all inputs and outputs. ate the inputs and outputs to the following pins of the PLDT-3 board. Input Table 1 Output (QA3~QA0) Output (QB3~QB0) CLR P53 a P57 a1 P15 P25 b P58 b1 P18 CE_A P11 c P61 c1 P23 CE_B P7 d P62 d1 P21 LoadH_ShiftL P6 e P63 e1 P19 ADDH_SUBL P5 f P65 f1 P14 D0 P1 g P66 g1 P17 D1 D2 D3 P2 P3 P4 8. Implement your circuit and download the generated programming data into the PLDT-3 board. 9. As you know in Lab 6 and Lab 7, the location of the pin, p53, is close to the DIP switch. We will use one input of the DIP switch as the reset input, CLR. So, you need to connect a wire between the DIP switch and the pin, p The clock bit is connected to the pin, p25. For this lab, since the operation is performed by one bit per clock cycle, the clock signal is very important. A normal push button may generate a bounce signal so that the serial adder/subtractor will misunderstand it as multiple clock cycles and jump over many steps. Therefore, it could be better for us to use debounced push button switches. The push button switches, S1 and S2 (The grey and yellow buttons), are built with debounced circuits. Connect the pin 25 to T4 (The yellow button). 11. The control signals, CE_A, CE_B, LOADH_SHIFTL, ADDL_SUBH as well as the input D3~D0 signals are connected the toggle switches S6 and S7, respectively. The results stored in the REGA register and the REGB register will be displayed on the left seven segment display and right seven segment display, respectively. Demonstrate the correct operation of your circuit to your lab instructor and have your instructor sign your lab8 schematic. 4

5 4 Lab Report In the result section of your final lab report, include the schematic diagrams: SREG, TWOSCOMP, SADDSUB and lab8. Show results of the simulations for the circuits, SREG, TWOSCOMP and SADDSUB (for simulation of SREG and SADDSUB, use the set of data given by the instructor; for TWOSCOMP, simulate the data from the complete truth table). Interpret the simulation results when necessary. 5