Versatile IO Circuit Schemes for LPDDR4 with 1.8mW/Gbps/pin Power Efficiency. Kyoung-Hoi Koo
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1 Versatile IO Circuit Schemes for LPDDR4 with 1.8mW/Gbps/pin Power Efficiency Kyoung-Hoi Koo
2 Outline Introduction for LPDDR4 Channel Sensitivity Analysis Backward Compatibility Summary
3 Rapid Technology Revolution
4 Outline Introduction for LPDDR4 Channel Sensitivity Analysis Backward Compatibility Summary
5 Mobile DRAM Power Requirements A great user experience requires great power efficiency Phones are targeting 10+ days of standby Tablets in connected standby targeting 2+ weeks Ultrabooks require always on, always connected power state,<5 battery drain within 16 hours Memory consumers up to 30% of the system power in standby modes Energy per Bit(pJ) Total Bandwidth(GB/s) Energy per Bit(pJ) Bandwidth(GB/s) LPDDR LPDDR2 LPDDR3 LPDDR4 Source : JEDEC, 2013 Active and Standby power are critical for mobile platforms
6 Low Power DRAM Bandwidth LPDDR3(x64) BW target is 17 GB/s Evolutionary successor to LPDDR2 Data rate up to 2133Mbps DDR Wide IO(x512) BW target is 17GB/s Limited performance scalability Data rate up to 266Mbps SDR LPDDR4(x64) BW target is 34GB/s Scalable performance Data rate up to 4.2Gbps DDR WIO2(x256) BW target is 34 GB/s Scalable performance Stacked-die configuration(x512, 68GB/s) Data rate up to 1066Mbps DDR Source : JEDEC, 2013
7 LPDDR4 vs. DDR4 Comparison Attribute LPDDR4 DDR4 Target Market Mobile Devices Laptop,PC,Server Die Architecture 2chX16 1chX16 IO Spec. ~350mV LVSTL POD_12 DLL in Dram No Yes Termination CI/O <1.0pF >1.0pF C/A 6pin SDR CA bus 22pins Topology Point-to-point PoP&MCP DIMM Max. Frequency 3.2Gbps/4.2Gbps 3.2Gbps Low Frequency operation Yes Target Supply 1.1V(1.0V) 1.2V Yes (DLL off <125MHz) Source : JEDEC, 2013
8 Signaling Difference(LP3 vs. LP4) (1.2V) RTERM Vref LPDDR3 Signaling (1.1V) IPU Vref RTERM LPDDR4 Signaling
9 LVSTL Signaling Level (1.2V) Pull-up drive case IPU=k(-Vth) r Vx VOH=-Vth (w/o RTERM) RTERM VOH VOH= IPUXRTERM =/3 or /2.5 Vref=0.5*VOH (1.2V) Pull-down drive case Vx RTERM IRTERM =VOH / RTERM VOH= IPUXRTERM =/3 or /2.5 Vref=0.5*VOH
10 Driver Scheme for Ultra Low Ci/o Receiver end Cap. causes signal distortion Ci/o portion Driver : ~40% Receiver : ~5% ESD : ~30% Cio=0.5345pF Parasitic: ~25% Low Ci/o driver scheme VOH Cio=0.4553pF Slew rate Pull-up unit : Voh level Cio=0.4236pF Pull-down unit : slew-rate Target Ci/o value : 0.5~0.7pF
11 Special pre-driver/driver Control Scheme Proposed scheme for duty balance and minimized SSON Independent pull-up and pull-down control 1x 1x PU PU 1x PD PD Conventional scheme Proposed scheme PAD PU control PD control pre-driver control timing
12 Fast Boost Reference Generator A wide range reference generator is required to support w/o Voh calibration, w/ Voh calibration, un-termination mode Fast setting time for reference voltage change =1.0 =1.1V VOH Boundary V Vref Vref /3-15% % /2.5-15% % /3-30% % /2.5-30% % Condition w/ VOH calibration w/o VOH calibration Un-Termination Voltage selector + - Boosting circuit Mode selector Vref
13 Calibration Circuit A wide range reference generator is required to support w/o Voh calibration, w/ Voh calibration, un-termination mode Fast setting time for reference voltage change Short calibration time for on-time P/V/T variation tracking 240ohm FSM N Pull-up Array calibrated code for VOH + - *VREF + - Pull-down Array N FSM Pull-down Array calibrated code for -TERM 1 st calibration-loop 2 nd calibration-loop
14 Outline Introduction for LPDDR4 Channel Sensitivity Analysis Backward Compatibility Summary
15 Channel Sensitivity Analysis Channel sensitivity analysis using DOE PKG length and Ci/o are most sensitive design parameters
16 Channel Sensitivity Analysis-cont. Considering power consumption weak ODT, low Ci/o is recommend weak ODT, low Ci/o, short AP Length weak ODT, high Ci/o, long AP Length strong ODT, low Ci/o, short AP Length strong ODT, high Ci/o, long AP Length
17 On-die De-cap. Estimation Cost effective on-die de-cap estimation method is required No de-cap 1x de-cap 2x de-cap 3x de-cap 4x de-cap +81ps +91ps +92ps +92ps ODT 120ohm ODT 60ohm saturation point saturation point 0pF x1 x2 x3 x4 x5 x6 x7 x8 x9 0pF x1 x2 x3 x4 x5 x6 x7 x8 x9
18 Lower Voltage Operation For ultra low power consumption, lower voltage operation should be verified ~4% timing margin degradation is expected under 1.0V conditions Short channel length (AP-Memory) is required to ensure more timing margin =1.1V Eye Opening Difference =1.0V Short channel Long channel Short channel Long channel Fast corner Slow corner
19 Case Study for PKG. Spacing Wider AP PKG. spacing securing ~14% eye-opening 2x spacing 1x spacing Difference Fast corner Slow corner Fast corner Slow corner Short channel Long channel Short channel Long channel Strong ODT Weak ODT 2x spacing 1x spacing 14%
20 Outline Introduction for LPDDR4 Channel Sensitivity Analysis Backward Compatibility Summary
21 Signaling Features(LP3 vs. LP4) (1.2V) PMOS pull-up : large pre-driver size RTERM Vref Termination Large swing LPDDR3 Signaling Large current consumption Large SSN & X-talk (1.1V) IPU Vref RTERM NMOS pull-up : small pre-driver size VOHmax=-Vth VOH=Ipu*Rterm LPDDR4 Signaling Reduced Cio Small swing, small SSN & X-talk
22 How to Combine LP3/LP4 Driver -1.2V -0.8V -TERM -TERM Pull-up PG Pull-up PG Pull-up PG2 Pull-up2 Pull-down NG Pull-down Change the level? Performance degradation Mismatch in signaling level Change the pull-up driver? Area overhead Ci/o increase
23 Proposed LP3/LP4 Driver Schemes
24 Outline Introduction for LPDDR4 Channel Sensitivity Analysis Backward Compatibility Summary
25 Summary Versatile schemes for 3.2Gbps LPDDR4 interface Ultra low(0.5~0.7pf) Ci/o driver scheme Special pre-driver/driver control scheme Internal Vref. generation with fast boost -TERM and Voh calibration Channel sensitivity analysis DOE analysis On-die de-cap. estimation Lower operation AP PKG. spacing study
26 Summary-cont. Backward Compatibility Differentiated MKT. solution for controller side Proposed LP3/LP4 compatible driver scheme
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